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35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0,
116 ATOM_SCALER_CENTER =1,
117 ATOM_SCALER_EXPANSION =2,
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type{
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM = 0x60,
183};
184
185enum atom_dp_vs_preemph_def{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
196};
197
198
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206
207#pragma pack(1)
208
209enum atombios_image_offset{
210OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
211OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
212OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
213MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20,
214OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
215OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
216};
217
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223
224struct atom_common_table_header
225{
226 uint16_t structuresize;
227 uint8_t format_revision;
228 uint8_t content_revision;
229};
230
231
232
233
234struct atom_rom_header_v2_2
235{
236 struct atom_common_table_header table_header;
237 uint8_t atom_bios_string[4];
238 uint16_t bios_segment_address;
239 uint16_t protectedmodeoffset;
240 uint16_t configfilenameoffset;
241 uint16_t crc_block_offset;
242 uint16_t vbios_bootupmessageoffset;
243 uint16_t int10_offset;
244 uint16_t pcibusdevinitcode;
245 uint16_t iobaseaddress;
246 uint16_t subsystem_vendor_id;
247 uint16_t subsystem_id;
248 uint16_t pci_info_offset;
249 uint16_t masterhwfunction_offset;
250 uint16_t masterdatatable_offset;
251 uint16_t reserved;
252 uint32_t pspdirtableoffset;
253};
254
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257
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261
262
263struct atom_master_list_of_command_functions_v2_1{
264 uint16_t asic_init;
265 uint16_t cmd_function1;
266 uint16_t cmd_function2;
267 uint16_t cmd_function3;
268 uint16_t digxencodercontrol;
269 uint16_t cmd_function5;
270 uint16_t cmd_function6;
271 uint16_t cmd_function7;
272 uint16_t cmd_function8;
273 uint16_t cmd_function9;
274 uint16_t setengineclock;
275 uint16_t setmemoryclock;
276 uint16_t setpixelclock;
277 uint16_t enabledisppowergating;
278 uint16_t cmd_function14;
279 uint16_t cmd_function15;
280 uint16_t cmd_function16;
281 uint16_t cmd_function17;
282 uint16_t cmd_function18;
283 uint16_t cmd_function19;
284 uint16_t cmd_function20;
285 uint16_t cmd_function21;
286 uint16_t cmd_function22;
287 uint16_t cmd_function23;
288 uint16_t cmd_function24;
289 uint16_t cmd_function25;
290 uint16_t cmd_function26;
291 uint16_t cmd_function27;
292 uint16_t cmd_function28;
293 uint16_t cmd_function29;
294 uint16_t cmd_function30;
295 uint16_t cmd_function31;
296 uint16_t cmd_function32;
297 uint16_t cmd_function33;
298 uint16_t blankcrtc;
299 uint16_t enablecrtc;
300 uint16_t cmd_function36;
301 uint16_t cmd_function37;
302 uint16_t cmd_function38;
303 uint16_t cmd_function39;
304 uint16_t cmd_function40;
305 uint16_t getsmuclockinfo;
306 uint16_t selectcrtc_source;
307 uint16_t cmd_function43;
308 uint16_t cmd_function44;
309 uint16_t cmd_function45;
310 uint16_t setdceclock;
311 uint16_t getmemoryclock;
312 uint16_t getengineclock;
313 uint16_t setcrtc_usingdtdtiming;
314 uint16_t externalencodercontrol;
315 uint16_t cmd_function51;
316 uint16_t cmd_function52;
317 uint16_t cmd_function53;
318 uint16_t processi2cchanneltransaction;
319 uint16_t cmd_function55;
320 uint16_t cmd_function56;
321 uint16_t cmd_function57;
322 uint16_t cmd_function58;
323 uint16_t cmd_function59;
324 uint16_t computegpuclockparam;
325 uint16_t cmd_function61;
326 uint16_t cmd_function62;
327 uint16_t dynamicmemorysettings;
328 uint16_t memorytraining;
329 uint16_t cmd_function65;
330 uint16_t cmd_function66;
331 uint16_t setvoltage;
332 uint16_t cmd_function68;
333 uint16_t readefusevalue;
334 uint16_t cmd_function70;
335 uint16_t cmd_function71;
336 uint16_t cmd_function72;
337 uint16_t cmd_function73;
338 uint16_t cmd_function74;
339 uint16_t cmd_function75;
340 uint16_t dig1transmittercontrol;
341 uint16_t cmd_function77;
342 uint16_t processauxchanneltransaction;
343 uint16_t cmd_function79;
344 uint16_t getvoltageinfo;
345};
346
347struct atom_master_command_function_v2_1
348{
349 struct atom_common_table_header table_header;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
351};
352
353
354
355
356struct atom_function_attribute
357{
358 uint16_t ws_in_bytes:8;
359 uint16_t ps_in_bytes:7;
360 uint16_t updated_by_util:1;
361};
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363
364
365
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367
368
369struct atom_rom_hw_function_header
370{
371 struct atom_common_table_header func_header;
372 struct atom_function_attribute func_attrib;
373};
374
375
376
377
378
379
380
381struct atom_master_list_of_data_tables_v2_1{
382 uint16_t utilitypipeline;
383 uint16_t multimedia_info;
384 uint16_t smc_dpm_info;
385 uint16_t sw_datatable3;
386 uint16_t firmwareinfo;
387 uint16_t sw_datatable5;
388 uint16_t lcd_info;
389 uint16_t sw_datatable7;
390 uint16_t smu_info;
391 uint16_t sw_datatable9;
392 uint16_t sw_datatable10;
393 uint16_t vram_usagebyfirmware;
394 uint16_t gpio_pin_lut;
395 uint16_t sw_datatable13;
396 uint16_t gfx_info;
397 uint16_t powerplayinfo;
398 uint16_t sw_datatable16;
399 uint16_t sw_datatable17;
400 uint16_t sw_datatable18;
401 uint16_t sw_datatable19;
402 uint16_t sw_datatable20;
403 uint16_t sw_datatable21;
404 uint16_t displayobjectinfo;
405 uint16_t indirectioaccess;
406 uint16_t umc_info;
407 uint16_t sw_datatable25;
408 uint16_t sw_datatable26;
409 uint16_t dce_info;
410 uint16_t vram_info;
411 uint16_t sw_datatable29;
412 uint16_t integratedsysteminfo;
413 uint16_t asic_profiling_info;
414 uint16_t voltageobject_info;
415 uint16_t sw_datatable33;
416 uint16_t sw_datatable34;
417};
418
419
420struct atom_master_data_table_v2_1
421{
422 struct atom_common_table_header table_header;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
424};
425
426
427struct atom_dtd_format
428{
429 uint16_t pixclk;
430 uint16_t h_active;
431 uint16_t h_blanking_time;
432 uint16_t v_active;
433 uint16_t v_blanking_time;
434 uint16_t h_sync_offset;
435 uint16_t h_sync_width;
436 uint16_t v_sync_offset;
437 uint16_t v_syncwidth;
438 uint16_t reserved;
439 uint16_t reserved0;
440 uint8_t h_border;
441 uint8_t v_border;
442 uint16_t miscinfo;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
445};
446
447
448enum atom_dtd_format_modemiscinfo{
449 ATOM_HSYNC_POLARITY = 0x0002,
450 ATOM_VSYNC_POLARITY = 0x0004,
451 ATOM_H_REPLICATIONBY2 = 0x0010,
452 ATOM_V_REPLICATIONBY2 = 0x0020,
453 ATOM_INTERLACE = 0x0080,
454 ATOM_COMPOSITESYNC = 0x0040,
455};
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469
470struct atom_firmware_info_v3_1
471{
472 struct atom_common_table_header table_header;
473 uint32_t firmware_revision;
474 uint32_t bootup_sclk_in10khz;
475 uint32_t bootup_mclk_in10khz;
476 uint32_t firmware_capability;
477 uint32_t main_call_parser_entry;
478 uint32_t bios_scratch_reg_startaddr;
479 uint16_t bootup_vddc_mv;
480 uint16_t bootup_vddci_mv;
481 uint16_t bootup_mvddc_mv;
482 uint16_t bootup_vddgfx_mv;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id;
485 uint8_t reserved1[2];
486 uint32_t mc_baseaddr_high;
487 uint32_t mc_baseaddr_low;
488 uint32_t reserved2[6];
489};
490
491
492enum atombios_firmware_capability
493{
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
497};
498
499enum atom_cooling_solution_id{
500 AIR_COOLING = 0x00,
501 LIQUID_COOLING = 0x01
502};
503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability;
510 uint32_t main_call_parser_entry;
511 uint32_t bios_scratch_reg_startaddr;
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id;
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id;
522 uint8_t board_i2c_feature_gpio_id;
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
530
531
532
533
534
535
536
537struct lcd_info_v2_1
538{
539 struct atom_common_table_header table_header;
540 struct atom_dtd_format lcd_timing;
541 uint16_t backlight_pwm;
542 uint16_t special_handle_cap;
543 uint16_t panel_misc;
544 uint16_t lvds_max_slink_pclk;
545 uint16_t lvds_ss_percentage;
546 uint16_t lvds_ss_rate_10hz;
547 uint8_t pwr_on_digon_to_de;
548 uint8_t pwr_on_de_to_vary_bl;
549 uint8_t pwr_down_vary_bloff_to_de;
550 uint8_t pwr_down_de_to_digoff;
551 uint8_t pwr_off_delay;
552 uint8_t pwr_on_vary_bl_to_blon;
553 uint8_t pwr_down_bloff_to_vary_bloff;
554 uint8_t panel_bpc;
555 uint8_t dpcd_edp_config_cap;
556 uint8_t dpcd_max_link_rate;
557 uint8_t dpcd_max_lane_count;
558 uint8_t dpcd_max_downspread;
559 uint8_t min_allowed_bl_level;
560 uint8_t max_allowed_bl_level;
561 uint8_t bootup_bl_level;
562 uint8_t dplvdsrxid;
563 uint32_t reserved1[8];
564};
565
566
567enum atom_lcd_info_panel_misc{
568 ATOM_PANEL_MISC_FPDI =0x0002,
569};
570
571
572enum atom_lcd_info_dptolvds_rx_id
573{
574 eDP_TO_LVDS_RX_DISABLE = 0x00,
575 eDP_TO_LVDS_COMMON_ID = 0x01,
576 eDP_TO_LVDS_REALTEK_ID = 0x02,
577};
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579
580
581
582
583
584
585
586struct atom_gpio_pin_assignment
587{
588 uint32_t data_a_reg_index;
589 uint8_t gpio_bitshift;
590 uint8_t gpio_mask_bitshift;
591 uint8_t gpio_id;
592 uint8_t reserved;
593};
594
595
596enum atom_gpio_pin_assignment_gpio_id {
597 I2C_HW_LANE_MUX =0x0f,
598 I2C_HW_ENGINE_ID_MASK =0x70,
599 I2C_HW_CAP =0x80,
600
601
602
603 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
604
605 PP_AC_DC_SWITCH_GPIO_PINID = 60,
606
607 VDDC_VRHOT_GPIO_PINID = 61,
608
609 VDDC_PCC_GPIO_PINID = 62,
610
611 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
612
613 DRAM_SELF_REFRESH_GPIO_PINID = 64,
614
615 THERMAL_INT_OUTPUT_GPIO_PINID =65,
616};
617
618
619struct atom_gpio_pin_lut_v2_1
620{
621 struct atom_common_table_header table_header;
622
623 struct atom_gpio_pin_assignment gpio_pin[8];
624};
625
626
627
628
629
630
631
632
633struct vram_usagebyfirmware_v2_1
634{
635 struct atom_common_table_header table_header;
636 uint32_t start_address_in_kb;
637 uint16_t used_by_firmware_in_kb;
638 uint16_t used_by_driver_in_kb;
639};
640
641
642
643
644
645
646
647
648enum atom_object_record_type_id
649{
650 ATOM_I2C_RECORD_TYPE =1,
651 ATOM_HPD_INT_RECORD_TYPE =2,
652 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
653 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
654 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
655 ATOM_ENCODER_CAP_RECORD_TYPE=20,
656 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
657 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
658 ATOM_RECORD_END_TYPE =0xFF,
659};
660
661struct atom_common_record_header
662{
663 uint8_t record_type;
664 uint8_t record_size;
665};
666
667struct atom_i2c_record
668{
669 struct atom_common_record_header record_header;
670 uint8_t i2c_id;
671 uint8_t i2c_slave_addr;
672};
673
674struct atom_hpd_int_record
675{
676 struct atom_common_record_header record_header;
677 uint8_t pin_id;
678 uint8_t plugin_pin_state;
679};
680
681
682enum atom_encoder_caps_def
683{
684 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01,
685 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01,
686 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02,
687 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04,
688 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08,
689};
690
691struct atom_encoder_caps_record
692{
693 struct atom_common_record_header record_header;
694 uint32_t encodercaps;
695};
696
697enum atom_connector_caps_def
698{
699 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01,
700 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02,
701};
702
703struct atom_disp_connector_caps_record
704{
705 struct atom_common_record_header record_header;
706 uint32_t connectcaps;
707};
708
709
710struct atom_gpio_pin_control_pair
711{
712 uint8_t gpio_id;
713 uint8_t gpio_pinstate;
714};
715
716struct atom_object_gpio_cntl_record
717{
718 struct atom_common_record_header record_header;
719 uint8_t flag;
720 uint8_t number_of_pins;
721 struct atom_gpio_pin_control_pair gpio[1];
722};
723
724
725enum atom_gpio_pin_control_pinstate_def
726{
727 GPIO_PIN_TYPE_INPUT = 0x00,
728 GPIO_PIN_TYPE_OUTPUT = 0x10,
729 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
730
731
732 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
733 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
734 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
735 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
736};
737
738
739
740enum atom_glsync_record_gpio_index_def
741{
742 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
743 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
744 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
745 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
746 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
747 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
748 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
749 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
750 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
751 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
752};
753
754
755struct atom_connector_hpdpin_lut_record
756{
757 struct atom_common_record_header record_header;
758 uint8_t hpd_pin_map[8];
759};
760
761struct atom_connector_auxddc_lut_record
762{
763 struct atom_common_record_header record_header;
764 uint8_t aux_ddc_map[8];
765};
766
767struct atom_connector_forced_tmds_cap_record
768{
769 struct atom_common_record_header record_header;
770
771 uint8_t maxtmdsclkrate_in2_5mhz;
772 uint8_t reserved;
773};
774
775struct atom_connector_layout_info
776{
777 uint16_t connectorobjid;
778 uint8_t connector_type;
779 uint8_t position;
780};
781
782
783enum atom_connector_layout_info_connector_type_def
784{
785 CONNECTOR_TYPE_DVI_D = 1,
786
787 CONNECTOR_TYPE_HDMI = 4,
788 CONNECTOR_TYPE_DISPLAY_PORT = 5,
789 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
790};
791
792struct atom_bracket_layout_record
793{
794 struct atom_common_record_header record_header;
795 uint8_t bracketlen;
796 uint8_t bracketwidth;
797 uint8_t conn_num;
798 uint8_t reserved;
799 struct atom_connector_layout_info conn_info[1];
800};
801
802enum atom_display_device_tag_def{
803 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002,
804 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
805 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
806 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
807 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
808 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
809 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
810 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
811};
812
813struct atom_display_object_path_v2
814{
815 uint16_t display_objid;
816 uint16_t disp_recordoffset;
817 uint16_t encoderobjid;
818 uint16_t extencoderobjid;
819 uint16_t encoder_recordoffset;
820 uint16_t extencoder_recordoffset;
821 uint16_t device_tag;
822 uint8_t priority_id;
823 uint8_t reserved;
824};
825
826struct display_object_info_table_v1_4
827{
828 struct atom_common_table_header table_header;
829 uint16_t supporteddevices;
830 uint8_t number_of_path;
831 uint8_t reserved;
832 struct atom_display_object_path_v2 display_path[8];
833};
834
835
836
837
838
839
840
841struct atom_display_controller_info_v4_1
842{
843 struct atom_common_table_header table_header;
844 uint32_t display_caps;
845 uint32_t bootup_dispclk_10khz;
846 uint16_t dce_refclk_10khz;
847 uint16_t i2c_engine_refclk_10khz;
848 uint16_t dvi_ss_percentage;
849 uint16_t dvi_ss_rate_10hz;
850 uint16_t hdmi_ss_percentage;
851 uint16_t hdmi_ss_rate_10hz;
852 uint16_t dp_ss_percentage;
853 uint16_t dp_ss_rate_10hz;
854 uint8_t dvi_ss_mode;
855 uint8_t hdmi_ss_mode;
856 uint8_t dp_ss_mode;
857 uint8_t ss_reserved;
858 uint8_t hardcode_mode_num;
859 uint8_t reserved1[3];
860 uint16_t dpphy_refclk_10khz;
861 uint16_t reserved2;
862 uint8_t dceip_min_ver;
863 uint8_t dceip_max_ver;
864 uint8_t max_disp_pipe_num;
865 uint8_t max_vbios_active_disp_pipe_num;
866 uint8_t max_ppll_num;
867 uint8_t max_disp_phy_num;
868 uint8_t max_aux_pairs;
869 uint8_t remotedisplayconfig;
870 uint8_t reserved3[8];
871};
872
873
874struct atom_display_controller_info_v4_2
875{
876 struct atom_common_table_header table_header;
877 uint32_t display_caps;
878 uint32_t bootup_dispclk_10khz;
879 uint16_t dce_refclk_10khz;
880 uint16_t i2c_engine_refclk_10khz;
881 uint16_t dvi_ss_percentage;
882 uint16_t dvi_ss_rate_10hz;
883 uint16_t hdmi_ss_percentage;
884 uint16_t hdmi_ss_rate_10hz;
885 uint16_t dp_ss_percentage;
886 uint16_t dp_ss_rate_10hz;
887 uint8_t dvi_ss_mode;
888 uint8_t hdmi_ss_mode;
889 uint8_t dp_ss_mode;
890 uint8_t ss_reserved;
891 uint8_t dfp_hardcode_mode_num;
892 uint8_t dfp_hardcode_refreshrate;
893 uint8_t vga_hardcode_mode_num;
894 uint8_t vga_hardcode_refreshrate;
895 uint16_t dpphy_refclk_10khz;
896 uint16_t reserved2;
897 uint8_t dcnip_min_ver;
898 uint8_t dcnip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
906};
907
908
909enum dce_info_caps_def
910{
911
912 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
913
914 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
915
916 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
917
918};
919
920
921
922
923
924
925struct atom_ext_display_path
926{
927 uint16_t device_tag;
928 uint16_t device_acpi_enum;
929 uint16_t connectorobjid;
930 uint8_t auxddclut_index;
931 uint8_t hpdlut_index;
932 uint16_t ext_encoder_objid;
933 uint8_t channelmapping;
934 uint8_t chpninvert;
935 uint16_t caps;
936 uint16_t reserved;
937};
938
939
940enum ext_display_path_cap_def
941{
942 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
943 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
944 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
945};
946
947struct atom_external_display_connection_info
948{
949 struct atom_common_table_header table_header;
950 uint8_t guid[16];
951 struct atom_ext_display_path path[7];
952 uint8_t checksum;
953 uint8_t stereopinid;
954 uint8_t remotedisplayconfig;
955 uint8_t edptolvdsrxid;
956 uint8_t fixdpvoltageswing;
957 uint8_t reserved[3];
958};
959
960
961
962
963
964
965
966struct atom_camera_dphy_timing_param
967{
968 uint8_t profile_id;
969 uint32_t param;
970};
971
972struct atom_camera_dphy_elec_param
973{
974 uint16_t param[3];
975};
976
977struct atom_camera_module_info
978{
979 uint8_t module_id;
980 uint8_t module_name[8];
981 struct atom_camera_dphy_timing_param timingparam[6];
982};
983
984struct atom_camera_flashlight_info
985{
986 uint8_t flashlight_id;
987 uint8_t name[8];
988};
989
990struct atom_camera_data
991{
992 uint32_t versionCode;
993 struct atom_camera_module_info cameraInfo[3];
994 struct atom_camera_flashlight_info flashInfo;
995 struct atom_camera_dphy_elec_param dphy_param;
996 uint32_t crc_val;
997};
998
999
1000struct atom_14nm_dpphy_dvihdmi_tuningset
1001{
1002 uint32_t max_symclk_in10khz;
1003 uint8_t encoder_mode;
1004 uint8_t phy_sel;
1005 uint16_t margindeemph;
1006 uint8_t deemph_6db_4;
1007 uint8_t boostadj;
1008 uint8_t tx_driver_fifty_ohms;
1009 uint8_t deemph_sel;
1010};
1011
1012struct atom_14nm_dpphy_dp_setting{
1013 uint8_t dp_vs_pemph_level;
1014 uint16_t margindeemph;
1015 uint8_t deemph_6db_4;
1016 uint8_t boostadj;
1017};
1018
1019struct atom_14nm_dpphy_dp_tuningset{
1020 uint8_t phy_sel;
1021 uint8_t version;
1022 uint16_t table_size;
1023 uint16_t reserved;
1024 struct atom_14nm_dpphy_dp_setting dptuning[10];
1025};
1026
1027struct atom_14nm_dig_transmitter_info_header_v4_0{
1028 struct atom_common_table_header table_header;
1029 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset;
1030 uint16_t uniphy_vs_emph_lookup_table_offset;
1031 uint16_t uniphy_xbar_settings_table_offset;
1032};
1033
1034struct atom_14nm_combphy_tmds_vs_set
1035{
1036 uint8_t sym_clk;
1037 uint8_t dig_mode;
1038 uint8_t phy_sel;
1039 uint16_t common_mar_deemph_nom__margin_deemph_val;
1040 uint8_t common_seldeemph60__deemph_6db_4_val;
1041 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1042 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1043 uint8_t margin_deemph_lane0__deemph_sel_val;
1044};
1045
1046struct atom_i2c_reg_info {
1047 uint8_t ucI2cRegIndex;
1048 uint8_t ucI2cRegVal;
1049};
1050
1051struct atom_hdmi_retimer_redriver_set {
1052 uint8_t HdmiSlvAddr;
1053 uint8_t HdmiRegNum;
1054 uint8_t Hdmi6GRegNum;
1055 struct atom_i2c_reg_info HdmiRegSetting[9];
1056 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];
1057};
1058
1059struct atom_integrated_system_info_v1_11
1060{
1061 struct atom_common_table_header table_header;
1062 uint32_t vbios_misc;
1063 uint32_t gpucapinfo;
1064 uint32_t system_config;
1065 uint32_t cpucapinfo;
1066 uint16_t gpuclk_ss_percentage;
1067 uint16_t gpuclk_ss_type;
1068 uint16_t lvds_ss_percentage;
1069 uint16_t lvds_ss_rate_10hz;
1070 uint16_t hdmi_ss_percentage;
1071 uint16_t hdmi_ss_rate_10hz;
1072 uint16_t dvi_ss_percentage;
1073 uint16_t dvi_ss_rate_10hz;
1074 uint16_t dpphy_override;
1075 uint16_t lvds_misc;
1076 uint16_t backlight_pwm_hz;
1077 uint8_t memorytype;
1078 uint8_t umachannelnumber;
1079 uint8_t pwr_on_digon_to_de;
1080 uint8_t pwr_on_de_to_vary_bl;
1081 uint8_t pwr_down_vary_bloff_to_de;
1082 uint8_t pwr_down_de_to_digoff;
1083 uint8_t pwr_off_delay;
1084 uint8_t pwr_on_vary_bl_to_blon;
1085 uint8_t pwr_down_bloff_to_vary_bloff;
1086 uint8_t min_allowed_bl_level;
1087 struct atom_external_display_connection_info extdispconninfo;
1088 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1089 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1090 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1091 struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
1092 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
1093 struct atom_camera_data camera_info;
1094 struct atom_hdmi_retimer_redriver_set dp0_retimer_set;
1095 struct atom_hdmi_retimer_redriver_set dp1_retimer_set;
1096 struct atom_hdmi_retimer_redriver_set dp2_retimer_set;
1097 struct atom_hdmi_retimer_redriver_set dp3_retimer_set;
1098 uint32_t reserved[108];
1099};
1100
1101
1102
1103enum atom_system_vbiosmisc_def{
1104 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1105};
1106
1107
1108
1109enum atom_system_gpucapinf_def{
1110 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1111};
1112
1113
1114enum atom_sysinfo_dpphy_override_def{
1115 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1116 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1117 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1118 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1119 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1120};
1121
1122
1123enum atom_sys_info_lvds_misc_def
1124{
1125 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1126 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1127 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1128};
1129
1130
1131
1132enum atom_dmi_t17_mem_type_def{
1133 OtherMemType = 0x01,
1134 UnknownMemType,
1135 DramMemType,
1136 EdramMemType,
1137 VramMemType,
1138 SramMemType,
1139 RamMemType,
1140 RomMemType,
1141 FlashMemType,
1142 EepromMemType,
1143 FepromMemType,
1144 EpromMemType,
1145 CdramMemType,
1146 ThreeDramMemType,
1147 SdramMemType,
1148 SgramMemType,
1149 RdramMemType,
1150 DdrMemType,
1151 Ddr2MemType,
1152 Ddr2FbdimmMemType,
1153 Ddr3MemType = 0x18,
1154 Fbd2MemType,
1155 Ddr4MemType,
1156 LpDdrMemType,
1157 LpDdr2MemType,
1158 LpDdr3MemType,
1159 LpDdr4MemType,
1160};
1161
1162
1163
1164struct atom_fusion_system_info_v4
1165{
1166 struct atom_integrated_system_info_v1_11 sysinfo;
1167 uint32_t powerplayinfo[256];
1168};
1169
1170
1171
1172
1173
1174
1175
1176
1177struct atom_gfx_info_v2_2
1178{
1179 struct atom_common_table_header table_header;
1180 uint8_t gfxip_min_ver;
1181 uint8_t gfxip_max_ver;
1182 uint8_t max_shader_engines;
1183 uint8_t max_tile_pipes;
1184 uint8_t max_cu_per_sh;
1185 uint8_t max_sh_per_se;
1186 uint8_t max_backends_per_se;
1187 uint8_t max_texture_channel_caches;
1188 uint32_t regaddr_cp_dma_src_addr;
1189 uint32_t regaddr_cp_dma_src_addr_hi;
1190 uint32_t regaddr_cp_dma_dst_addr;
1191 uint32_t regaddr_cp_dma_dst_addr_hi;
1192 uint32_t regaddr_cp_dma_command;
1193 uint32_t regaddr_cp_status;
1194 uint32_t regaddr_rlc_gpu_clock_32;
1195 uint32_t rlc_gpu_timer_refclk;
1196};
1197
1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
1221
1222struct atom_gfx_info_v2_4 {
1223 struct atom_common_table_header table_header;
1224 uint8_t gfxip_min_ver;
1225 uint8_t gfxip_max_ver;
1226 uint8_t gc_num_se;
1227 uint8_t max_tile_pipes;
1228 uint8_t gc_num_cu_per_sh;
1229 uint8_t gc_num_sh_per_se;
1230 uint8_t gc_num_rb_per_se;
1231 uint8_t gc_num_tccs;
1232 uint32_t regaddr_cp_dma_src_addr;
1233 uint32_t regaddr_cp_dma_src_addr_hi;
1234 uint32_t regaddr_cp_dma_dst_addr;
1235 uint32_t regaddr_cp_dma_dst_addr_hi;
1236 uint32_t regaddr_cp_dma_command;
1237 uint32_t regaddr_cp_status;
1238 uint32_t regaddr_rlc_gpu_clock_32;
1239 uint32_t rlc_gpu_timer_refclk;
1240 uint8_t active_cu_per_sh;
1241 uint8_t active_rb_per_se;
1242 uint16_t gcgoldenoffset;
1243 uint16_t gc_num_gprs;
1244 uint16_t gc_gsprim_buff_depth;
1245 uint16_t gc_parameter_cache_depth;
1246 uint16_t gc_wave_size;
1247 uint16_t gc_max_waves_per_simd;
1248 uint16_t gc_lds_size;
1249 uint8_t gc_num_max_gs_thds;
1250 uint8_t gc_gs_table_depth;
1251 uint8_t gc_double_offchip_lds_buffer;
1252 uint8_t gc_max_scratch_slots_per_cu;
1253 uint32_t sram_rm_fuses_val;
1254 uint32_t sram_custom_rm_fuses_val;
1255};
1256
1257
1258
1259
1260
1261
1262struct atom_smu_info_v3_1
1263{
1264 struct atom_common_table_header table_header;
1265 uint8_t smuip_min_ver;
1266 uint8_t smuip_max_ver;
1267 uint8_t smu_rsd1;
1268 uint8_t gpuclk_ss_mode;
1269 uint16_t sclk_ss_percentage;
1270 uint16_t sclk_ss_rate_10hz;
1271 uint16_t gpuclk_ss_percentage;
1272 uint16_t gpuclk_ss_rate_10hz;
1273 uint32_t core_refclk_10khz;
1274 uint8_t ac_dc_gpio_bit;
1275 uint8_t ac_dc_polarity;
1276 uint8_t vr0hot_gpio_bit;
1277 uint8_t vr0hot_polarity;
1278 uint8_t vr1hot_gpio_bit;
1279 uint8_t vr1hot_polarity;
1280 uint8_t fw_ctf_gpio_bit;
1281 uint8_t fw_ctf_polarity;
1282};
1283
1284struct atom_smu_info_v3_2 {
1285 struct atom_common_table_header table_header;
1286 uint8_t smuip_min_ver;
1287 uint8_t smuip_max_ver;
1288 uint8_t smu_rsd1;
1289 uint8_t gpuclk_ss_mode;
1290 uint16_t sclk_ss_percentage;
1291 uint16_t sclk_ss_rate_10hz;
1292 uint16_t gpuclk_ss_percentage;
1293 uint16_t gpuclk_ss_rate_10hz;
1294 uint32_t core_refclk_10khz;
1295 uint8_t ac_dc_gpio_bit;
1296 uint8_t ac_dc_polarity;
1297 uint8_t vr0hot_gpio_bit;
1298 uint8_t vr0hot_polarity;
1299 uint8_t vr1hot_gpio_bit;
1300 uint8_t vr1hot_polarity;
1301 uint8_t fw_ctf_gpio_bit;
1302 uint8_t fw_ctf_polarity;
1303 uint8_t pcc_gpio_bit;
1304 uint8_t pcc_gpio_polarity;
1305 uint16_t smugoldenoffset;
1306 uint32_t gpupll_vco_freq_10khz;
1307 uint32_t bootup_smnclk_10khz;
1308 uint32_t bootup_socclk_10khz;
1309 uint32_t bootup_mp0clk_10khz;
1310 uint32_t bootup_mp1clk_10khz;
1311 uint32_t bootup_lclk_10khz;
1312 uint32_t bootup_dcefclk_10khz;
1313 uint32_t ctf_threshold_override_value;
1314 uint32_t reserved[5];
1315};
1316
1317struct atom_smu_info_v3_3 {
1318 struct atom_common_table_header table_header;
1319 uint8_t smuip_min_ver;
1320 uint8_t smuip_max_ver;
1321 uint8_t smu_rsd1;
1322 uint8_t gpuclk_ss_mode;
1323 uint16_t sclk_ss_percentage;
1324 uint16_t sclk_ss_rate_10hz;
1325 uint16_t gpuclk_ss_percentage;
1326 uint16_t gpuclk_ss_rate_10hz;
1327 uint32_t core_refclk_10khz;
1328 uint8_t ac_dc_gpio_bit;
1329 uint8_t ac_dc_polarity;
1330 uint8_t vr0hot_gpio_bit;
1331 uint8_t vr0hot_polarity;
1332 uint8_t vr1hot_gpio_bit;
1333 uint8_t vr1hot_polarity;
1334 uint8_t fw_ctf_gpio_bit;
1335 uint8_t fw_ctf_polarity;
1336 uint8_t pcc_gpio_bit;
1337 uint8_t pcc_gpio_polarity;
1338 uint16_t smugoldenoffset;
1339 uint32_t gpupll_vco_freq_10khz;
1340 uint32_t bootup_smnclk_10khz;
1341 uint32_t bootup_socclk_10khz;
1342 uint32_t bootup_mp0clk_10khz;
1343 uint32_t bootup_mp1clk_10khz;
1344 uint32_t bootup_lclk_10khz;
1345 uint32_t bootup_dcefclk_10khz;
1346 uint32_t ctf_threshold_override_value;
1347 uint32_t syspll3_0_vco_freq_10khz;
1348 uint32_t syspll3_1_vco_freq_10khz;
1349 uint32_t bootup_fclk_10khz;
1350 uint32_t bootup_waflclk_10khz;
1351 uint32_t reserved[3];
1352};
1353
1354
1355
1356
1357
1358
1359struct atom_smc_dpm_info_v4_1
1360{
1361 struct atom_common_table_header table_header;
1362 uint8_t liquid1_i2c_address;
1363 uint8_t liquid2_i2c_address;
1364 uint8_t vr_i2c_address;
1365 uint8_t plx_i2c_address;
1366
1367 uint8_t liquid_i2c_linescl;
1368 uint8_t liquid_i2c_linesda;
1369 uint8_t vr_i2c_linescl;
1370 uint8_t vr_i2c_linesda;
1371
1372 uint8_t plx_i2c_linescl;
1373 uint8_t plx_i2c_linesda;
1374 uint8_t vrsensorpresent;
1375 uint8_t liquidsensorpresent;
1376
1377 uint16_t maxvoltagestepgfx;
1378 uint16_t maxvoltagestepsoc;
1379
1380 uint8_t vddgfxvrmapping;
1381 uint8_t vddsocvrmapping;
1382 uint8_t vddmem0vrmapping;
1383 uint8_t vddmem1vrmapping;
1384
1385 uint8_t gfxulvphasesheddingmask;
1386 uint8_t soculvphasesheddingmask;
1387 uint8_t padding8_v[2];
1388
1389 uint16_t gfxmaxcurrent;
1390 uint8_t gfxoffset;
1391 uint8_t padding_telemetrygfx;
1392
1393 uint16_t socmaxcurrent;
1394 uint8_t socoffset;
1395 uint8_t padding_telemetrysoc;
1396
1397 uint16_t mem0maxcurrent;
1398 uint8_t mem0offset;
1399 uint8_t padding_telemetrymem0;
1400
1401 uint16_t mem1maxcurrent;
1402 uint8_t mem1offset;
1403 uint8_t padding_telemetrymem1;
1404
1405 uint8_t acdcgpio;
1406 uint8_t acdcpolarity;
1407 uint8_t vr0hotgpio;
1408 uint8_t vr0hotpolarity;
1409
1410 uint8_t vr1hotgpio;
1411 uint8_t vr1hotpolarity;
1412 uint8_t padding1;
1413 uint8_t padding2;
1414
1415 uint8_t ledpin0;
1416 uint8_t ledpin1;
1417 uint8_t ledpin2;
1418 uint8_t padding8_4;
1419
1420 uint8_t pllgfxclkspreadenabled;
1421 uint8_t pllgfxclkspreadpercent;
1422 uint16_t pllgfxclkspreadfreq;
1423
1424 uint8_t uclkspreadenabled;
1425 uint8_t uclkspreadpercent;
1426 uint16_t uclkspreadfreq;
1427
1428 uint8_t socclkspreadenabled;
1429 uint8_t socclkspreadpercent;
1430 uint16_t socclkspreadfreq;
1431
1432 uint8_t acggfxclkspreadenabled;
1433 uint8_t acggfxclkspreadpercent;
1434 uint16_t acggfxclkspreadfreq;
1435
1436 uint8_t Vr2_I2C_address;
1437 uint8_t padding_vr2[3];
1438
1439 uint32_t boardreserved[9];
1440};
1441
1442
1443
1444
1445
1446
1447struct atom_asic_profiling_info_v4_1
1448{
1449 struct atom_common_table_header table_header;
1450 uint32_t maxvddc;
1451 uint32_t minvddc;
1452 uint32_t avfs_meannsigma_acontant0;
1453 uint32_t avfs_meannsigma_acontant1;
1454 uint32_t avfs_meannsigma_acontant2;
1455 uint16_t avfs_meannsigma_dc_tol_sigma;
1456 uint16_t avfs_meannsigma_platform_mean;
1457 uint16_t avfs_meannsigma_platform_sigma;
1458 uint32_t gb_vdroop_table_cksoff_a0;
1459 uint32_t gb_vdroop_table_cksoff_a1;
1460 uint32_t gb_vdroop_table_cksoff_a2;
1461 uint32_t gb_vdroop_table_ckson_a0;
1462 uint32_t gb_vdroop_table_ckson_a1;
1463 uint32_t gb_vdroop_table_ckson_a2;
1464 uint32_t avfsgb_fuse_table_cksoff_m1;
1465 uint32_t avfsgb_fuse_table_cksoff_m2;
1466 uint32_t avfsgb_fuse_table_cksoff_b;
1467 uint32_t avfsgb_fuse_table_ckson_m1;
1468 uint32_t avfsgb_fuse_table_ckson_m2;
1469 uint32_t avfsgb_fuse_table_ckson_b;
1470 uint16_t max_voltage_0_25mv;
1471 uint8_t enable_gb_vdroop_table_cksoff;
1472 uint8_t enable_gb_vdroop_table_ckson;
1473 uint8_t enable_gb_fuse_table_cksoff;
1474 uint8_t enable_gb_fuse_table_ckson;
1475 uint16_t psm_age_comfactor;
1476 uint8_t enable_apply_avfs_cksoff_voltage;
1477 uint8_t reserved;
1478 uint32_t dispclk2gfxclk_a;
1479 uint32_t dispclk2gfxclk_b;
1480 uint32_t dispclk2gfxclk_c;
1481 uint32_t pixclk2gfxclk_a;
1482 uint32_t pixclk2gfxclk_b;
1483 uint32_t pixclk2gfxclk_c;
1484 uint32_t dcefclk2gfxclk_a;
1485 uint32_t dcefclk2gfxclk_b;
1486 uint32_t dcefclk2gfxclk_c;
1487 uint32_t phyclk2gfxclk_a;
1488 uint32_t phyclk2gfxclk_b;
1489 uint32_t phyclk2gfxclk_c;
1490};
1491
1492struct atom_asic_profiling_info_v4_2 {
1493 struct atom_common_table_header table_header;
1494 uint32_t maxvddc;
1495 uint32_t minvddc;
1496 uint32_t avfs_meannsigma_acontant0;
1497 uint32_t avfs_meannsigma_acontant1;
1498 uint32_t avfs_meannsigma_acontant2;
1499 uint16_t avfs_meannsigma_dc_tol_sigma;
1500 uint16_t avfs_meannsigma_platform_mean;
1501 uint16_t avfs_meannsigma_platform_sigma;
1502 uint32_t gb_vdroop_table_cksoff_a0;
1503 uint32_t gb_vdroop_table_cksoff_a1;
1504 uint32_t gb_vdroop_table_cksoff_a2;
1505 uint32_t gb_vdroop_table_ckson_a0;
1506 uint32_t gb_vdroop_table_ckson_a1;
1507 uint32_t gb_vdroop_table_ckson_a2;
1508 uint32_t avfsgb_fuse_table_cksoff_m1;
1509 uint32_t avfsgb_fuse_table_cksoff_m2;
1510 uint32_t avfsgb_fuse_table_cksoff_b;
1511 uint32_t avfsgb_fuse_table_ckson_m1;
1512 uint32_t avfsgb_fuse_table_ckson_m2;
1513 uint32_t avfsgb_fuse_table_ckson_b;
1514 uint16_t max_voltage_0_25mv;
1515 uint8_t enable_gb_vdroop_table_cksoff;
1516 uint8_t enable_gb_vdroop_table_ckson;
1517 uint8_t enable_gb_fuse_table_cksoff;
1518 uint8_t enable_gb_fuse_table_ckson;
1519 uint16_t psm_age_comfactor;
1520 uint8_t enable_apply_avfs_cksoff_voltage;
1521 uint8_t reserved;
1522 uint32_t dispclk2gfxclk_a;
1523 uint32_t dispclk2gfxclk_b;
1524 uint32_t dispclk2gfxclk_c;
1525 uint32_t pixclk2gfxclk_a;
1526 uint32_t pixclk2gfxclk_b;
1527 uint32_t pixclk2gfxclk_c;
1528 uint32_t dcefclk2gfxclk_a;
1529 uint32_t dcefclk2gfxclk_b;
1530 uint32_t dcefclk2gfxclk_c;
1531 uint32_t phyclk2gfxclk_a;
1532 uint32_t phyclk2gfxclk_b;
1533 uint32_t phyclk2gfxclk_c;
1534 uint32_t acg_gb_vdroop_table_a0;
1535 uint32_t acg_gb_vdroop_table_a1;
1536 uint32_t acg_gb_vdroop_table_a2;
1537 uint32_t acg_avfsgb_fuse_table_m1;
1538 uint32_t acg_avfsgb_fuse_table_m2;
1539 uint32_t acg_avfsgb_fuse_table_b;
1540 uint8_t enable_acg_gb_vdroop_table;
1541 uint8_t enable_acg_gb_fuse_table;
1542 uint32_t acg_dispclk2gfxclk_a;
1543 uint32_t acg_dispclk2gfxclk_b;
1544 uint32_t acg_dispclk2gfxclk_c;
1545 uint32_t acg_pixclk2gfxclk_a;
1546 uint32_t acg_pixclk2gfxclk_b;
1547 uint32_t acg_pixclk2gfxclk_c;
1548 uint32_t acg_dcefclk2gfxclk_a;
1549 uint32_t acg_dcefclk2gfxclk_b;
1550 uint32_t acg_dcefclk2gfxclk_c;
1551 uint32_t acg_phyclk2gfxclk_a;
1552 uint32_t acg_phyclk2gfxclk_b;
1553 uint32_t acg_phyclk2gfxclk_c;
1554};
1555
1556
1557
1558
1559
1560
1561struct atom_multimedia_info_v2_1
1562{
1563 struct atom_common_table_header table_header;
1564 uint8_t uvdip_min_ver;
1565 uint8_t uvdip_max_ver;
1566 uint8_t vceip_min_ver;
1567 uint8_t vceip_max_ver;
1568 uint16_t uvd_enc_max_input_width_pixels;
1569 uint16_t uvd_enc_max_input_height_pixels;
1570 uint16_t vce_enc_max_input_width_pixels;
1571 uint16_t vce_enc_max_input_height_pixels;
1572 uint32_t uvd_enc_max_bandwidth;
1573 uint32_t vce_enc_max_bandwidth;
1574};
1575
1576
1577
1578
1579
1580
1581
1582struct atom_umc_info_v3_1
1583{
1584 struct atom_common_table_header table_header;
1585 uint32_t ucode_version;
1586 uint32_t ucode_rom_startaddr;
1587 uint32_t ucode_length;
1588 uint16_t umc_reg_init_offset;
1589 uint16_t customer_ucode_name_offset;
1590 uint16_t mclk_ss_percentage;
1591 uint16_t mclk_ss_rate_10hz;
1592 uint8_t umcip_min_ver;
1593 uint8_t umcip_max_ver;
1594 uint8_t vram_type;
1595 uint8_t umc_config;
1596 uint32_t mem_refclk_10khz;
1597};
1598
1599
1600
1601
1602
1603
1604
1605struct atom_vram_module_v9
1606{
1607
1608 uint32_t memory_size;
1609 uint32_t channel_enable;
1610 uint32_t umcch_addrcfg;
1611 uint32_t umcch_addrsel;
1612 uint32_t umcch_colsel;
1613 uint16_t vram_module_size;
1614 uint8_t ext_memory_id;
1615 uint8_t memory_type;
1616 uint8_t channel_num;
1617 uint8_t channel_width;
1618 uint8_t density;
1619 uint8_t tunningset_id;
1620 uint8_t vender_rev_id;
1621 uint8_t refreshrate;
1622 uint16_t vram_rsd2;
1623 char dram_pnstring[20];
1624};
1625
1626
1627struct atom_vram_info_header_v2_3
1628{
1629 struct atom_common_table_header table_header;
1630 uint16_t mem_adjust_tbloffset;
1631 uint16_t mem_clk_patch_tbloffset;
1632 uint16_t mc_adjust_pertile_tbloffset;
1633 uint16_t mc_phyinit_tbloffset;
1634 uint16_t dram_data_remap_tbloffset;
1635 uint16_t vram_rsd2[3];
1636 uint8_t vram_module_num;
1637 uint8_t vram_rsd1[2];
1638 uint8_t mc_phy_tile_num;
1639 struct atom_vram_module_v9 vram_module[16];
1640};
1641
1642struct atom_umc_register_addr_info{
1643 uint32_t umc_register_addr:24;
1644 uint32_t umc_reg_type_ind:1;
1645 uint32_t umc_reg_rsvd:7;
1646};
1647
1648
1649enum atom_umc_register_addr_info_flag{
1650 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
1651};
1652
1653union atom_umc_register_addr_info_access
1654{
1655 struct atom_umc_register_addr_info umc_reg_addr;
1656 uint32_t u32umc_reg_addr;
1657};
1658
1659struct atom_umc_reg_setting_id_config{
1660 uint32_t memclockrange:24;
1661 uint32_t mem_blk_id:8;
1662};
1663
1664union atom_umc_reg_setting_id_config_access
1665{
1666 struct atom_umc_reg_setting_id_config umc_id_access;
1667 uint32_t u32umc_id_access;
1668};
1669
1670struct atom_umc_reg_setting_data_block{
1671 union atom_umc_reg_setting_id_config_access block_id;
1672 uint32_t u32umc_reg_data[1];
1673};
1674
1675struct atom_umc_init_reg_block{
1676 uint16_t umc_reg_num;
1677 uint16_t reserved;
1678 union atom_umc_register_addr_info_access umc_reg_list[1];
1679 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1680};
1681
1682
1683
1684
1685
1686
1687
1688struct atom_i2c_data_entry
1689{
1690 uint16_t i2c_reg_index;
1691 uint16_t i2c_reg_data;
1692};
1693
1694struct atom_voltage_object_header_v4{
1695 uint8_t voltage_type;
1696 uint8_t voltage_mode;
1697 uint16_t object_size;
1698};
1699
1700
1701enum atom_voltage_object_mode
1702{
1703 VOLTAGE_OBJ_GPIO_LUT = 0,
1704 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3,
1705 VOLTAGE_OBJ_PHASE_LUT = 4,
1706 VOLTAGE_OBJ_SVID2 = 7,
1707 VOLTAGE_OBJ_EVV = 8,
1708 VOLTAGE_OBJ_MERGED_POWER = 9,
1709};
1710
1711struct atom_i2c_voltage_object_v4
1712{
1713 struct atom_voltage_object_header_v4 header;
1714 uint8_t regulator_id;
1715 uint8_t i2c_id;
1716 uint8_t i2c_slave_addr;
1717 uint8_t i2c_control_offset;
1718 uint8_t i2c_flag;
1719 uint8_t i2c_speed;
1720 uint8_t reserved[2];
1721 struct atom_i2c_data_entry i2cdatalut[1];
1722};
1723
1724
1725enum atom_i2c_voltage_control_flag
1726{
1727 VOLTAGE_DATA_ONE_BYTE = 0,
1728 VOLTAGE_DATA_TWO_BYTE = 1,
1729};
1730
1731
1732struct atom_voltage_gpio_map_lut
1733{
1734 uint32_t voltage_gpio_reg_val;
1735 uint16_t voltage_level_mv;
1736};
1737
1738struct atom_gpio_voltage_object_v4
1739{
1740 struct atom_voltage_object_header_v4 header;
1741 uint8_t gpio_control_id;
1742 uint8_t gpio_entry_num;
1743 uint8_t phase_delay_us;
1744 uint8_t reserved;
1745 uint32_t gpio_mask_val;
1746 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1747};
1748
1749struct atom_svid2_voltage_object_v4
1750{
1751 struct atom_voltage_object_header_v4 header;
1752 uint8_t loadline_psi1;
1753 uint8_t psi0_l_vid_thresd;
1754 uint8_t psi0_enable;
1755 uint8_t maxvstep;
1756 uint8_t telemetry_offset;
1757 uint8_t telemetry_gain;
1758 uint16_t reserved1;
1759};
1760
1761struct atom_merged_voltage_object_v4
1762{
1763 struct atom_voltage_object_header_v4 header;
1764 uint8_t merged_powerrail_type;
1765 uint8_t reserved[3];
1766};
1767
1768union atom_voltage_object_v4{
1769 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1770 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1771 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1772 struct atom_merged_voltage_object_v4 merged_voltage_obj;
1773};
1774
1775struct atom_voltage_objects_info_v4_1
1776{
1777 struct atom_common_table_header table_header;
1778 union atom_voltage_object_v4 voltage_object[1];
1779};
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794struct asic_init_engine_parameters
1795{
1796 uint32_t sclkfreqin10khz:24;
1797 uint32_t engineflag:8;
1798};
1799
1800struct asic_init_mem_parameters
1801{
1802 uint32_t mclkfreqin10khz:24;
1803 uint32_t memflag:8;
1804};
1805
1806struct asic_init_parameters_v2_1
1807{
1808 struct asic_init_engine_parameters engineparam;
1809 struct asic_init_mem_parameters memparam;
1810};
1811
1812struct asic_init_ps_allocation_v2_1
1813{
1814 struct asic_init_parameters_v2_1 param;
1815 uint32_t reserved[16];
1816};
1817
1818
1819enum atom_asic_init_engine_flag
1820{
1821 b3NORMAL_ENGINE_INIT = 0,
1822 b3SRIOV_SKIP_ASIC_INIT = 0x02,
1823 b3SRIOV_LOAD_UCODE = 0x40,
1824};
1825
1826enum atom_asic_init_mem_flag
1827{
1828 b3NORMAL_MEM_INIT = 0,
1829 b3DRAM_SELF_REFRESH_EXIT =0x20,
1830};
1831
1832
1833
1834
1835
1836
1837
1838struct set_engine_clock_parameters_v2_1
1839{
1840 uint32_t sclkfreqin10khz:24;
1841 uint32_t sclkflag:8;
1842 uint32_t reserved[10];
1843};
1844
1845struct set_engine_clock_ps_allocation_v2_1
1846{
1847 struct set_engine_clock_parameters_v2_1 clockinfo;
1848 uint32_t reserved[10];
1849};
1850
1851
1852enum atom_set_engine_mem_clock_flag
1853{
1854 b3NORMAL_CHANGE_CLOCK = 0,
1855 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
1856 b3STORE_DPM_TRAINGING = 0x40,
1857};
1858
1859
1860
1861
1862
1863
1864struct get_engine_clock_parameter
1865{
1866 uint32_t sclk_10khz;
1867 uint32_t reserved;
1868};
1869
1870
1871
1872
1873
1874
1875struct set_memory_clock_parameters_v2_1
1876{
1877 uint32_t mclkfreqin10khz:24;
1878 uint32_t mclkflag:8;
1879 uint32_t reserved[10];
1880};
1881
1882struct set_memory_clock_ps_allocation_v2_1
1883{
1884 struct set_memory_clock_parameters_v2_1 clockinfo;
1885 uint32_t reserved[10];
1886};
1887
1888
1889
1890
1891
1892
1893
1894struct get_memory_clock_parameter
1895{
1896 uint32_t mclk_10khz;
1897 uint32_t reserved;
1898};
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908struct set_voltage_parameters_v1_4
1909{
1910 uint8_t voltagetype;
1911 uint8_t command;
1912 uint16_t vlevel_mv;
1913};
1914
1915
1916enum atom_set_voltage_command{
1917 ATOM_SET_VOLTAGE = 0,
1918 ATOM_INIT_VOLTAGE_REGULATOR = 3,
1919 ATOM_SET_VOLTAGE_PHASE = 4,
1920 ATOM_GET_LEAKAGE_ID = 8,
1921};
1922
1923struct set_voltage_ps_allocation_v1_4
1924{
1925 struct set_voltage_parameters_v1_4 setvoltageparam;
1926 uint32_t reserved[10];
1927};
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937enum atom_gpu_clock_type
1938{
1939 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
1940 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
1941 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
1942};
1943
1944struct compute_gpu_clock_input_parameter_v1_8
1945{
1946 uint32_t gpuclock_10khz:24;
1947 uint32_t gpu_clock_type:8;
1948 uint32_t reserved[5];
1949};
1950
1951
1952struct compute_gpu_clock_output_parameter_v1_8
1953{
1954 uint32_t gpuclock_10khz:24;
1955 uint32_t dfs_did:8;
1956 uint32_t pll_fb_mult;
1957 uint32_t pll_ss_fbsmult;
1958 uint16_t pll_ss_slew_frac;
1959 uint8_t pll_ss_enable;
1960 uint8_t reserved;
1961 uint32_t reserved1[2];
1962};
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972struct read_efuse_input_parameters_v3_1
1973{
1974 uint16_t efuse_start_index;
1975 uint8_t reserved;
1976 uint8_t bitslen;
1977};
1978
1979
1980union read_efuse_value_parameters_v3_1
1981{
1982 struct read_efuse_input_parameters_v3_1 efuse_info;
1983 uint32_t efusevalue;
1984};
1985
1986
1987
1988
1989
1990
1991
1992struct atom_get_smu_clock_info_parameters_v3_1
1993{
1994 uint8_t syspll_id;
1995 uint8_t clk_id;
1996 uint8_t command;
1997 uint8_t dfsdid;
1998};
1999
2000enum atom_get_smu_clock_info_command
2001{
2002 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
2003 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
2004 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
2005};
2006
2007enum atom_smu9_syspll0_clock_id
2008{
2009 SMU9_SYSPLL0_SMNCLK_ID = 0,
2010 SMU9_SYSPLL0_SOCCLK_ID = 1,
2011 SMU9_SYSPLL0_MP0CLK_ID = 2,
2012 SMU9_SYSPLL0_MP1CLK_ID = 3,
2013 SMU9_SYSPLL0_LCLK_ID = 4,
2014 SMU9_SYSPLL0_DCLK_ID = 5,
2015 SMU9_SYSPLL0_VCLK_ID = 6,
2016 SMU9_SYSPLL0_ECLK_ID = 7,
2017 SMU9_SYSPLL0_DCEFCLK_ID = 8,
2018 SMU9_SYSPLL0_DPREFCLK_ID = 10,
2019 SMU9_SYSPLL0_DISPCLK_ID = 11,
2020};
2021
2022enum atom_smu11_syspll_id {
2023 SMU11_SYSPLL0_ID = 0,
2024 SMU11_SYSPLL1_0_ID = 1,
2025 SMU11_SYSPLL1_1_ID = 2,
2026 SMU11_SYSPLL1_2_ID = 3,
2027 SMU11_SYSPLL2_ID = 4,
2028 SMU11_SYSPLL3_0_ID = 5,
2029 SMU11_SYSPLL3_1_ID = 6,
2030};
2031
2032enum atom_smu11_syspll0_clock_id {
2033 SMU11_SYSPLL0_ECLK_ID = 0,
2034 SMU11_SYSPLL0_SOCCLK_ID = 1,
2035 SMU11_SYSPLL0_MP0CLK_ID = 2,
2036 SMU11_SYSPLL0_DCLK_ID = 3,
2037 SMU11_SYSPLL0_VCLK_ID = 4,
2038 SMU11_SYSPLL0_DCEFCLK_ID = 5,
2039};
2040
2041enum atom_smu11_syspll1_0_clock_id {
2042 SMU11_SYSPLL1_0_UCLKA_ID = 0,
2043};
2044
2045enum atom_smu11_syspll1_1_clock_id {
2046 SMU11_SYSPLL1_0_UCLKB_ID = 0,
2047};
2048
2049enum atom_smu11_syspll1_2_clock_id {
2050 SMU11_SYSPLL1_0_FCLK_ID = 0,
2051};
2052
2053enum atom_smu11_syspll2_clock_id {
2054 SMU11_SYSPLL2_GFXCLK_ID = 0,
2055};
2056
2057enum atom_smu11_syspll3_0_clock_id {
2058 SMU11_SYSPLL3_0_WAFCLK_ID = 0,
2059 SMU11_SYSPLL3_0_DISPCLK_ID = 1,
2060 SMU11_SYSPLL3_0_DPREFCLK_ID = 2,
2061};
2062
2063enum atom_smu11_syspll3_1_clock_id {
2064 SMU11_SYSPLL3_1_MP1CLK_ID = 0,
2065 SMU11_SYSPLL3_1_SMNCLK_ID = 1,
2066 SMU11_SYSPLL3_1_LCLK_ID = 2,
2067};
2068
2069struct atom_get_smu_clock_info_output_parameters_v3_1
2070{
2071 union {
2072 uint32_t smu_clock_freq_hz;
2073 uint32_t syspllvcofreq_10khz;
2074 uint32_t sysspllrefclk_10khz;
2075 }atom_smu_outputclkfreq;
2076};
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086enum atom_dynamic_memory_setting_command
2087{
2088 COMPUTE_MEMORY_PLL_PARAM = 1,
2089 COMPUTE_ENGINE_PLL_PARAM = 2,
2090 ADJUST_MC_SETTING_PARAM = 3,
2091};
2092
2093
2094struct dynamic_mclk_settings_parameters_v2_1
2095{
2096 uint32_t mclk_10khz:24;
2097 uint32_t command:8;
2098 uint32_t reserved;
2099};
2100
2101
2102struct dynamic_sclk_settings_parameters_v2_1
2103{
2104 uint32_t sclk_10khz:24;
2105 uint32_t command:8;
2106 uint32_t mclk_10khz;
2107 uint32_t reserved;
2108};
2109
2110union dynamic_memory_settings_parameters_v2_1
2111{
2112 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2113 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2114};
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124enum atom_umc6_0_ucode_function_call_enum_id
2125{
2126 UMC60_UCODE_FUNC_ID_REINIT = 0,
2127 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2128 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2129};
2130
2131
2132struct memory_training_parameters_v2_1
2133{
2134 uint8_t ucode_func_id;
2135 uint8_t ucode_reserved[3];
2136 uint32_t reserved[5];
2137};
2138
2139
2140
2141
2142
2143
2144
2145
2146struct set_pixel_clock_parameter_v1_7
2147{
2148 uint32_t pixclk_100hz;
2149
2150 uint8_t pll_id;
2151 uint8_t encoderobjid;
2152
2153 uint8_t encoder_mode;
2154 uint8_t miscinfo;
2155 uint8_t crtc_id;
2156 uint8_t deep_color_ratio;
2157 uint8_t reserved1[2];
2158 uint32_t reserved2;
2159};
2160
2161
2162enum atom_set_pixel_clock_v1_7_misc_info
2163{
2164 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2165 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2166 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2167 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2168 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2169 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2170 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2171 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2172 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2173 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2174 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2175};
2176
2177
2178enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2179{
2180 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00,
2181 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01,
2182 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02,
2183 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03,
2184};
2185
2186
2187
2188
2189
2190
2191
2192
2193struct set_dce_clock_parameters_v2_1
2194{
2195 uint32_t dceclk_10khz;
2196 uint8_t dceclktype;
2197 uint8_t dceclksrc;
2198 uint8_t dceclkflag;
2199 uint8_t crtc_id;
2200};
2201
2202
2203enum atom_set_dce_clock_clock_type
2204{
2205 DCE_CLOCK_TYPE_DISPCLK = 0,
2206 DCE_CLOCK_TYPE_DPREFCLK = 1,
2207 DCE_CLOCK_TYPE_PIXELCLK = 2,
2208};
2209
2210
2211enum atom_set_dce_clock_dprefclk_flag
2212{
2213 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2214 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2215 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2216 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2217 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2218};
2219
2220
2221enum atom_set_dce_clock_pixclk_flag
2222{
2223 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2224 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00,
2225 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01,
2226 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02,
2227 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03,
2228 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2229};
2230
2231struct set_dce_clock_ps_allocation_v2_1
2232{
2233 struct set_dce_clock_parameters_v2_1 param;
2234 uint32_t ulReserved[2];
2235};
2236
2237
2238
2239
2240
2241struct blank_crtc_parameters
2242{
2243 uint8_t crtc_id;
2244 uint8_t blanking;
2245 uint16_t reserved;
2246 uint32_t reserved1;
2247};
2248
2249enum atom_blank_crtc_command
2250{
2251 ATOM_BLANKING = 1,
2252 ATOM_BLANKING_OFF = 0,
2253};
2254
2255
2256
2257
2258struct enable_crtc_parameters
2259{
2260 uint8_t crtc_id;
2261 uint8_t enable;
2262 uint8_t padding[2];
2263};
2264
2265
2266
2267
2268
2269struct enable_disp_power_gating_parameters_v2_1
2270{
2271 uint8_t disp_pipe_id;
2272 uint8_t enable;
2273 uint8_t padding[2];
2274};
2275
2276struct enable_disp_power_gating_ps_allocation
2277{
2278 struct enable_disp_power_gating_parameters_v2_1 param;
2279 uint32_t ulReserved[4];
2280};
2281
2282
2283
2284
2285struct set_crtc_using_dtd_timing_parameters
2286{
2287 uint16_t h_size;
2288 uint16_t h_blanking_time;
2289 uint16_t v_size;
2290 uint16_t v_blanking_time;
2291 uint16_t h_syncoffset;
2292 uint16_t h_syncwidth;
2293 uint16_t v_syncoffset;
2294 uint16_t v_syncwidth;
2295 uint16_t modemiscinfo;
2296 uint8_t h_border;
2297 uint8_t v_border;
2298 uint8_t crtc_id;
2299 uint8_t encoder_mode;
2300 uint8_t padding[2];
2301};
2302
2303
2304
2305
2306
2307struct process_i2c_channel_transaction_parameters
2308{
2309 uint8_t i2cspeed_khz;
2310 union {
2311 uint8_t regindex;
2312 uint8_t status;
2313 } regind_status;
2314 uint16_t i2c_data_out;
2315 uint8_t flag;
2316 uint8_t trans_bytes;
2317 uint8_t slave_addr;
2318 uint8_t i2c_id;
2319};
2320
2321
2322enum atom_process_i2c_flag
2323{
2324 HW_I2C_WRITE = 1,
2325 HW_I2C_READ = 0,
2326 I2C_2BYTE_ADDR = 0x02,
2327 HW_I2C_SMBUS_BYTE_WR = 0x04,
2328};
2329
2330
2331enum atom_process_i2c_status
2332{
2333 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2334 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2335};
2336
2337
2338
2339
2340
2341
2342struct process_aux_channel_transaction_parameters_v1_2
2343{
2344 uint16_t aux_request;
2345 uint16_t dataout;
2346 uint8_t channelid;
2347 union {
2348 uint8_t reply_status;
2349 uint8_t aux_delay;
2350 } aux_status_delay;
2351 uint8_t dataout_len;
2352 uint8_t hpd_id;
2353};
2354
2355
2356
2357
2358
2359
2360struct select_crtc_source_parameters_v2_3
2361{
2362 uint8_t crtc_id;
2363 uint8_t encoder_id;
2364 uint8_t encode_mode;
2365 uint8_t dst_bpc;
2366};
2367
2368
2369
2370
2371
2372
2373
2374enum atom_dig_encoder_control_action
2375{
2376 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2377 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2378 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2379 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2380 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2381 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2382 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2383 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2384 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2385 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2386 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2387 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2388 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2389 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2390};
2391
2392
2393enum atom_dig_encoder_control_panelmode
2394{
2395 DP_PANEL_MODE_DISABLE = 0x00,
2396 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2397 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2398};
2399
2400
2401enum atom_dig_encoder_control_v5_digid
2402{
2403 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2404 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2405 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2406 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2407 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2408 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2409 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2410 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2411};
2412
2413struct dig_encoder_stream_setup_parameters_v1_5
2414{
2415 uint8_t digid;
2416 uint8_t action;
2417 uint8_t digmode;
2418 uint8_t lanenum;
2419 uint32_t pclk_10khz;
2420 uint8_t bitpercolor;
2421 uint8_t dplinkrate_270mhz;
2422 uint8_t reserved[2];
2423};
2424
2425struct dig_encoder_link_setup_parameters_v1_5
2426{
2427 uint8_t digid;
2428 uint8_t action;
2429 uint8_t digmode;
2430 uint8_t lanenum;
2431 uint8_t symclk_10khz;
2432 uint8_t hpd_sel;
2433 uint8_t digfe_sel;
2434 uint8_t reserved[2];
2435};
2436
2437struct dp_panel_mode_set_parameters_v1_5
2438{
2439 uint8_t digid;
2440 uint8_t action;
2441 uint8_t panelmode;
2442 uint8_t reserved1;
2443 uint32_t reserved2[2];
2444};
2445
2446struct dig_encoder_generic_cmd_parameters_v1_5
2447{
2448 uint8_t digid;
2449 uint8_t action;
2450 uint8_t reserved1[2];
2451 uint32_t reserved2[2];
2452};
2453
2454union dig_encoder_control_parameters_v1_5
2455{
2456 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2457 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2458 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2459 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2460};
2461
2462
2463
2464
2465
2466
2467struct dig_transmitter_control_parameters_v1_6
2468{
2469 uint8_t phyid;
2470 uint8_t action;
2471 union {
2472 uint8_t digmode;
2473 uint8_t dplaneset;
2474 } mode_laneset;
2475 uint8_t lanenum;
2476 uint32_t symclk_10khz;
2477 uint8_t hpdsel;
2478 uint8_t digfe_sel;
2479 uint8_t connobj_id;
2480 uint8_t reserved;
2481 uint32_t reserved1;
2482};
2483
2484struct dig_transmitter_control_ps_allocation_v1_6
2485{
2486 struct dig_transmitter_control_parameters_v1_6 param;
2487 uint32_t reserved[4];
2488};
2489
2490
2491enum atom_dig_transmitter_control_action
2492{
2493 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
2494 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
2495 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
2496 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
2497 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
2498 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
2499 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
2500 ATOM_TRANSMITTER_ACTION_INIT = 7,
2501 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
2502 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
2503 ATOM_TRANSMITTER_ACTION_SETUP = 10,
2504 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
2505 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
2506 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
2507};
2508
2509
2510enum atom_dig_transmitter_control_digfe_sel
2511{
2512 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
2513 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
2514 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
2515 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
2516 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
2517 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
2518 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
2519};
2520
2521
2522
2523enum atom_dig_transmitter_control_hpd_sel
2524{
2525 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
2526 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
2527 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
2528 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
2529 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
2530 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
2531 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
2532};
2533
2534
2535enum atom_dig_transmitter_control_dplaneset
2536{
2537 DP_LANE_SET__0DB_0_4V = 0x00,
2538 DP_LANE_SET__0DB_0_6V = 0x01,
2539 DP_LANE_SET__0DB_0_8V = 0x02,
2540 DP_LANE_SET__0DB_1_2V = 0x03,
2541 DP_LANE_SET__3_5DB_0_4V = 0x08,
2542 DP_LANE_SET__3_5DB_0_6V = 0x09,
2543 DP_LANE_SET__3_5DB_0_8V = 0x0a,
2544 DP_LANE_SET__6DB_0_4V = 0x10,
2545 DP_LANE_SET__6DB_0_6V = 0x11,
2546 DP_LANE_SET__9_5DB_0_4V = 0x18,
2547};
2548
2549
2550
2551
2552
2553
2554
2555struct external_encoder_control_parameters_v2_4
2556{
2557 uint16_t pixelclock_10khz;
2558 uint8_t config;
2559 uint8_t action;
2560 uint8_t encodermode;
2561 uint8_t lanenum;
2562 uint8_t bitpercolor;
2563 uint8_t hpd_id;
2564};
2565
2566
2567
2568enum external_encoder_control_action_def
2569{
2570 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
2571 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
2572 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
2573 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
2574 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
2575 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
2576 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
2577 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
2578};
2579
2580
2581enum external_encoder_control_v2_4_config_def
2582{
2583 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
2584 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
2585 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
2586 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
2587 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
2588 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
2589 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
2590 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
2591 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
2592};
2593
2594struct external_encoder_control_ps_allocation_v2_4
2595{
2596 struct external_encoder_control_parameters_v2_4 sExtEncoder;
2597 uint32_t reserved[2];
2598};
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608struct amd_acpi_description_header{
2609 uint32_t signature;
2610 uint32_t tableLength;
2611 uint8_t revision;
2612 uint8_t checksum;
2613 uint8_t oemId[6];
2614 uint8_t oemTableId[8];
2615 uint32_t oemRevision;
2616 uint32_t creatorId;
2617 uint32_t creatorRevision;
2618};
2619
2620struct uefi_acpi_vfct{
2621 struct amd_acpi_description_header sheader;
2622 uint8_t tableUUID[16];
2623 uint32_t vbiosimageoffset;
2624 uint32_t lib1Imageoffset;
2625 uint32_t reserved[4];
2626};
2627
2628struct vfct_image_header{
2629 uint32_t pcibus;
2630 uint32_t pcidevice;
2631 uint32_t pcifunction;
2632 uint16_t vendorid;
2633 uint16_t deviceid;
2634 uint16_t ssvid;
2635 uint16_t ssid;
2636 uint32_t revision;
2637 uint32_t imagelength;
2638};
2639
2640
2641struct gop_vbios_content {
2642 struct vfct_image_header vbiosheader;
2643 uint8_t vbioscontent[1];
2644};
2645
2646struct gop_lib1_content {
2647 struct vfct_image_header lib1header;
2648 uint8_t lib1content[1];
2649};
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661enum scratch_register_def{
2662 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
2663 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
2664 ATOM_ACTIVE_INFO_DEF = 3,
2665 ATOM_LCD_INFO_DEF = 4,
2666 ATOM_DEVICE_REQ_INFO_DEF = 5,
2667 ATOM_ACC_CHANGE_INFO_DEF = 6,
2668 ATOM_PRE_OS_MODE_INFO_DEF = 7,
2669 ATOM_PRE_OS_ASSERTION_DEF = 8,
2670 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
2671};
2672
2673enum scratch_device_connect_info_bit_def{
2674 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
2675 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
2676 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
2677 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
2678 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
2679 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
2680 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
2681 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
2682 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
2683};
2684
2685enum scratch_bl_bri_level_info_bit_def{
2686 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
2687#ifndef _H2INC
2688 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
2689 ATOM_DEVICE_DPMS_STATE =0x00010000,
2690#endif
2691};
2692
2693enum scratch_active_info_bits_def{
2694 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
2695 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
2696 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
2697 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
2698 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
2699 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
2700 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
2701 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
2702};
2703
2704enum scratch_device_req_info_bits_def{
2705 ATOM_DISPLAY_LCD1_REQ =0x0002,
2706 ATOM_DISPLAY_DFP1_REQ =0x0008,
2707 ATOM_DISPLAY_DFP2_REQ =0x0080,
2708 ATOM_DISPLAY_DFP3_REQ =0x0200,
2709 ATOM_DISPLAY_DFP4_REQ =0x0400,
2710 ATOM_DISPLAY_DFP5_REQ =0x0800,
2711 ATOM_DISPLAY_DFP6_REQ =0x0040,
2712 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
2713};
2714
2715enum scratch_acc_change_info_bitshift_def{
2716 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
2717 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
2718};
2719
2720enum scratch_acc_change_info_bits_def{
2721 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
2722 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
2723};
2724
2725enum scratch_pre_os_mode_info_bits_def{
2726 ATOM_PRE_OS_MODE_MASK =0x00000003,
2727 ATOM_PRE_OS_MODE_VGA =0x00000000,
2728 ATOM_PRE_OS_MODE_VESA =0x00000001,
2729 ATOM_PRE_OS_MODE_GOP =0x00000002,
2730 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
2731 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2732 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
2733 ATOM_ASIC_INIT_COMPLETE =0x00000200,
2734#ifndef _H2INC
2735 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
2736#endif
2737};
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747#include "atomfirmwareid.h"
2748#pragma pack()
2749
2750#endif
2751
2752