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27#include <linux/seq_file.h>
28#include <linux/circ_buf.h>
29#include <linux/ctype.h>
30#include <linux/debugfs.h>
31#include "intel_drv.h"
32
33struct pipe_crc_info {
34 const char *name;
35 struct drm_i915_private *dev_priv;
36 enum pipe pipe;
37};
38
39static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
40{
41 struct pipe_crc_info *info = inode->i_private;
42 struct drm_i915_private *dev_priv = info->dev_priv;
43 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
44
45 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
46 return -ENODEV;
47
48 spin_lock_irq(&pipe_crc->lock);
49
50 if (pipe_crc->opened) {
51 spin_unlock_irq(&pipe_crc->lock);
52 return -EBUSY;
53 }
54
55 pipe_crc->opened = true;
56 filep->private_data = inode->i_private;
57
58 spin_unlock_irq(&pipe_crc->lock);
59
60 return 0;
61}
62
63static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
64{
65 struct pipe_crc_info *info = inode->i_private;
66 struct drm_i915_private *dev_priv = info->dev_priv;
67 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
68
69 spin_lock_irq(&pipe_crc->lock);
70 pipe_crc->opened = false;
71 spin_unlock_irq(&pipe_crc->lock);
72
73 return 0;
74}
75
76
77#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
78
79#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
80
81static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
82{
83 lockdep_assert_held(&pipe_crc->lock);
84 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
85 INTEL_PIPE_CRC_ENTRIES_NR);
86}
87
88static ssize_t
89i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
90 loff_t *pos)
91{
92 struct pipe_crc_info *info = filep->private_data;
93 struct drm_i915_private *dev_priv = info->dev_priv;
94 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
95 char buf[PIPE_CRC_BUFFER_LEN];
96 int n_entries;
97 ssize_t bytes_read;
98
99
100
101
102
103 if (count < PIPE_CRC_LINE_LEN)
104 return -EINVAL;
105
106 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
107 return 0;
108
109
110 spin_lock_irq(&pipe_crc->lock);
111 while (pipe_crc_data_count(pipe_crc) == 0) {
112 int ret;
113
114 if (filep->f_flags & O_NONBLOCK) {
115 spin_unlock_irq(&pipe_crc->lock);
116 return -EAGAIN;
117 }
118
119 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
120 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
121 if (ret) {
122 spin_unlock_irq(&pipe_crc->lock);
123 return ret;
124 }
125 }
126
127
128 n_entries = count / PIPE_CRC_LINE_LEN;
129
130 bytes_read = 0;
131 while (n_entries > 0) {
132 struct intel_pipe_crc_entry *entry =
133 &pipe_crc->entries[pipe_crc->tail];
134
135 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
136 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
137 break;
138
139 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
140 pipe_crc->tail = (pipe_crc->tail + 1) &
141 (INTEL_PIPE_CRC_ENTRIES_NR - 1);
142
143 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
144 "%8u %8x %8x %8x %8x %8x\n",
145 entry->frame, entry->crc[0],
146 entry->crc[1], entry->crc[2],
147 entry->crc[3], entry->crc[4]);
148
149 spin_unlock_irq(&pipe_crc->lock);
150
151 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
152 return -EFAULT;
153
154 user_buf += PIPE_CRC_LINE_LEN;
155 n_entries--;
156
157 spin_lock_irq(&pipe_crc->lock);
158 }
159
160 spin_unlock_irq(&pipe_crc->lock);
161
162 return bytes_read;
163}
164
165static const struct file_operations i915_pipe_crc_fops = {
166 .owner = THIS_MODULE,
167 .open = i915_pipe_crc_open,
168 .read = i915_pipe_crc_read,
169 .release = i915_pipe_crc_release,
170};
171
172static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
173 {
174 .name = "i915_pipe_A_crc",
175 .pipe = PIPE_A,
176 },
177 {
178 .name = "i915_pipe_B_crc",
179 .pipe = PIPE_B,
180 },
181 {
182 .name = "i915_pipe_C_crc",
183 .pipe = PIPE_C,
184 },
185};
186
187static const char * const pipe_crc_sources[] = {
188 "none",
189 "plane1",
190 "plane2",
191 "pf",
192 "pipe",
193 "TV",
194 "DP-B",
195 "DP-C",
196 "DP-D",
197 "auto",
198};
199
200static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
201{
202 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
203 return pipe_crc_sources[source];
204}
205
206static int display_crc_ctl_show(struct seq_file *m, void *data)
207{
208 struct drm_i915_private *dev_priv = m->private;
209 enum pipe pipe;
210
211 for_each_pipe(dev_priv, pipe)
212 seq_printf(m, "%c %s\n", pipe_name(pipe),
213 pipe_crc_source_name(dev_priv->pipe_crc[pipe].source));
214
215 return 0;
216}
217
218static int display_crc_ctl_open(struct inode *inode, struct file *file)
219{
220 return single_open(file, display_crc_ctl_show, inode->i_private);
221}
222
223static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
224 uint32_t *val)
225{
226 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
227 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
228
229 switch (*source) {
230 case INTEL_PIPE_CRC_SOURCE_PIPE:
231 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
232 break;
233 case INTEL_PIPE_CRC_SOURCE_NONE:
234 *val = 0;
235 break;
236 default:
237 return -EINVAL;
238 }
239
240 return 0;
241}
242
243static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
244 enum pipe pipe,
245 enum intel_pipe_crc_source *source)
246{
247 struct drm_device *dev = &dev_priv->drm;
248 struct intel_encoder *encoder;
249 struct intel_crtc *crtc;
250 struct intel_digital_port *dig_port;
251 int ret = 0;
252
253 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
254
255 drm_modeset_lock_all(dev);
256 for_each_intel_encoder(dev, encoder) {
257 if (!encoder->base.crtc)
258 continue;
259
260 crtc = to_intel_crtc(encoder->base.crtc);
261
262 if (crtc->pipe != pipe)
263 continue;
264
265 switch (encoder->type) {
266 case INTEL_OUTPUT_TVOUT:
267 *source = INTEL_PIPE_CRC_SOURCE_TV;
268 break;
269 case INTEL_OUTPUT_DP:
270 case INTEL_OUTPUT_EDP:
271 dig_port = enc_to_dig_port(&encoder->base);
272 switch (dig_port->base.port) {
273 case PORT_B:
274 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
275 break;
276 case PORT_C:
277 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
278 break;
279 case PORT_D:
280 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
281 break;
282 default:
283 WARN(1, "nonexisting DP port %c\n",
284 port_name(dig_port->base.port));
285 break;
286 }
287 break;
288 default:
289 break;
290 }
291 }
292 drm_modeset_unlock_all(dev);
293
294 return ret;
295}
296
297static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
298 enum pipe pipe,
299 enum intel_pipe_crc_source *source,
300 uint32_t *val)
301{
302 bool need_stable_symbols = false;
303
304 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
305 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
306 if (ret)
307 return ret;
308 }
309
310 switch (*source) {
311 case INTEL_PIPE_CRC_SOURCE_PIPE:
312 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
313 break;
314 case INTEL_PIPE_CRC_SOURCE_DP_B:
315 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
316 need_stable_symbols = true;
317 break;
318 case INTEL_PIPE_CRC_SOURCE_DP_C:
319 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
320 need_stable_symbols = true;
321 break;
322 case INTEL_PIPE_CRC_SOURCE_DP_D:
323 if (!IS_CHERRYVIEW(dev_priv))
324 return -EINVAL;
325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
326 need_stable_symbols = true;
327 break;
328 case INTEL_PIPE_CRC_SOURCE_NONE:
329 *val = 0;
330 break;
331 default:
332 return -EINVAL;
333 }
334
335
336
337
338
339
340
341
342
343
344 if (need_stable_symbols) {
345 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
346
347 tmp |= DC_BALANCE_RESET_VLV;
348 switch (pipe) {
349 case PIPE_A:
350 tmp |= PIPE_A_SCRAMBLE_RESET;
351 break;
352 case PIPE_B:
353 tmp |= PIPE_B_SCRAMBLE_RESET;
354 break;
355 case PIPE_C:
356 tmp |= PIPE_C_SCRAMBLE_RESET;
357 break;
358 default:
359 return -EINVAL;
360 }
361 I915_WRITE(PORT_DFT2_G4X, tmp);
362 }
363
364 return 0;
365}
366
367static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
368 enum pipe pipe,
369 enum intel_pipe_crc_source *source,
370 uint32_t *val)
371{
372 bool need_stable_symbols = false;
373
374 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
375 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
376 if (ret)
377 return ret;
378 }
379
380 switch (*source) {
381 case INTEL_PIPE_CRC_SOURCE_PIPE:
382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
383 break;
384 case INTEL_PIPE_CRC_SOURCE_TV:
385 if (!SUPPORTS_TV(dev_priv))
386 return -EINVAL;
387 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
388 break;
389 case INTEL_PIPE_CRC_SOURCE_DP_B:
390 if (!IS_G4X(dev_priv))
391 return -EINVAL;
392 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
393 need_stable_symbols = true;
394 break;
395 case INTEL_PIPE_CRC_SOURCE_DP_C:
396 if (!IS_G4X(dev_priv))
397 return -EINVAL;
398 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
399 need_stable_symbols = true;
400 break;
401 case INTEL_PIPE_CRC_SOURCE_DP_D:
402 if (!IS_G4X(dev_priv))
403 return -EINVAL;
404 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
405 need_stable_symbols = true;
406 break;
407 case INTEL_PIPE_CRC_SOURCE_NONE:
408 *val = 0;
409 break;
410 default:
411 return -EINVAL;
412 }
413
414
415
416
417
418
419
420
421
422
423 if (need_stable_symbols) {
424 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
425
426 WARN_ON(!IS_G4X(dev_priv));
427
428 I915_WRITE(PORT_DFT_I9XX,
429 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
430
431 if (pipe == PIPE_A)
432 tmp |= PIPE_A_SCRAMBLE_RESET;
433 else
434 tmp |= PIPE_B_SCRAMBLE_RESET;
435
436 I915_WRITE(PORT_DFT2_G4X, tmp);
437 }
438
439 return 0;
440}
441
442static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
443 enum pipe pipe)
444{
445 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
446
447 switch (pipe) {
448 case PIPE_A:
449 tmp &= ~PIPE_A_SCRAMBLE_RESET;
450 break;
451 case PIPE_B:
452 tmp &= ~PIPE_B_SCRAMBLE_RESET;
453 break;
454 case PIPE_C:
455 tmp &= ~PIPE_C_SCRAMBLE_RESET;
456 break;
457 default:
458 return;
459 }
460 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
461 tmp &= ~DC_BALANCE_RESET_VLV;
462 I915_WRITE(PORT_DFT2_G4X, tmp);
463
464}
465
466static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
467 enum pipe pipe)
468{
469 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
470
471 if (pipe == PIPE_A)
472 tmp &= ~PIPE_A_SCRAMBLE_RESET;
473 else
474 tmp &= ~PIPE_B_SCRAMBLE_RESET;
475 I915_WRITE(PORT_DFT2_G4X, tmp);
476
477 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
478 I915_WRITE(PORT_DFT_I9XX,
479 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
480 }
481}
482
483static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
484 uint32_t *val)
485{
486 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
487 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
488
489 switch (*source) {
490 case INTEL_PIPE_CRC_SOURCE_PLANE1:
491 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
492 break;
493 case INTEL_PIPE_CRC_SOURCE_PLANE2:
494 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
495 break;
496 case INTEL_PIPE_CRC_SOURCE_PIPE:
497 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
498 break;
499 case INTEL_PIPE_CRC_SOURCE_NONE:
500 *val = 0;
501 break;
502 default:
503 return -EINVAL;
504 }
505
506 return 0;
507}
508
509static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
510 bool enable)
511{
512 struct drm_device *dev = &dev_priv->drm;
513 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
514 struct intel_crtc_state *pipe_config;
515 struct drm_atomic_state *state;
516 struct drm_modeset_acquire_ctx ctx;
517 int ret = 0;
518
519 drm_modeset_acquire_init(&ctx, 0);
520
521 state = drm_atomic_state_alloc(dev);
522 if (!state) {
523 ret = -ENOMEM;
524 goto unlock;
525 }
526
527 state->acquire_ctx = &ctx;
528
529retry:
530 pipe_config = intel_atomic_get_crtc_state(state, crtc);
531 if (IS_ERR(pipe_config)) {
532 ret = PTR_ERR(pipe_config);
533 goto put_state;
534 }
535
536 if (HAS_IPS(dev_priv)) {
537
538
539
540
541
542
543 pipe_config->ips_force_disable = enable;
544 }
545
546 if (IS_HASWELL(dev_priv)) {
547 pipe_config->pch_pfit.force_thru = enable;
548 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
549 pipe_config->pch_pfit.enabled != enable)
550 pipe_config->base.connectors_changed = true;
551 }
552
553 ret = drm_atomic_commit(state);
554
555put_state:
556 if (ret == -EDEADLK) {
557 drm_atomic_state_clear(state);
558 drm_modeset_backoff(&ctx);
559 goto retry;
560 }
561
562 drm_atomic_state_put(state);
563unlock:
564 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
565 drm_modeset_drop_locks(&ctx);
566 drm_modeset_acquire_fini(&ctx);
567}
568
569static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
570 enum pipe pipe,
571 enum intel_pipe_crc_source *source,
572 uint32_t *val,
573 bool set_wa)
574{
575 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
576 *source = INTEL_PIPE_CRC_SOURCE_PF;
577
578 switch (*source) {
579 case INTEL_PIPE_CRC_SOURCE_PLANE1:
580 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
581 break;
582 case INTEL_PIPE_CRC_SOURCE_PLANE2:
583 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
584 break;
585 case INTEL_PIPE_CRC_SOURCE_PF:
586 if (set_wa && (IS_HASWELL(dev_priv) ||
587 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
588 hsw_pipe_A_crc_wa(dev_priv, true);
589
590 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
591 break;
592 case INTEL_PIPE_CRC_SOURCE_NONE:
593 *val = 0;
594 break;
595 default:
596 return -EINVAL;
597 }
598
599 return 0;
600}
601
602static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
603 enum pipe pipe,
604 enum intel_pipe_crc_source *source, u32 *val,
605 bool set_wa)
606{
607 if (IS_GEN2(dev_priv))
608 return i8xx_pipe_crc_ctl_reg(source, val);
609 else if (INTEL_GEN(dev_priv) < 5)
610 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
611 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
612 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
613 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
614 return ilk_pipe_crc_ctl_reg(source, val);
615 else
616 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
617}
618
619static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
620 enum pipe pipe,
621 enum intel_pipe_crc_source source)
622{
623 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
624 enum intel_display_power_domain power_domain;
625 u32 val = 0;
626 int ret;
627
628 if (pipe_crc->source == source)
629 return 0;
630
631
632 if (pipe_crc->source && source)
633 return -EINVAL;
634
635 power_domain = POWER_DOMAIN_PIPE(pipe);
636 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
637 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
638 return -EIO;
639 }
640
641 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val, true);
642 if (ret != 0)
643 goto out;
644
645
646 if (source) {
647 struct intel_pipe_crc_entry *entries;
648
649 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
650 pipe_name(pipe), pipe_crc_source_name(source));
651
652 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
653 sizeof(pipe_crc->entries[0]),
654 GFP_KERNEL);
655 if (!entries) {
656 ret = -ENOMEM;
657 goto out;
658 }
659
660 spin_lock_irq(&pipe_crc->lock);
661 kfree(pipe_crc->entries);
662 pipe_crc->entries = entries;
663 pipe_crc->head = 0;
664 pipe_crc->tail = 0;
665 spin_unlock_irq(&pipe_crc->lock);
666 }
667
668 pipe_crc->source = source;
669
670 I915_WRITE(PIPE_CRC_CTL(pipe), val);
671 POSTING_READ(PIPE_CRC_CTL(pipe));
672
673
674 if (!source) {
675 struct intel_pipe_crc_entry *entries;
676 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
677 pipe);
678
679 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
680 pipe_name(pipe));
681
682 drm_modeset_lock(&crtc->base.mutex, NULL);
683 if (crtc->base.state->active)
684 intel_wait_for_vblank(dev_priv, pipe);
685 drm_modeset_unlock(&crtc->base.mutex);
686
687 spin_lock_irq(&pipe_crc->lock);
688 entries = pipe_crc->entries;
689 pipe_crc->entries = NULL;
690 pipe_crc->head = 0;
691 pipe_crc->tail = 0;
692 spin_unlock_irq(&pipe_crc->lock);
693
694 kfree(entries);
695
696 if (IS_G4X(dev_priv))
697 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
698 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
699 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
700 else if ((IS_HASWELL(dev_priv) ||
701 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
702 hsw_pipe_A_crc_wa(dev_priv, false);
703 }
704
705 ret = 0;
706
707out:
708 intel_display_power_put(dev_priv, power_domain);
709
710 return ret;
711}
712
713
714
715
716
717
718
719
720
721
722
723
724
725static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
726{
727 int n_words = 0;
728
729 while (*buf) {
730 char *end;
731
732
733 buf = skip_spaces(buf);
734 if (!*buf)
735 break;
736
737
738 for (end = buf; *end && !isspace(*end); end++)
739 ;
740
741 if (n_words == max_words) {
742 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
743 max_words);
744 return -EINVAL;
745 }
746
747 if (*end)
748 *end++ = '\0';
749 words[n_words++] = buf;
750 buf = end;
751 }
752
753 return n_words;
754}
755
756enum intel_pipe_crc_object {
757 PIPE_CRC_OBJECT_PIPE,
758};
759
760static const char * const pipe_crc_objects[] = {
761 "pipe",
762};
763
764static int
765display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
766{
767 int i;
768
769 i = match_string(pipe_crc_objects, ARRAY_SIZE(pipe_crc_objects), buf);
770 if (i < 0)
771 return i;
772
773 *o = i;
774 return 0;
775}
776
777static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
778 const char *buf, enum pipe *pipe)
779{
780 const char name = buf[0];
781
782 if (name < 'A' || name >= pipe_name(INTEL_INFO(dev_priv)->num_pipes))
783 return -EINVAL;
784
785 *pipe = name - 'A';
786
787 return 0;
788}
789
790static int
791display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
792{
793 int i;
794
795 if (!buf) {
796 *s = INTEL_PIPE_CRC_SOURCE_NONE;
797 return 0;
798 }
799
800 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
801 if (i < 0)
802 return i;
803
804 *s = i;
805 return 0;
806}
807
808static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
809 char *buf, size_t len)
810{
811#define N_WORDS 3
812 int n_words;
813 char *words[N_WORDS];
814 enum pipe pipe;
815 enum intel_pipe_crc_object object;
816 enum intel_pipe_crc_source source;
817
818 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
819 if (n_words != N_WORDS) {
820 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
821 N_WORDS);
822 return -EINVAL;
823 }
824
825 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
826 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
827 return -EINVAL;
828 }
829
830 if (display_crc_ctl_parse_pipe(dev_priv, words[1], &pipe) < 0) {
831 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
832 return -EINVAL;
833 }
834
835 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
836 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
837 return -EINVAL;
838 }
839
840 return pipe_crc_set_source(dev_priv, pipe, source);
841}
842
843static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
844 size_t len, loff_t *offp)
845{
846 struct seq_file *m = file->private_data;
847 struct drm_i915_private *dev_priv = m->private;
848 char *tmpbuf;
849 int ret;
850
851 if (len == 0)
852 return 0;
853
854 if (len > PAGE_SIZE - 1) {
855 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
856 PAGE_SIZE);
857 return -E2BIG;
858 }
859
860 tmpbuf = memdup_user_nul(ubuf, len);
861 if (IS_ERR(tmpbuf))
862 return PTR_ERR(tmpbuf);
863
864 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
865
866 kfree(tmpbuf);
867 if (ret < 0)
868 return ret;
869
870 *offp += len;
871 return len;
872}
873
874const struct file_operations i915_display_crc_ctl_fops = {
875 .owner = THIS_MODULE,
876 .open = display_crc_ctl_open,
877 .read = seq_read,
878 .llseek = seq_lseek,
879 .release = single_release,
880 .write = display_crc_ctl_write
881};
882
883void intel_display_crc_init(struct drm_i915_private *dev_priv)
884{
885 enum pipe pipe;
886
887 for_each_pipe(dev_priv, pipe) {
888 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
889
890 pipe_crc->opened = false;
891 spin_lock_init(&pipe_crc->lock);
892 init_waitqueue_head(&pipe_crc->wq);
893 }
894}
895
896int intel_pipe_crc_create(struct drm_minor *minor)
897{
898 struct drm_i915_private *dev_priv = to_i915(minor->dev);
899 struct dentry *ent;
900 int i;
901
902 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
903 struct pipe_crc_info *info = &i915_pipe_crc_data[i];
904
905 info->dev_priv = dev_priv;
906 ent = debugfs_create_file(info->name, S_IRUGO,
907 minor->debugfs_root, info,
908 &i915_pipe_crc_fops);
909 if (!ent)
910 return -ENOMEM;
911 }
912
913 return 0;
914}
915
916int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
917 size_t *values_cnt)
918{
919 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
920 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
921 enum intel_display_power_domain power_domain;
922 enum intel_pipe_crc_source source;
923 u32 val = 0;
924 int ret = 0;
925
926 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
927 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
928 return -EINVAL;
929 }
930
931 power_domain = POWER_DOMAIN_PIPE(crtc->index);
932 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
933 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
934 return -EIO;
935 }
936
937 ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
938 if (ret != 0)
939 goto out;
940
941 pipe_crc->source = source;
942 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
943 POSTING_READ(PIPE_CRC_CTL(crtc->index));
944
945 if (!source) {
946 if (IS_G4X(dev_priv))
947 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
948 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
949 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
950 else if ((IS_HASWELL(dev_priv) ||
951 IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
952 hsw_pipe_A_crc_wa(dev_priv, false);
953 }
954
955 pipe_crc->skipped = 0;
956 *values_cnt = 5;
957
958out:
959 intel_display_power_put(dev_priv, power_domain);
960
961 return ret;
962}
963
964void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
965{
966 struct drm_crtc *crtc = &intel_crtc->base;
967 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
968 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
969 u32 val = 0;
970
971 if (!crtc->crc.opened)
972 return;
973
974 if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
975 return;
976
977
978 pipe_crc->skipped = 0;
979
980 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
981 POSTING_READ(PIPE_CRC_CTL(crtc->index));
982}
983
984void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
985{
986 struct drm_crtc *crtc = &intel_crtc->base;
987 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
988 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
989
990
991 spin_lock_irq(&pipe_crc->lock);
992 pipe_crc->skipped = INT_MIN;
993 spin_unlock_irq(&pipe_crc->lock);
994
995 I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
996 POSTING_READ(PIPE_CRC_CTL(crtc->index));
997 synchronize_irq(dev_priv->drm.irq);
998}
999
