1#ifndef _CHIP_H
2#define _CHIP_H
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54
55#define CCE_NUM_MSIX_VECTORS 256
56#define CCE_NUM_INT_CSRS 12
57#define CCE_NUM_INT_MAP_CSRS 96
58#define NUM_INTERRUPT_SOURCES 768
59#define RXE_NUM_CONTEXTS 160
60#define RXE_PER_CONTEXT_SIZE 0x1000
61#define RXE_NUM_TID_FLOWS 32
62#define RXE_NUM_DATA_VL 8
63#define TXE_NUM_CONTEXTS 160
64#define TXE_NUM_SDMA_ENGINES 16
65#define NUM_CONTEXTS_PER_SET 8
66#define VL_ARB_HIGH_PRIO_TABLE_SIZE 16
67#define VL_ARB_LOW_PRIO_TABLE_SIZE 16
68#define VL_ARB_TABLE_SIZE 16
69#define TXE_NUM_32_BIT_COUNTER 7
70#define TXE_NUM_64_BIT_COUNTER 30
71#define TXE_NUM_DATA_VL 8
72#define TXE_PIO_SIZE (32 * 0x100000)
73#define PIO_BLOCK_SIZE 64
74#define SDMA_BLOCK_SIZE 64
75#define RCV_BUF_BLOCK_SIZE 64
76#define PIO_CMASK 0x7ff
77#define MAX_EAGER_ENTRIES 2048
78#define MAX_TID_PAIR_ENTRIES 1024
79
80
81
82
83#define CM_VAU 3
84
85#define CM_GLOBAL_CREDITS 0x880
86
87#define MAX_PKEY_VALUES 16
88
89#include "chip_registers.h"
90
91#define RXE_PER_CONTEXT_USER (RXE + RXE_PER_CONTEXT_OFFSET)
92#define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
93
94
95#define PBC_INTR BIT_ULL(31)
96#define PBC_DC_INFO_SHIFT (30)
97#define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT)
98#define PBC_TEST_EBP BIT_ULL(29)
99#define PBC_PACKET_BYPASS BIT_ULL(28)
100#define PBC_CREDIT_RETURN BIT_ULL(25)
101#define PBC_INSERT_BYPASS_ICRC BIT_ULL(24)
102#define PBC_TEST_BAD_ICRC BIT_ULL(23)
103#define PBC_FECN BIT_ULL(22)
104
105
106#define PBC_IHCRC_LKDETH 0x0
107#define PBC_IHCRC_GKDETH 0x1
108#define PBC_IHCRC_NONE 0x2
109
110
111#define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT 32
112#define PBC_STATIC_RATE_CONTROL_COUNT_MASK 0xffffull
113#define PBC_STATIC_RATE_CONTROL_COUNT_SMASK \
114 (PBC_STATIC_RATE_CONTROL_COUNT_MASK << \
115 PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
116
117#define PBC_INSERT_HCRC_SHIFT 26
118#define PBC_INSERT_HCRC_MASK 0x3ull
119#define PBC_INSERT_HCRC_SMASK \
120 (PBC_INSERT_HCRC_MASK << PBC_INSERT_HCRC_SHIFT)
121
122#define PBC_VL_SHIFT 12
123#define PBC_VL_MASK 0xfull
124#define PBC_VL_SMASK (PBC_VL_MASK << PBC_VL_SHIFT)
125
126#define PBC_LENGTH_DWS_SHIFT 0
127#define PBC_LENGTH_DWS_MASK 0xfffull
128#define PBC_LENGTH_DWS_SMASK \
129 (PBC_LENGTH_DWS_MASK << PBC_LENGTH_DWS_SHIFT)
130
131
132#define CR_COUNTER_SHIFT 0
133#define CR_COUNTER_MASK 0x7ffull
134#define CR_COUNTER_SMASK (CR_COUNTER_MASK << CR_COUNTER_SHIFT)
135
136#define CR_STATUS_SHIFT 11
137#define CR_STATUS_MASK 0x1ull
138#define CR_STATUS_SMASK (CR_STATUS_MASK << CR_STATUS_SHIFT)
139
140#define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT 12
141#define CR_CREDIT_RETURN_DUE_TO_PBC_MASK 0x1ull
142#define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK \
143 (CR_CREDIT_RETURN_DUE_TO_PBC_MASK << \
144 CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT)
145
146#define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT 13
147#define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK 0x1ull
148#define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK \
149 (CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK << \
150 CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT)
151
152#define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT 14
153#define CR_CREDIT_RETURN_DUE_TO_ERR_MASK 0x1ull
154#define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK \
155 (CR_CREDIT_RETURN_DUE_TO_ERR_MASK << \
156 CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT)
157
158#define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT 15
159#define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK 0x1ull
160#define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK \
161 (CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \
162 CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT)
163
164
165#define IS_GENERAL_ERR_START 0
166#define IS_SDMAENG_ERR_START 16
167#define IS_SENDCTXT_ERR_START 32
168#define IS_SDMA_START 192
169#define IS_VARIOUS_START 240
170#define IS_DC_START 248
171#define IS_RCVAVAIL_START 256
172#define IS_RCVURGENT_START 416
173#define IS_SENDCREDIT_START 576
174#define IS_RESERVED_START 736
175#define IS_MAX_SOURCES 768
176
177
178#define IS_GENERAL_ERR_END IS_SDMAENG_ERR_START
179#define IS_SDMAENG_ERR_END IS_SENDCTXT_ERR_START
180#define IS_SENDCTXT_ERR_END IS_SDMA_START
181#define IS_SDMA_END IS_VARIOUS_START
182#define IS_VARIOUS_END IS_DC_START
183#define IS_DC_END IS_RCVAVAIL_START
184#define IS_RCVAVAIL_END IS_RCVURGENT_START
185#define IS_RCVURGENT_END IS_SENDCREDIT_START
186#define IS_SENDCREDIT_END IS_RESERVED_START
187#define IS_RESERVED_END IS_MAX_SOURCES
188
189
190#define QSFP1_INT 242
191#define QSFP2_INT 243
192
193
194#define LSTATE_DOWN 0x1
195#define LSTATE_INIT 0x2
196#define LSTATE_ARMED 0x3
197#define LSTATE_ACTIVE 0x4
198
199
200#define LCB_RX_FPE_TX_FPE_INTO_RESET (DCC_CFG_RESET_RESET_LCB | \
201 DCC_CFG_RESET_RESET_TX_FPE | \
202 DCC_CFG_RESET_RESET_RX_FPE | \
203 DCC_CFG_RESET_ENABLE_CCLK_BCC)
204
205
206#define LCB_RX_FPE_TX_FPE_OUT_OF_RESET DCC_CFG_RESET_ENABLE_CCLK_BCC
207
208
209#define PLS_DISABLED 0x30
210#define PLS_OFFLINE 0x90
211#define PLS_OFFLINE_QUIET 0x90
212#define PLS_OFFLINE_PLANNED_DOWN_INFORM 0x91
213#define PLS_OFFLINE_READY_TO_QUIET_LT 0x92
214#define PLS_OFFLINE_REPORT_FAILURE 0x93
215#define PLS_OFFLINE_READY_TO_QUIET_BCC 0x94
216#define PLS_OFFLINE_QUIET_DURATION 0x95
217#define PLS_POLLING 0x20
218#define PLS_POLLING_QUIET 0x20
219#define PLS_POLLING_ACTIVE 0x21
220#define PLS_CONFIGPHY 0x40
221#define PLS_CONFIGPHY_DEBOUCE 0x40
222#define PLS_CONFIGPHY_ESTCOMM 0x41
223#define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT 0x42
224#define PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE 0x43
225#define PLS_CONFIGPHY_OPTEQ 0x44
226#define PLS_CONFIGPHY_OPTEQ_OPTIMIZING 0x44
227#define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE 0x45
228#define PLS_CONFIGPHY_VERIFYCAP 0x46
229#define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE 0x46
230#define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE 0x47
231#define PLS_CONFIGLT 0x48
232#define PLS_CONFIGLT_CONFIGURE 0x48
233#define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE 0x49
234#define PLS_LINKUP 0x50
235#define PLS_PHYTEST 0xB0
236#define PLS_INTERNAL_SERDES_LOOPBACK 0xe1
237#define PLS_QUICK_LINKUP 0xe2
238
239
240#define HCMD_LOAD_CONFIG_DATA 0x01
241#define HCMD_READ_CONFIG_DATA 0x02
242#define HCMD_CHANGE_PHY_STATE 0x03
243#define HCMD_SEND_LCB_IDLE_MSG 0x04
244#define HCMD_MISC 0x05
245#define HCMD_READ_LCB_IDLE_MSG 0x06
246#define HCMD_READ_LCB_CSR 0x07
247#define HCMD_WRITE_LCB_CSR 0x08
248#define HCMD_INTERFACE_TEST 0xff
249
250
251#define HCMD_SUCCESS 2
252
253
254#define SPICO_ROM_FAILED BIT(0)
255#define UNKNOWN_FRAME BIT(1)
256#define TARGET_BER_NOT_MET BIT(2)
257#define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3)
258#define FAILED_SERDES_INIT BIT(4)
259#define FAILED_LNI_POLLING BIT(5)
260#define FAILED_LNI_DEBOUNCE BIT(6)
261#define FAILED_LNI_ESTBCOMM BIT(7)
262#define FAILED_LNI_OPTEQ BIT(8)
263#define FAILED_LNI_VERIFY_CAP1 BIT(9)
264#define FAILED_LNI_VERIFY_CAP2 BIT(10)
265#define FAILED_LNI_CONFIGLT BIT(11)
266#define HOST_HANDSHAKE_TIMEOUT BIT(12)
267#define EXTERNAL_DEVICE_REQ_TIMEOUT BIT(13)
268
269#define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \
270 | FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \
271 | FAILED_LNI_VERIFY_CAP1 \
272 | FAILED_LNI_VERIFY_CAP2 \
273 | FAILED_LNI_CONFIGLT | HOST_HANDSHAKE_TIMEOUT \
274 | EXTERNAL_DEVICE_REQ_TIMEOUT)
275
276
277#define HOST_REQ_DONE BIT(0)
278#define BC_PWR_MGM_MSG BIT(1)
279#define BC_SMA_MSG BIT(2)
280#define BC_BCC_UNKNOWN_MSG BIT(3)
281#define BC_IDLE_UNKNOWN_MSG BIT(4)
282#define EXT_DEVICE_CFG_REQ BIT(5)
283#define VERIFY_CAP_FRAME BIT(6)
284#define LINKUP_ACHIEVED BIT(7)
285#define LINK_GOING_DOWN BIT(8)
286#define LINK_WIDTH_DOWNGRADED BIT(9)
287
288
289#define HREQ_LOAD_CONFIG 0x01
290#define HREQ_SAVE_CONFIG 0x02
291#define HREQ_READ_CONFIG 0x03
292#define HREQ_SET_TX_EQ_ABS 0x04
293#define HREQ_SET_TX_EQ_REL 0x05
294#define HREQ_ENABLE 0x06
295#define HREQ_LCB_RESET 0x07
296#define HREQ_CONFIG_DONE 0xfe
297#define HREQ_INTERFACE_TEST 0xff
298
299
300#define HREQ_INVALID 0x01
301#define HREQ_SUCCESS 0x02
302#define HREQ_NOT_SUPPORTED 0x03
303#define HREQ_FEATURE_NOT_SUPPORTED 0x04
304#define HREQ_REQUEST_REJECTED 0xfe
305#define HREQ_EXECUTION_ONGOING 0xff
306
307
308#define HCMD_MISC_REQUEST_LCB_ACCESS 0x1
309#define HCMD_MISC_GRANT_LCB_ACCESS 0x2
310
311
312#define IDLE_PHYSICAL_LINK_MGMT 0x1
313#define IDLE_CRU 0x2
314#define IDLE_SMA 0x3
315#define IDLE_POWER_MGMT 0x4
316
317
318#define IDLE_PAYLOAD_MASK 0xffffffffffull
319#define IDLE_PAYLOAD_SHIFT 8
320#define IDLE_MSG_TYPE_MASK 0xf
321#define IDLE_MSG_TYPE_SHIFT 0
322
323
324#define READ_IDLE_MSG_TYPE_MASK 0xf
325#define READ_IDLE_MSG_TYPE_SHIFT 0
326
327
328#define SMA_IDLE_ARM 1
329#define SMA_IDLE_ACTIVE 2
330
331
332#define DISABLE_SELF_GUID_CHECK 0x2
333
334
335#define BAD_L2_ERR 0x6
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338
339
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341
342
343
344#define MIN_EAGER_BUFFER (4 * 1024)
345#define MAX_EAGER_BUFFER (256 * 1024)
346#define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20))
347#define MAX_EXPECTED_BUFFER (2048 * 1024)
348
349
350
351
352
353#define RCV_SHIFT 3
354#define RCV_INCREMENT BIT(RCV_SHIFT)
355
356
357
358
359
360#define HDRQ_SIZE_SHIFT 5
361#define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT)
362
363
364
365
366#define FREEZE_ABORT 0x01
367#define FREEZE_SELF 0x02
368#define FREEZE_LINK_DOWN 0x04
369
370
371
372
373#define ICODE_RTL_SILICON 0x00
374#define ICODE_RTL_VCS_SIMULATION 0x01
375#define ICODE_FPGA_EMULATION 0x02
376#define ICODE_FUNCTIONAL_SIMULATOR 0x03
377
378
379
380
381#define DC8051_DATA_MEM_SIZE 0x1000
382
383
384
385
386#define NUM_GENERAL_FIELDS 0x17
387#define NUM_LANE_FIELDS 0x8
388
389
390#define LINK_OPTIMIZATION_SETTINGS 0x00
391#define LINK_TUNING_PARAMETERS 0x02
392#define DC_HOST_COMM_SETTINGS 0x03
393#define TX_SETTINGS 0x06
394#define VERIFY_CAP_LOCAL_PHY 0x07
395#define VERIFY_CAP_LOCAL_FABRIC 0x08
396#define VERIFY_CAP_LOCAL_LINK_MODE 0x09
397#define LOCAL_DEVICE_ID 0x0a
398#define RESERVED_REGISTERS 0x0b
399#define LOCAL_LNI_INFO 0x0c
400#define REMOTE_LNI_INFO 0x0d
401#define MISC_STATUS 0x0e
402#define VERIFY_CAP_REMOTE_PHY 0x0f
403#define VERIFY_CAP_REMOTE_FABRIC 0x10
404#define VERIFY_CAP_REMOTE_LINK_WIDTH 0x11
405#define LAST_LOCAL_STATE_COMPLETE 0x12
406#define LAST_REMOTE_STATE_COMPLETE 0x13
407#define LINK_QUALITY_INFO 0x14
408#define REMOTE_DEVICE_ID 0x15
409#define LINK_DOWN_REASON 0x16
410#define VERSION_PATCH 0x16
411
412
413#define TX_EQ_SETTINGS 0x00
414#define CHANNEL_LOSS_SETTINGS 0x05
415
416
417#define GENERAL_CONFIG 4
418
419
420#define TUNING_METHOD_SHIFT 24
421
422
423#define ENABLE_EXT_DEV_CONFIG_SHIFT 24
424
425
426#define LOAD_DATA_FIELD_ID_SHIFT 40
427#define LOAD_DATA_FIELD_ID_MASK 0xfull
428#define LOAD_DATA_LANE_ID_SHIFT 32
429#define LOAD_DATA_LANE_ID_MASK 0xfull
430#define LOAD_DATA_DATA_SHIFT 0x0
431#define LOAD_DATA_DATA_MASK 0xffffffffull
432
433
434#define READ_DATA_FIELD_ID_SHIFT 40
435#define READ_DATA_FIELD_ID_MASK 0xffull
436#define READ_DATA_LANE_ID_SHIFT 32
437#define READ_DATA_LANE_ID_MASK 0xffull
438#define READ_DATA_DATA_SHIFT 0x0
439#define READ_DATA_DATA_MASK 0xffffffffull
440
441
442#define ENABLE_LANE_TX_SHIFT 0
443#define ENABLE_LANE_TX_MASK 0xff
444#define TX_POLARITY_INVERSION_SHIFT 8
445#define TX_POLARITY_INVERSION_MASK 0xff
446#define RX_POLARITY_INVERSION_SHIFT 16
447#define RX_POLARITY_INVERSION_MASK 0xff
448#define MAX_RATE_SHIFT 24
449#define MAX_RATE_MASK 0xff
450
451
452#define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 0x4
453#define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK 0x1
454#define POWER_MANAGEMENT_SHIFT 0x0
455#define POWER_MANAGEMENT_MASK 0xf
456
457
458#define SPICO_FW_VERSION 0x7
459
460
461#define SPICO_ROM_VERSION_SHIFT 0
462#define SPICO_ROM_VERSION_MASK 0xffff
463#define SPICO_ROM_PROD_ID_SHIFT 16
464#define SPICO_ROM_PROD_ID_MASK 0xffff
465
466
467#define VAU_SHIFT 0
468#define VAU_MASK 0x0007
469#define Z_SHIFT 3
470#define Z_MASK 0x0001
471#define VCU_SHIFT 4
472#define VCU_MASK 0x0007
473#define VL15BUF_SHIFT 8
474#define VL15BUF_MASK 0x0fff
475#define CRC_SIZES_SHIFT 20
476#define CRC_SIZES_MASK 0x7
477
478
479#define LINK_WIDTH_SHIFT 0
480#define LINK_WIDTH_MASK 0xffff
481#define LOCAL_FLAG_BITS_SHIFT 16
482#define LOCAL_FLAG_BITS_MASK 0xff
483#define MISC_CONFIG_BITS_SHIFT 24
484#define MISC_CONFIG_BITS_MASK 0xff
485
486
487#define REMOTE_TX_RATE_SHIFT 16
488#define REMOTE_TX_RATE_MASK 0xff
489
490
491#define LOCAL_DEVICE_REV_SHIFT 0
492#define LOCAL_DEVICE_REV_MASK 0xff
493#define LOCAL_DEVICE_ID_SHIFT 8
494#define LOCAL_DEVICE_ID_MASK 0xffff
495
496
497#define REMOTE_DEVICE_REV_SHIFT 0
498#define REMOTE_DEVICE_REV_MASK 0xff
499#define REMOTE_DEVICE_ID_SHIFT 8
500#define REMOTE_DEVICE_ID_MASK 0xffff
501
502
503#define ENABLE_LANE_RX_SHIFT 16
504#define ENABLE_LANE_RX_MASK 0xff
505
506
507#define MGMT_ALLOWED_SHIFT 23
508#define MGMT_ALLOWED_MASK 0x1
509
510
511#define LINK_QUALITY_SHIFT 24
512#define LINK_QUALITY_MASK 0x7
513
514
515
516
517
518#define DOWN_REMOTE_REASON_SHIFT 16
519#define DOWN_REMOTE_REASON_MASK 0xff
520
521#define HOST_INTERFACE_VERSION 1
522#define HOST_INTERFACE_VERSION_SHIFT 16
523#define HOST_INTERFACE_VERSION_MASK 0xff
524
525
526#define PWRM_BER_CONTROL 0x1
527#define PWRM_BANDWIDTH_CONTROL 0x2
528
529
530#define LDR_LINK_TRANSFER_ACTIVE_LOW 0xa
531#define LDR_RECEIVED_LINKDOWN_IDLE_MSG 0xb
532#define LDR_RECEIVED_HOST_OFFLINE_REQ 0xc
533
534
535enum {
536 CAP_CRC_14B = (1 << 0),
537 CAP_CRC_48B = (1 << 1),
538 CAP_CRC_12B_16B_PER_LANE = (1 << 2)
539};
540
541#define SUPPORTED_CRCS (CAP_CRC_14B | CAP_CRC_48B)
542
543
544#define STS_FM_VERSION_MINOR_SHIFT 16
545#define STS_FM_VERSION_MINOR_MASK 0xff
546#define STS_FM_VERSION_MAJOR_SHIFT 24
547#define STS_FM_VERSION_MAJOR_MASK 0xff
548#define STS_FM_VERSION_PATCH_SHIFT 24
549#define STS_FM_VERSION_PATCH_MASK 0xff
550
551
552#define LCB_CRC_16B 0x0
553#define LCB_CRC_14B 0x1
554#define LCB_CRC_48B 0x2
555#define LCB_CRC_12B_16B_PER_LANE 0x3
556
557
558
559
560
561enum {
562 PORT_LTP_CRC_MODE_NONE = 0,
563 PORT_LTP_CRC_MODE_14 = 1,
564 PORT_LTP_CRC_MODE_16 = 2,
565 PORT_LTP_CRC_MODE_48 = 4,
566
567 PORT_LTP_CRC_MODE_PER_LANE = 8
568
569};
570
571
572#define LINK_RESTART_DELAY 1000
573#define TIMEOUT_8051_START 5000
574#define DC8051_COMMAND_TIMEOUT 1000
575#define FREEZE_STATUS_TIMEOUT 20
576#define VL_STATUS_CLEAR_TIMEOUT 5000
577#define CCE_STATUS_TIMEOUT 10
578
579
580#define ASIC_CCLOCK_PS 1242
581#define FPGA_CCLOCK_PS 30300
582
583
584
585
586
587#define DRIVER_MISC_MASK \
588 (~(MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK \
589 | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK))
590
591
592#define LOOPBACK_NONE 0
593#define LOOPBACK_SERDES 1
594#define LOOPBACK_LCB 2
595#define LOOPBACK_CABLE 3
596
597
598#define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT 0
599#define EXT_CFG_LCB_RESET_SUPPORTED_SHIFT 3
600
601
602u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
603void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
604
605
606
607
608
609
610static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt,
611 u32 offset0)
612{
613
614 return read_csr(dd, offset0 + (0x100 * ctxt));
615}
616
617static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt,
618 u32 offset0, u64 value)
619{
620
621 write_csr(dd, offset0 + (0x100 * ctxt), value);
622}
623
624int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data);
625int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data);
626
627void __iomem *get_csr_addr(
628 const struct hfi1_devdata *dd,
629 u32 offset);
630
631static inline void __iomem *get_kctxt_csr_addr(
632 const struct hfi1_devdata *dd,
633 int ctxt,
634 u32 offset0)
635{
636 return get_csr_addr(dd, offset0 + (0x100 * ctxt));
637}
638
639
640
641
642
643
644
645static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt,
646 u32 offset0)
647{
648
649 return read_csr(dd, offset0 + (0x1000 * ctxt));
650}
651
652static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt,
653 u32 offset0, u64 value)
654{
655
656 write_csr(dd, offset0 + (0x1000 * ctxt), value);
657}
658
659u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
660 u32 dw_len);
661
662
663#define SBUS_MASTER_BROADCAST 0xfd
664#define NUM_PCIE_SERDES 16
665extern const u8 pcie_serdes_broadcast[];
666extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES];
667
668
669#define RESET_SBUS_RECEIVER 0x20
670#define WRITE_SBUS_RECEIVER 0x21
671#define READ_SBUS_RECEIVER 0x22
672void sbus_request(struct hfi1_devdata *dd,
673 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
674int sbus_request_slow(struct hfi1_devdata *dd,
675 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
676void set_sbus_fast_mode(struct hfi1_devdata *dd);
677void clear_sbus_fast_mode(struct hfi1_devdata *dd);
678int hfi1_firmware_init(struct hfi1_devdata *dd);
679int load_pcie_firmware(struct hfi1_devdata *dd);
680int load_firmware(struct hfi1_devdata *dd);
681void dispose_firmware(void);
682int acquire_hw_mutex(struct hfi1_devdata *dd);
683void release_hw_mutex(struct hfi1_devdata *dd);
684
685
686
687
688
689
690
691
692
693#define CR_SBUS 0x01
694#define CR_EPROM 0x02
695#define CR_I2C1 0x04
696#define CR_I2C2 0x08
697#define CR_DYN_SHIFT 8
698#define CR_DYN_MASK ((1ull << CR_DYN_SHIFT) - 1)
699
700
701
702
703
704
705#define CR_THERM_INIT 0x010000
706
707int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait);
708void release_chip_resource(struct hfi1_devdata *dd, u32 resource);
709bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
710 const char *func);
711void init_chip_resources(struct hfi1_devdata *dd);
712void finish_chip_resources(struct hfi1_devdata *dd);
713
714
715#define SBUS_TIMEOUT 4000
716
717
718#define QSFP_WAIT 20000
719
720void fabric_serdes_reset(struct hfi1_devdata *dd);
721int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result);
722
723
724void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
725 u8 *ver_patch);
726int write_host_interface_version(struct hfi1_devdata *dd, u8 version);
727void read_guid(struct hfi1_devdata *dd);
728int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout);
729void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
730 u8 neigh_reason, u8 rem_reason);
731int set_link_state(struct hfi1_pportdata *, u32 state);
732int port_ltp_to_cap(int port_ltp);
733void handle_verify_cap(struct work_struct *work);
734void handle_freeze(struct work_struct *work);
735void handle_link_up(struct work_struct *work);
736void handle_link_down(struct work_struct *work);
737void handle_link_downgrade(struct work_struct *work);
738void handle_link_bounce(struct work_struct *work);
739void handle_start_link(struct work_struct *work);
740void handle_sma_message(struct work_struct *work);
741int reset_qsfp(struct hfi1_pportdata *ppd);
742void qsfp_event(struct work_struct *work);
743void start_freeze_handling(struct hfi1_pportdata *ppd, int flags);
744int send_idle_sma(struct hfi1_devdata *dd, u64 message);
745int load_8051_config(struct hfi1_devdata *, u8, u8, u32);
746int read_8051_config(struct hfi1_devdata *, u8, u8, u32 *);
747int start_link(struct hfi1_pportdata *ppd);
748int bringup_serdes(struct hfi1_pportdata *ppd);
749void set_intr_state(struct hfi1_devdata *dd, u32 enable);
750bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
751 bool refresh_widths);
752void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
753 u32 intr_adjust, u32 npkts);
754int stop_drain_data_vls(struct hfi1_devdata *dd);
755int open_fill_data_vls(struct hfi1_devdata *dd);
756u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns);
757u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock);
758void get_linkup_link_widths(struct hfi1_pportdata *ppd);
759void read_ltp_rtt(struct hfi1_devdata *dd);
760void clear_linkup_counters(struct hfi1_devdata *dd);
761u32 hdrqempty(struct hfi1_ctxtdata *rcd);
762int is_ax(struct hfi1_devdata *dd);
763int is_bx(struct hfi1_devdata *dd);
764u32 read_physical_state(struct hfi1_devdata *dd);
765u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate);
766const char *opa_lstate_name(u32 lstate);
767const char *opa_pstate_name(u32 pstate);
768u32 driver_pstate(struct hfi1_pportdata *ppd);
769u32 driver_lstate(struct hfi1_pportdata *ppd);
770
771int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
772int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
773#define LCB_START DC_LCB_CSRS
774#define LCB_END DC_8051_CSRS
775static inline int is_lcb_offset(u32 offset)
776{
777 return (offset >= LCB_START && offset < LCB_END);
778}
779
780extern uint num_vls;
781
782extern uint disable_integrity;
783u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl);
784u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data);
785u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl);
786u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data);
787u32 read_logical_state(struct hfi1_devdata *dd);
788void force_recv_intr(struct hfi1_ctxtdata *rcd);
789
790
791enum {
792 C_VL_0 = 0,
793 C_VL_1,
794 C_VL_2,
795 C_VL_3,
796 C_VL_4,
797 C_VL_5,
798 C_VL_6,
799 C_VL_7,
800 C_VL_15,
801 C_VL_COUNT
802};
803
804static inline int vl_from_idx(int idx)
805{
806 return (idx == C_VL_15 ? 15 : idx);
807}
808
809static inline int idx_from_vl(int vl)
810{
811 return (vl == 15 ? C_VL_15 : vl);
812}
813
814
815enum {
816 C_RCV_OVF = 0,
817 C_RX_TID_FULL,
818 C_RX_TID_INVALID,
819 C_RX_TID_FLGMS,
820 C_RX_CTX_EGRS,
821 C_RCV_TID_FLSMS,
822 C_CCE_PCI_CR_ST,
823 C_CCE_PCI_TR_ST,
824 C_CCE_PIO_WR_ST,
825 C_CCE_ERR_INT,
826 C_CCE_SDMA_INT,
827 C_CCE_MISC_INT,
828 C_CCE_RCV_AV_INT,
829 C_CCE_RCV_URG_INT,
830 C_CCE_SEND_CR_INT,
831 C_DC_UNC_ERR,
832 C_DC_RCV_ERR,
833 C_DC_FM_CFG_ERR,
834 C_DC_RMT_PHY_ERR,
835 C_DC_DROPPED_PKT,
836 C_DC_MC_XMIT_PKTS,
837 C_DC_MC_RCV_PKTS,
838 C_DC_XMIT_CERR,
839 C_DC_RCV_CERR,
840 C_DC_RCV_FCC,
841 C_DC_XMIT_FCC,
842 C_DC_XMIT_FLITS,
843 C_DC_RCV_FLITS,
844 C_DC_XMIT_PKTS,
845 C_DC_RCV_PKTS,
846 C_DC_RX_FLIT_VL,
847 C_DC_RX_PKT_VL,
848 C_DC_RCV_FCN,
849 C_DC_RCV_FCN_VL,
850 C_DC_RCV_BCN,
851 C_DC_RCV_BCN_VL,
852 C_DC_RCV_BBL,
853 C_DC_RCV_BBL_VL,
854 C_DC_MARK_FECN,
855 C_DC_MARK_FECN_VL,
856 C_DC_TOTAL_CRC,
857 C_DC_CRC_LN0,
858 C_DC_CRC_LN1,
859 C_DC_CRC_LN2,
860 C_DC_CRC_LN3,
861 C_DC_CRC_MULT_LN,
862 C_DC_TX_REPLAY,
863 C_DC_RX_REPLAY,
864 C_DC_SEQ_CRC_CNT,
865 C_DC_ESC0_ONLY_CNT,
866 C_DC_ESC0_PLUS1_CNT,
867 C_DC_ESC0_PLUS2_CNT,
868 C_DC_REINIT_FROM_PEER_CNT,
869 C_DC_SBE_CNT,
870 C_DC_MISC_FLG_CNT,
871 C_DC_PRF_GOOD_LTP_CNT,
872 C_DC_PRF_ACCEPTED_LTP_CNT,
873 C_DC_PRF_RX_FLIT_CNT,
874 C_DC_PRF_TX_FLIT_CNT,
875 C_DC_PRF_CLK_CNTR,
876 C_DC_PG_DBG_FLIT_CRDTS_CNT,
877 C_DC_PG_STS_PAUSE_COMPLETE_CNT,
878 C_DC_PG_STS_TX_SBE_CNT,
879 C_DC_PG_STS_TX_MBE_CNT,
880 C_SW_CPU_INTR,
881 C_SW_CPU_RCV_LIM,
882 C_SW_VTX_WAIT,
883 C_SW_PIO_WAIT,
884 C_SW_PIO_DRAIN,
885 C_SW_KMEM_WAIT,
886 C_SW_SEND_SCHED,
887 C_SDMA_DESC_FETCHED_CNT,
888 C_SDMA_INT_CNT,
889 C_SDMA_ERR_CNT,
890 C_SDMA_IDLE_INT_CNT,
891 C_SDMA_PROGRESS_INT_CNT,
892
893 C_MISC_PLL_LOCK_FAIL_ERR,
894 C_MISC_MBIST_FAIL_ERR,
895 C_MISC_INVALID_EEP_CMD_ERR,
896 C_MISC_EFUSE_DONE_PARITY_ERR,
897 C_MISC_EFUSE_WRITE_ERR,
898 C_MISC_EFUSE_READ_BAD_ADDR_ERR,
899 C_MISC_EFUSE_CSR_PARITY_ERR,
900 C_MISC_FW_AUTH_FAILED_ERR,
901 C_MISC_KEY_MISMATCH_ERR,
902 C_MISC_SBUS_WRITE_FAILED_ERR,
903 C_MISC_CSR_WRITE_BAD_ADDR_ERR,
904 C_MISC_CSR_READ_BAD_ADDR_ERR,
905 C_MISC_CSR_PARITY_ERR,
906
907
908
909
910
911
912 C_CCE_ERR_STATUS_AGGREGATED_CNT,
913 C_CCE_MSIX_CSR_PARITY_ERR,
914 C_CCE_INT_MAP_UNC_ERR,
915 C_CCE_INT_MAP_COR_ERR,
916 C_CCE_MSIX_TABLE_UNC_ERR,
917 C_CCE_MSIX_TABLE_COR_ERR,
918 C_CCE_RXDMA_CONV_FIFO_PARITY_ERR,
919 C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR,
920 C_CCE_SEG_WRITE_BAD_ADDR_ERR,
921 C_CCE_SEG_READ_BAD_ADDR_ERR,
922 C_LA_TRIGGERED,
923 C_CCE_TRGT_CPL_TIMEOUT_ERR,
924 C_PCIC_RECEIVE_PARITY_ERR,
925 C_PCIC_TRANSMIT_BACK_PARITY_ERR,
926 C_PCIC_TRANSMIT_FRONT_PARITY_ERR,
927 C_PCIC_CPL_DAT_Q_UNC_ERR,
928 C_PCIC_CPL_HD_Q_UNC_ERR,
929 C_PCIC_POST_DAT_Q_UNC_ERR,
930 C_PCIC_POST_HD_Q_UNC_ERR,
931 C_PCIC_RETRY_SOT_MEM_UNC_ERR,
932 C_PCIC_RETRY_MEM_UNC_ERR,
933 C_PCIC_N_POST_DAT_Q_PARITY_ERR,
934 C_PCIC_N_POST_H_Q_PARITY_ERR,
935 C_PCIC_CPL_DAT_Q_COR_ERR,
936 C_PCIC_CPL_HD_Q_COR_ERR,
937 C_PCIC_POST_DAT_Q_COR_ERR,
938 C_PCIC_POST_HD_Q_COR_ERR,
939 C_PCIC_RETRY_SOT_MEM_COR_ERR,
940 C_PCIC_RETRY_MEM_COR_ERR,
941 C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR,
942 C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR,
943 C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR,
944 C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR,
945 C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR,
946 C_CCE_CSR_CFG_BUS_PARITY_ERR,
947 C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR,
948 C_CCE_RSPD_DATA_PARITY_ERR,
949 C_CCE_TRGT_ACCESS_ERR,
950 C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR,
951 C_CCE_CSR_WRITE_BAD_ADDR_ERR,
952 C_CCE_CSR_READ_BAD_ADDR_ERR,
953 C_CCE_CSR_PARITY_ERR,
954
955 C_RX_CSR_PARITY_ERR,
956 C_RX_CSR_WRITE_BAD_ADDR_ERR,
957 C_RX_CSR_READ_BAD_ADDR_ERR,
958 C_RX_DMA_CSR_UNC_ERR,
959 C_RX_DMA_DQ_FSM_ENCODING_ERR,
960 C_RX_DMA_EQ_FSM_ENCODING_ERR,
961 C_RX_DMA_CSR_PARITY_ERR,
962 C_RX_RBUF_DATA_COR_ERR,
963 C_RX_RBUF_DATA_UNC_ERR,
964 C_RX_DMA_DATA_FIFO_RD_COR_ERR,
965 C_RX_DMA_DATA_FIFO_RD_UNC_ERR,
966 C_RX_DMA_HDR_FIFO_RD_COR_ERR,
967 C_RX_DMA_HDR_FIFO_RD_UNC_ERR,
968 C_RX_RBUF_DESC_PART2_COR_ERR,
969 C_RX_RBUF_DESC_PART2_UNC_ERR,
970 C_RX_RBUF_DESC_PART1_COR_ERR,
971 C_RX_RBUF_DESC_PART1_UNC_ERR,
972 C_RX_HQ_INTR_FSM_ERR,
973 C_RX_HQ_INTR_CSR_PARITY_ERR,
974 C_RX_LOOKUP_CSR_PARITY_ERR,
975 C_RX_LOOKUP_RCV_ARRAY_COR_ERR,
976 C_RX_LOOKUP_RCV_ARRAY_UNC_ERR,
977 C_RX_LOOKUP_DES_PART2_PARITY_ERR,
978 C_RX_LOOKUP_DES_PART1_UNC_COR_ERR,
979 C_RX_LOOKUP_DES_PART1_UNC_ERR,
980 C_RX_RBUF_NEXT_FREE_BUF_COR_ERR,
981 C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR,
982 C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR,
983 C_RX_RBUF_FL_INITDONE_PARITY_ERR,
984 C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR,
985 C_RX_RBUF_FL_RD_ADDR_PARITY_ERR,
986 C_RX_RBUF_EMPTY_ERR,
987 C_RX_RBUF_FULL_ERR,
988 C_RX_RBUF_BAD_LOOKUP_ERR,
989 C_RX_RBUF_CTX_ID_PARITY_ERR,
990 C_RX_RBUF_CSR_QEOPDW_PARITY_ERR,
991 C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR,
992 C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR,
993 C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR,
994 C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR,
995 C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR,
996 C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR,
997 C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR,
998 C_RX_RBUF_BLOCK_LIST_READ_COR_ERR,
999 C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR,
1000 C_RX_RBUF_LOOKUP_DES_COR_ERR,
1001 C_RX_RBUF_LOOKUP_DES_UNC_ERR,
1002 C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR,
1003 C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR,
1004 C_RX_RBUF_FREE_LIST_COR_ERR,
1005 C_RX_RBUF_FREE_LIST_UNC_ERR,
1006 C_RX_RCV_FSM_ENCODING_ERR,
1007 C_RX_DMA_FLAG_COR_ERR,
1008 C_RX_DMA_FLAG_UNC_ERR,
1009 C_RX_DC_SOP_EOP_PARITY_ERR,
1010 C_RX_RCV_CSR_PARITY_ERR,
1011 C_RX_RCV_QP_MAP_TABLE_COR_ERR,
1012 C_RX_RCV_QP_MAP_TABLE_UNC_ERR,
1013 C_RX_RCV_DATA_COR_ERR,
1014 C_RX_RCV_DATA_UNC_ERR,
1015 C_RX_RCV_HDR_COR_ERR,
1016 C_RX_RCV_HDR_UNC_ERR,
1017 C_RX_DC_INTF_PARITY_ERR,
1018 C_RX_DMA_CSR_COR_ERR,
1019
1020 C_PIO_PEC_SOP_HEAD_PARITY_ERR,
1021 C_PIO_PCC_SOP_HEAD_PARITY_ERR,
1022 C_PIO_LAST_RETURNED_CNT_PARITY_ERR,
1023 C_PIO_CURRENT_FREE_CNT_PARITY_ERR,
1024 C_PIO_RSVD_31_ERR,
1025 C_PIO_RSVD_30_ERR,
1026 C_PIO_PPMC_SOP_LEN_ERR,
1027 C_PIO_PPMC_BQC_MEM_PARITY_ERR,
1028 C_PIO_VL_FIFO_PARITY_ERR,
1029 C_PIO_VLF_SOP_PARITY_ERR,
1030 C_PIO_VLF_V1_LEN_PARITY_ERR,
1031 C_PIO_BLOCK_QW_COUNT_PARITY_ERR,
1032 C_PIO_WRITE_QW_VALID_PARITY_ERR,
1033 C_PIO_STATE_MACHINE_ERR,
1034 C_PIO_WRITE_DATA_PARITY_ERR,
1035 C_PIO_HOST_ADDR_MEM_COR_ERR,
1036 C_PIO_HOST_ADDR_MEM_UNC_ERR,
1037 C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR,
1038 C_PIO_INIT_SM_IN_ERR,
1039 C_PIO_PPMC_PBL_FIFO_ERR,
1040 C_PIO_CREDIT_RET_FIFO_PARITY_ERR,
1041 C_PIO_V1_LEN_MEM_BANK1_COR_ERR,
1042 C_PIO_V1_LEN_MEM_BANK0_COR_ERR,
1043 C_PIO_V1_LEN_MEM_BANK1_UNC_ERR,
1044 C_PIO_V1_LEN_MEM_BANK0_UNC_ERR,
1045 C_PIO_SM_PKT_RESET_PARITY_ERR,
1046 C_PIO_PKT_EVICT_FIFO_PARITY_ERR,
1047 C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR,
1048 C_PIO_SBRDCTL_CRREL_PARITY_ERR,
1049 C_PIO_PEC_FIFO_PARITY_ERR,
1050 C_PIO_PCC_FIFO_PARITY_ERR,
1051 C_PIO_SB_MEM_FIFO1_ERR,
1052 C_PIO_SB_MEM_FIFO0_ERR,
1053 C_PIO_CSR_PARITY_ERR,
1054 C_PIO_WRITE_ADDR_PARITY_ERR,
1055 C_PIO_WRITE_BAD_CTXT_ERR,
1056
1057 C_SDMA_PCIE_REQ_TRACKING_COR_ERR,
1058 C_SDMA_PCIE_REQ_TRACKING_UNC_ERR,
1059 C_SDMA_CSR_PARITY_ERR,
1060 C_SDMA_RPY_TAG_ERR,
1061
1062 C_TX_READ_PIO_MEMORY_CSR_UNC_ERR,
1063 C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR,
1064 C_TX_EGRESS_FIFO_COR_ERR,
1065 C_TX_READ_PIO_MEMORY_COR_ERR,
1066 C_TX_READ_SDMA_MEMORY_COR_ERR,
1067 C_TX_SB_HDR_COR_ERR,
1068 C_TX_CREDIT_OVERRUN_ERR,
1069 C_TX_LAUNCH_FIFO8_COR_ERR,
1070 C_TX_LAUNCH_FIFO7_COR_ERR,
1071 C_TX_LAUNCH_FIFO6_COR_ERR,
1072 C_TX_LAUNCH_FIFO5_COR_ERR,
1073 C_TX_LAUNCH_FIFO4_COR_ERR,
1074 C_TX_LAUNCH_FIFO3_COR_ERR,
1075 C_TX_LAUNCH_FIFO2_COR_ERR,
1076 C_TX_LAUNCH_FIFO1_COR_ERR,
1077 C_TX_LAUNCH_FIFO0_COR_ERR,
1078 C_TX_CREDIT_RETURN_VL_ERR,
1079 C_TX_HCRC_INSERTION_ERR,
1080 C_TX_EGRESS_FIFI_UNC_ERR,
1081 C_TX_READ_PIO_MEMORY_UNC_ERR,
1082 C_TX_READ_SDMA_MEMORY_UNC_ERR,
1083 C_TX_SB_HDR_UNC_ERR,
1084 C_TX_CREDIT_RETURN_PARITY_ERR,
1085 C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR,
1086 C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR,
1087 C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR,
1088 C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR,
1089 C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR,
1090 C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR,
1091 C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR,
1092 C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR,
1093 C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR,
1094 C_TX_SDMA15_DISALLOWED_PACKET_ERR,
1095 C_TX_SDMA14_DISALLOWED_PACKET_ERR,
1096 C_TX_SDMA13_DISALLOWED_PACKET_ERR,
1097 C_TX_SDMA12_DISALLOWED_PACKET_ERR,
1098 C_TX_SDMA11_DISALLOWED_PACKET_ERR,
1099 C_TX_SDMA10_DISALLOWED_PACKET_ERR,
1100 C_TX_SDMA9_DISALLOWED_PACKET_ERR,
1101 C_TX_SDMA8_DISALLOWED_PACKET_ERR,
1102 C_TX_SDMA7_DISALLOWED_PACKET_ERR,
1103 C_TX_SDMA6_DISALLOWED_PACKET_ERR,
1104 C_TX_SDMA5_DISALLOWED_PACKET_ERR,
1105 C_TX_SDMA4_DISALLOWED_PACKET_ERR,
1106 C_TX_SDMA3_DISALLOWED_PACKET_ERR,
1107 C_TX_SDMA2_DISALLOWED_PACKET_ERR,
1108 C_TX_SDMA1_DISALLOWED_PACKET_ERR,
1109 C_TX_SDMA0_DISALLOWED_PACKET_ERR,
1110 C_TX_CONFIG_PARITY_ERR,
1111 C_TX_SBRD_CTL_CSR_PARITY_ERR,
1112 C_TX_LAUNCH_CSR_PARITY_ERR,
1113 C_TX_ILLEGAL_CL_ERR,
1114 C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR,
1115 C_TX_RESERVED_10,
1116 C_TX_RESERVED_9,
1117 C_TX_SDMA_LAUNCH_INTF_PARITY_ERR,
1118 C_TX_PIO_LAUNCH_INTF_PARITY_ERR,
1119 C_TX_RESERVED_6,
1120 C_TX_INCORRECT_LINK_STATE_ERR,
1121 C_TX_LINK_DOWN_ERR,
1122 C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR,
1123 C_TX_RESERVED_2,
1124 C_TX_PKT_INTEGRITY_MEM_UNC_ERR,
1125 C_TX_PKT_INTEGRITY_MEM_COR_ERR,
1126
1127 C_SEND_CSR_WRITE_BAD_ADDR_ERR,
1128 C_SEND_CSR_READ_BAD_ADD_ERR,
1129 C_SEND_CSR_PARITY_ERR,
1130
1131 C_PIO_WRITE_OUT_OF_BOUNDS_ERR,
1132 C_PIO_WRITE_OVERFLOW_ERR,
1133 C_PIO_WRITE_CROSSES_BOUNDARY_ERR,
1134 C_PIO_DISALLOWED_PACKET_ERR,
1135 C_PIO_INCONSISTENT_SOP_ERR,
1136
1137 C_SDMA_HEADER_REQUEST_FIFO_COR_ERR,
1138 C_SDMA_HEADER_STORAGE_COR_ERR,
1139 C_SDMA_PACKET_TRACKING_COR_ERR,
1140 C_SDMA_ASSEMBLY_COR_ERR,
1141 C_SDMA_DESC_TABLE_COR_ERR,
1142 C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR,
1143 C_SDMA_HEADER_STORAGE_UNC_ERR,
1144 C_SDMA_PACKET_TRACKING_UNC_ERR,
1145 C_SDMA_ASSEMBLY_UNC_ERR,
1146 C_SDMA_DESC_TABLE_UNC_ERR,
1147 C_SDMA_TIMEOUT_ERR,
1148 C_SDMA_HEADER_LENGTH_ERR,
1149 C_SDMA_HEADER_ADDRESS_ERR,
1150 C_SDMA_HEADER_SELECT_ERR,
1151 C_SMDA_RESERVED_9,
1152 C_SDMA_PACKET_DESC_OVERFLOW_ERR,
1153 C_SDMA_LENGTH_MISMATCH_ERR,
1154 C_SDMA_HALT_ERR,
1155 C_SDMA_MEM_READ_ERR,
1156 C_SDMA_FIRST_DESC_ERR,
1157 C_SDMA_TAIL_OUT_OF_BOUNDS_ERR,
1158 C_SDMA_TOO_LONG_ERR,
1159 C_SDMA_GEN_MISMATCH_ERR,
1160 C_SDMA_WRONG_DW_ERR,
1161 DEV_CNTR_LAST
1162};
1163
1164
1165enum {
1166 C_TX_UNSUP_VL = 0,
1167 C_TX_INVAL_LEN,
1168 C_TX_MM_LEN_ERR,
1169 C_TX_UNDERRUN,
1170 C_TX_FLOW_STALL,
1171 C_TX_DROPPED,
1172 C_TX_HDR_ERR,
1173 C_TX_PKT,
1174 C_TX_WORDS,
1175 C_TX_WAIT,
1176 C_TX_FLIT_VL,
1177 C_TX_PKT_VL,
1178 C_TX_WAIT_VL,
1179 C_RX_PKT,
1180 C_RX_WORDS,
1181 C_SW_LINK_DOWN,
1182 C_SW_LINK_UP,
1183 C_SW_UNKNOWN_FRAME,
1184 C_SW_XMIT_DSCD,
1185 C_SW_XMIT_DSCD_VL,
1186 C_SW_XMIT_CSTR_ERR,
1187 C_SW_RCV_CSTR_ERR,
1188 C_SW_IBP_LOOP_PKTS,
1189 C_SW_IBP_RC_RESENDS,
1190 C_SW_IBP_RNR_NAKS,
1191 C_SW_IBP_OTHER_NAKS,
1192 C_SW_IBP_RC_TIMEOUTS,
1193 C_SW_IBP_PKT_DROPS,
1194 C_SW_IBP_DMA_WAIT,
1195 C_SW_IBP_RC_SEQNAK,
1196 C_SW_IBP_RC_DUPREQ,
1197 C_SW_IBP_RDMA_SEQ,
1198 C_SW_IBP_UNALIGNED,
1199 C_SW_IBP_SEQ_NAK,
1200 C_SW_CPU_RC_ACKS,
1201 C_SW_CPU_RC_QACKS,
1202 C_SW_CPU_RC_DELAYED_COMP,
1203 C_RCV_HDR_OVF_0,
1204 C_RCV_HDR_OVF_1,
1205 C_RCV_HDR_OVF_2,
1206 C_RCV_HDR_OVF_3,
1207 C_RCV_HDR_OVF_4,
1208 C_RCV_HDR_OVF_5,
1209 C_RCV_HDR_OVF_6,
1210 C_RCV_HDR_OVF_7,
1211 C_RCV_HDR_OVF_8,
1212 C_RCV_HDR_OVF_9,
1213 C_RCV_HDR_OVF_10,
1214 C_RCV_HDR_OVF_11,
1215 C_RCV_HDR_OVF_12,
1216 C_RCV_HDR_OVF_13,
1217 C_RCV_HDR_OVF_14,
1218 C_RCV_HDR_OVF_15,
1219 C_RCV_HDR_OVF_16,
1220 C_RCV_HDR_OVF_17,
1221 C_RCV_HDR_OVF_18,
1222 C_RCV_HDR_OVF_19,
1223 C_RCV_HDR_OVF_20,
1224 C_RCV_HDR_OVF_21,
1225 C_RCV_HDR_OVF_22,
1226 C_RCV_HDR_OVF_23,
1227 C_RCV_HDR_OVF_24,
1228 C_RCV_HDR_OVF_25,
1229 C_RCV_HDR_OVF_26,
1230 C_RCV_HDR_OVF_27,
1231 C_RCV_HDR_OVF_28,
1232 C_RCV_HDR_OVF_29,
1233 C_RCV_HDR_OVF_30,
1234 C_RCV_HDR_OVF_31,
1235 C_RCV_HDR_OVF_32,
1236 C_RCV_HDR_OVF_33,
1237 C_RCV_HDR_OVF_34,
1238 C_RCV_HDR_OVF_35,
1239 C_RCV_HDR_OVF_36,
1240 C_RCV_HDR_OVF_37,
1241 C_RCV_HDR_OVF_38,
1242 C_RCV_HDR_OVF_39,
1243 C_RCV_HDR_OVF_40,
1244 C_RCV_HDR_OVF_41,
1245 C_RCV_HDR_OVF_42,
1246 C_RCV_HDR_OVF_43,
1247 C_RCV_HDR_OVF_44,
1248 C_RCV_HDR_OVF_45,
1249 C_RCV_HDR_OVF_46,
1250 C_RCV_HDR_OVF_47,
1251 C_RCV_HDR_OVF_48,
1252 C_RCV_HDR_OVF_49,
1253 C_RCV_HDR_OVF_50,
1254 C_RCV_HDR_OVF_51,
1255 C_RCV_HDR_OVF_52,
1256 C_RCV_HDR_OVF_53,
1257 C_RCV_HDR_OVF_54,
1258 C_RCV_HDR_OVF_55,
1259 C_RCV_HDR_OVF_56,
1260 C_RCV_HDR_OVF_57,
1261 C_RCV_HDR_OVF_58,
1262 C_RCV_HDR_OVF_59,
1263 C_RCV_HDR_OVF_60,
1264 C_RCV_HDR_OVF_61,
1265 C_RCV_HDR_OVF_62,
1266 C_RCV_HDR_OVF_63,
1267 C_RCV_HDR_OVF_64,
1268 C_RCV_HDR_OVF_65,
1269 C_RCV_HDR_OVF_66,
1270 C_RCV_HDR_OVF_67,
1271 C_RCV_HDR_OVF_68,
1272 C_RCV_HDR_OVF_69,
1273 C_RCV_HDR_OVF_70,
1274 C_RCV_HDR_OVF_71,
1275 C_RCV_HDR_OVF_72,
1276 C_RCV_HDR_OVF_73,
1277 C_RCV_HDR_OVF_74,
1278 C_RCV_HDR_OVF_75,
1279 C_RCV_HDR_OVF_76,
1280 C_RCV_HDR_OVF_77,
1281 C_RCV_HDR_OVF_78,
1282 C_RCV_HDR_OVF_79,
1283 C_RCV_HDR_OVF_80,
1284 C_RCV_HDR_OVF_81,
1285 C_RCV_HDR_OVF_82,
1286 C_RCV_HDR_OVF_83,
1287 C_RCV_HDR_OVF_84,
1288 C_RCV_HDR_OVF_85,
1289 C_RCV_HDR_OVF_86,
1290 C_RCV_HDR_OVF_87,
1291 C_RCV_HDR_OVF_88,
1292 C_RCV_HDR_OVF_89,
1293 C_RCV_HDR_OVF_90,
1294 C_RCV_HDR_OVF_91,
1295 C_RCV_HDR_OVF_92,
1296 C_RCV_HDR_OVF_93,
1297 C_RCV_HDR_OVF_94,
1298 C_RCV_HDR_OVF_95,
1299 C_RCV_HDR_OVF_96,
1300 C_RCV_HDR_OVF_97,
1301 C_RCV_HDR_OVF_98,
1302 C_RCV_HDR_OVF_99,
1303 C_RCV_HDR_OVF_100,
1304 C_RCV_HDR_OVF_101,
1305 C_RCV_HDR_OVF_102,
1306 C_RCV_HDR_OVF_103,
1307 C_RCV_HDR_OVF_104,
1308 C_RCV_HDR_OVF_105,
1309 C_RCV_HDR_OVF_106,
1310 C_RCV_HDR_OVF_107,
1311 C_RCV_HDR_OVF_108,
1312 C_RCV_HDR_OVF_109,
1313 C_RCV_HDR_OVF_110,
1314 C_RCV_HDR_OVF_111,
1315 C_RCV_HDR_OVF_112,
1316 C_RCV_HDR_OVF_113,
1317 C_RCV_HDR_OVF_114,
1318 C_RCV_HDR_OVF_115,
1319 C_RCV_HDR_OVF_116,
1320 C_RCV_HDR_OVF_117,
1321 C_RCV_HDR_OVF_118,
1322 C_RCV_HDR_OVF_119,
1323 C_RCV_HDR_OVF_120,
1324 C_RCV_HDR_OVF_121,
1325 C_RCV_HDR_OVF_122,
1326 C_RCV_HDR_OVF_123,
1327 C_RCV_HDR_OVF_124,
1328 C_RCV_HDR_OVF_125,
1329 C_RCV_HDR_OVF_126,
1330 C_RCV_HDR_OVF_127,
1331 C_RCV_HDR_OVF_128,
1332 C_RCV_HDR_OVF_129,
1333 C_RCV_HDR_OVF_130,
1334 C_RCV_HDR_OVF_131,
1335 C_RCV_HDR_OVF_132,
1336 C_RCV_HDR_OVF_133,
1337 C_RCV_HDR_OVF_134,
1338 C_RCV_HDR_OVF_135,
1339 C_RCV_HDR_OVF_136,
1340 C_RCV_HDR_OVF_137,
1341 C_RCV_HDR_OVF_138,
1342 C_RCV_HDR_OVF_139,
1343 C_RCV_HDR_OVF_140,
1344 C_RCV_HDR_OVF_141,
1345 C_RCV_HDR_OVF_142,
1346 C_RCV_HDR_OVF_143,
1347 C_RCV_HDR_OVF_144,
1348 C_RCV_HDR_OVF_145,
1349 C_RCV_HDR_OVF_146,
1350 C_RCV_HDR_OVF_147,
1351 C_RCV_HDR_OVF_148,
1352 C_RCV_HDR_OVF_149,
1353 C_RCV_HDR_OVF_150,
1354 C_RCV_HDR_OVF_151,
1355 C_RCV_HDR_OVF_152,
1356 C_RCV_HDR_OVF_153,
1357 C_RCV_HDR_OVF_154,
1358 C_RCV_HDR_OVF_155,
1359 C_RCV_HDR_OVF_156,
1360 C_RCV_HDR_OVF_157,
1361 C_RCV_HDR_OVF_158,
1362 C_RCV_HDR_OVF_159,
1363 PORT_CNTR_LAST
1364};
1365
1366u64 get_all_cpu_total(u64 __percpu *cntr);
1367void hfi1_start_cleanup(struct hfi1_devdata *dd);
1368void hfi1_clear_tids(struct hfi1_ctxtdata *rcd);
1369void hfi1_init_ctxt(struct send_context *sc);
1370void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
1371 u32 type, unsigned long pa, u16 order);
1372void hfi1_quiet_serdes(struct hfi1_pportdata *ppd);
1373void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,
1374 struct hfi1_ctxtdata *rcd);
1375u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp);
1376u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp);
1377int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which);
1378int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val);
1379int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
1380 u16 jkey);
1381int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
1382int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt,
1383 u16 pkey);
1384int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
1385void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality);
1386void hfi1_init_vnic_rsm(struct hfi1_devdata *dd);
1387void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd);
1388
1389
1390
1391
1392
1393
1394
1395struct is_table {
1396 int start;
1397 int end;
1398
1399 char *(*is_name)(char *name, size_t size, unsigned int source);
1400
1401 void (*is_int)(struct hfi1_devdata *dd, unsigned int source);
1402};
1403
1404#endif
1405