linux/drivers/media/dvb-frontends/cx24110.c
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   1/*
   2    cx24110 - Single Chip Satellite Channel Receiver driver module
   3
   4    Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
   5    work
   6    Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23*/
  24
  25#include <linux/slab.h>
  26#include <linux/kernel.h>
  27#include <linux/module.h>
  28#include <linux/init.h>
  29
  30#include <media/dvb_frontend.h>
  31#include "cx24110.h"
  32
  33
  34struct cx24110_state {
  35
  36        struct i2c_adapter* i2c;
  37
  38        const struct cx24110_config* config;
  39
  40        struct dvb_frontend frontend;
  41
  42        u32 lastber;
  43        u32 lastbler;
  44        u32 lastesn0;
  45};
  46
  47static int debug;
  48#define dprintk(args...) \
  49        do { \
  50                if (debug) printk(KERN_DEBUG "cx24110: " args); \
  51        } while (0)
  52
  53static struct {u8 reg; u8 data;} cx24110_regdata[]=
  54                      /* Comments beginning with @ denote this value should
  55                         be the default */
  56        {{0x09,0x01}, /* SoftResetAll */
  57         {0x09,0x00}, /* release reset */
  58         {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
  59         {0x02,0x17}, /* middle byte " */
  60         {0x03,0x29}, /* LSB         " */
  61         {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
  62         {0x06,0xa5}, /* @ PLL 60MHz */
  63         {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
  64         {0x0a,0x00}, /* @ partial chip disables, do not set */
  65         {0x0b,0x01}, /* set output clock in gapped mode, start signal low
  66                         active for first byte */
  67         {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
  68         {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
  69         {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
  70                         to avoid starting the BER counter. Reset the
  71                         CRC test bit. Finite counting selected */
  72         {0x15,0xff}, /* @ size of the limited time window for RS BER
  73                         estimation. It is <value>*256 RS blocks, this
  74                         gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
  75         {0x16,0x00}, /* @ enable all RS output ports */
  76         {0x17,0x04}, /* @ time window allowed for the RS to sync */
  77         {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
  78                         for automatically */
  79                      /* leave the current code rate and normalization
  80                         registers as they are after reset... */
  81         {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
  82                         only once */
  83         {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
  84                         estimation. It is <value>*65536 channel bits, i.e.
  85                         approx. 38ms at 27.5MS/s, rate 3/4 */
  86         {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
  87                      /* leave front-end AGC parameters at default values */
  88                      /* leave decimation AGC parameters at default values */
  89         {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
  90         {0x36,0xff}, /* clear all interrupt pending flags */
  91         {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
  92         {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
  93                      /* leave the equalizer parameters on their default values */
  94                      /* leave the final AGC parameters on their default values */
  95         {0x41,0x00}, /* @ MSB of front-end derotator frequency */
  96         {0x42,0x00}, /* @ middle bytes " */
  97         {0x43,0x00}, /* @ LSB          " */
  98                      /* leave the carrier tracking loop parameters on default */
  99                      /* leave the bit timing loop parameters at default */
 100         {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
 101                      /* the cx24108 data sheet for symbol rates above 15MS/s */
 102         {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
 103         {0x61,0x95}, /* GPIO pins 1-4 have special function */
 104         {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
 105         {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
 106         {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
 107         {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
 108         {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
 109         {0x73,0x00}, /* @ disable several demod bypasses */
 110         {0x74,0x00}, /* @  " */
 111         {0x75,0x00}  /* @  " */
 112                      /* the remaining registers are for SEC */
 113        };
 114
 115
 116static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
 117{
 118        u8 buf [] = { reg, data };
 119        struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 120        int err;
 121
 122        if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 123                dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n",
 124                        __func__, err, reg, data);
 125                return -EREMOTEIO;
 126        }
 127
 128        return 0;
 129}
 130
 131static int cx24110_readreg (struct cx24110_state* state, u8 reg)
 132{
 133        int ret;
 134        u8 b0 [] = { reg };
 135        u8 b1 [] = { 0 };
 136        struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 137                           { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 138
 139        ret = i2c_transfer(state->i2c, msg, 2);
 140
 141        if (ret != 2) return ret;
 142
 143        return b1[0];
 144}
 145
 146static int cx24110_set_inversion(struct cx24110_state *state,
 147                                 enum fe_spectral_inversion inversion)
 148{
 149/* fixme (low): error handling */
 150
 151        switch (inversion) {
 152        case INVERSION_OFF:
 153                cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 154                /* AcqSpectrInvDis on. No idea why someone should want this */
 155                cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
 156                /* Initial value 0 at start of acq */
 157                cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
 158                /* current value 0 */
 159                /* The cx24110 manual tells us this reg is read-only.
 160                   But what the heck... set it ayways */
 161                break;
 162        case INVERSION_ON:
 163                cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 164                /* AcqSpectrInvDis on. No idea why someone should want this */
 165                cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
 166                /* Initial value 1 at start of acq */
 167                cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
 168                /* current value 1 */
 169                break;
 170        case INVERSION_AUTO:
 171                cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
 172                /* AcqSpectrInvDis off. Leave initial & current states as is */
 173                break;
 174        default:
 175                return -EINVAL;
 176        }
 177
 178        return 0;
 179}
 180
 181static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)
 182{
 183        static const int rate[FEC_AUTO] = {-1,    1,    2,    3,    5,    7, -1};
 184        static const int g1[FEC_AUTO]   = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};
 185        static const int g2[FEC_AUTO]   = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};
 186
 187        /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
 188           searches all enabled viterbi rates, and can handle non-standard
 189           rates as well. */
 190
 191        if (fec > FEC_AUTO)
 192                fec = FEC_AUTO;
 193
 194        if (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
 195                cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);
 196                /* clear AcqVitDis bit */
 197                cx24110_writereg(state, 0x18, 0xae);
 198                /* allow all DVB standard code rates */
 199                cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);
 200                /* set nominal Viterbi rate 3/4 */
 201                cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);
 202                /* set current Viterbi rate 3/4 */
 203                cx24110_writereg(state, 0x1a, 0x05);
 204                cx24110_writereg(state, 0x1b, 0x06);
 205                /* set the puncture registers for code rate 3/4 */
 206                return 0;
 207        } else {
 208                cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);
 209                /* set AcqVitDis bit */
 210                if (rate[fec] < 0)
 211                        return -EINVAL;
 212
 213                cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);
 214                /* set nominal Viterbi rate */
 215                cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);
 216                /* set current Viterbi rate */
 217                cx24110_writereg(state, 0x1a, g1[fec]);
 218                cx24110_writereg(state, 0x1b, g2[fec]);
 219                /* not sure if this is the right way: I always used AutoAcq mode */
 220        }
 221        return 0;
 222}
 223
 224static enum fe_code_rate cx24110_get_fec(struct cx24110_state *state)
 225{
 226        int i;
 227
 228        i=cx24110_readreg(state,0x22)&0x0f;
 229        if(!(i&0x08)) {
 230                return FEC_1_2 + i - 1;
 231        } else {
 232/* fixme (low): a special code rate has been selected. In theory, we need to
 233   return a denominator value, a numerator value, and a pair of puncture
 234   maps to correctly describe this mode. But this should never happen in
 235   practice, because it cannot be set by cx24110_get_fec. */
 236           return FEC_NONE;
 237        }
 238}
 239
 240static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
 241{
 242/* fixme (low): add error handling */
 243        u32 ratio;
 244        u32 tmp, fclk, BDRI;
 245
 246        static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
 247        int i;
 248
 249        dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
 250        if (srate>90999000UL/2)
 251                srate=90999000UL/2;
 252        if (srate<500000)
 253                srate=500000;
 254
 255        for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
 256                ;
 257        /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
 258           and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
 259           R06[3:0] PLLphaseDetGain */
 260        tmp=cx24110_readreg(state,0x07)&0xfc;
 261        if(srate<90999000UL/4) { /* sample rate 45MHz*/
 262                cx24110_writereg(state,0x07,tmp);
 263                cx24110_writereg(state,0x06,0x78);
 264                fclk=90999000UL/2;
 265        } else if(srate<60666000UL/2) { /* sample rate 60MHz */
 266                cx24110_writereg(state,0x07,tmp|0x1);
 267                cx24110_writereg(state,0x06,0xa5);
 268                fclk=60666000UL;
 269        } else if(srate<80888000UL/2) { /* sample rate 80MHz */
 270                cx24110_writereg(state,0x07,tmp|0x2);
 271                cx24110_writereg(state,0x06,0x87);
 272                fclk=80888000UL;
 273        } else { /* sample rate 90MHz */
 274                cx24110_writereg(state,0x07,tmp|0x3);
 275                cx24110_writereg(state,0x06,0x78);
 276                fclk=90999000UL;
 277        }
 278        dprintk("cx24110 debug: fclk %d Hz\n",fclk);
 279        /* we need to divide two integers with approx. 27 bits in 32 bit
 280           arithmetic giving a 25 bit result */
 281        /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
 282           also the most complex divisor. Hence, the dividend has,
 283           assuming 32bit unsigned arithmetic, 6 clear bits on top, the
 284           divisor 2 unused bits at the bottom. Also, the quotient is
 285           always less than 1/2. Borrowed from VES1893.c, of course */
 286
 287        tmp=srate<<6;
 288        BDRI=fclk>>2;
 289        ratio=(tmp/BDRI);
 290
 291        tmp=(tmp%BDRI)<<8;
 292        ratio=(ratio<<8)+(tmp/BDRI);
 293
 294        tmp=(tmp%BDRI)<<8;
 295        ratio=(ratio<<8)+(tmp/BDRI);
 296
 297        tmp=(tmp%BDRI)<<1;
 298        ratio=(ratio<<1)+(tmp/BDRI);
 299
 300        dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
 301        dprintk("fclk = %d\n", fclk);
 302        dprintk("ratio= %08x\n", ratio);
 303
 304        cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
 305        cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
 306        cx24110_writereg(state, 0x3, (ratio)&0xff);
 307
 308        return 0;
 309
 310}
 311
 312static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
 313{
 314        struct cx24110_state *state = fe->demodulator_priv;
 315
 316        if (len != 3)
 317                return -EINVAL;
 318
 319/* tuner data is 21 bits long, must be left-aligned in data */
 320/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
 321/* FIXME (low): add error handling, avoid infinite loops if HW fails... */
 322
 323        cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
 324        cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
 325
 326        /* if the auto tuner writer is still busy, clear it out */
 327        while (cx24110_readreg(state,0x6d)&0x80)
 328                cx24110_writereg(state,0x72,0);
 329
 330        /* write the topmost 8 bits */
 331        cx24110_writereg(state,0x72,buf[0]);
 332
 333        /* wait for the send to be completed */
 334        while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 335                ;
 336
 337        /* send another 8 bytes */
 338        cx24110_writereg(state,0x72,buf[1]);
 339        while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 340                ;
 341
 342        /* and the topmost 5 bits of this byte */
 343        cx24110_writereg(state,0x72,buf[2]);
 344        while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 345                ;
 346
 347        /* now strobe the enable line once */
 348        cx24110_writereg(state,0x6d,0x32);
 349        cx24110_writereg(state,0x6d,0x30);
 350
 351        return 0;
 352}
 353
 354static int cx24110_initfe(struct dvb_frontend* fe)
 355{
 356        struct cx24110_state *state = fe->demodulator_priv;
 357/* fixme (low): error handling */
 358        int i;
 359
 360        dprintk("%s: init chip\n", __func__);
 361
 362        for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
 363                cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
 364        }
 365
 366        return 0;
 367}
 368
 369static int cx24110_set_voltage(struct dvb_frontend *fe,
 370                               enum fe_sec_voltage voltage)
 371{
 372        struct cx24110_state *state = fe->demodulator_priv;
 373
 374        switch (voltage) {
 375        case SEC_VOLTAGE_13:
 376                return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
 377        case SEC_VOLTAGE_18:
 378                return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
 379        default:
 380                return -EINVAL;
 381        }
 382}
 383
 384static int cx24110_diseqc_send_burst(struct dvb_frontend *fe,
 385                                     enum fe_sec_mini_cmd burst)
 386{
 387        int rv, bit;
 388        struct cx24110_state *state = fe->demodulator_priv;
 389        unsigned long timeout;
 390
 391        if (burst == SEC_MINI_A)
 392                bit = 0x00;
 393        else if (burst == SEC_MINI_B)
 394                bit = 0x08;
 395        else
 396                return -EINVAL;
 397
 398        rv = cx24110_readreg(state, 0x77);
 399        if (!(rv & 0x04))
 400                cx24110_writereg(state, 0x77, rv | 0x04);
 401
 402        rv = cx24110_readreg(state, 0x76);
 403        cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
 404        timeout = jiffies + msecs_to_jiffies(100);
 405        while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 406                ; /* wait for LNB ready */
 407
 408        return 0;
 409}
 410
 411static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
 412                                   struct dvb_diseqc_master_cmd *cmd)
 413{
 414        int i, rv;
 415        struct cx24110_state *state = fe->demodulator_priv;
 416        unsigned long timeout;
 417
 418        if (cmd->msg_len < 3 || cmd->msg_len > 6)
 419                return -EINVAL;  /* not implemented */
 420
 421        for (i = 0; i < cmd->msg_len; i++)
 422                cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
 423
 424        rv = cx24110_readreg(state, 0x77);
 425        if (rv & 0x04) {
 426                cx24110_writereg(state, 0x77, rv & ~0x04);
 427                msleep(30); /* reportedly fixes switching problems */
 428        }
 429
 430        rv = cx24110_readreg(state, 0x76);
 431
 432        cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
 433        timeout = jiffies + msecs_to_jiffies(100);
 434        while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 435                ; /* wait for LNB ready */
 436
 437        return 0;
 438}
 439
 440static int cx24110_read_status(struct dvb_frontend *fe,
 441                               enum fe_status *status)
 442{
 443        struct cx24110_state *state = fe->demodulator_priv;
 444
 445        int sync = cx24110_readreg (state, 0x55);
 446
 447        *status = 0;
 448
 449        if (sync & 0x10)
 450                *status |= FE_HAS_SIGNAL;
 451
 452        if (sync & 0x08)
 453                *status |= FE_HAS_CARRIER;
 454
 455        sync = cx24110_readreg (state, 0x08);
 456
 457        if (sync & 0x40)
 458                *status |= FE_HAS_VITERBI;
 459
 460        if (sync & 0x20)
 461                *status |= FE_HAS_SYNC;
 462
 463        if ((sync & 0x60) == 0x60)
 464                *status |= FE_HAS_LOCK;
 465
 466        return 0;
 467}
 468
 469static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
 470{
 471        struct cx24110_state *state = fe->demodulator_priv;
 472
 473        /* fixme (maybe): value range is 16 bit. Scale? */
 474        if(cx24110_readreg(state,0x24)&0x10) {
 475                /* the Viterbi error counter has finished one counting window */
 476                cx24110_writereg(state,0x24,0x04); /* select the ber reg */
 477                state->lastber=cx24110_readreg(state,0x25)|
 478                        (cx24110_readreg(state,0x26)<<8);
 479                cx24110_writereg(state,0x24,0x04); /* start new count window */
 480                cx24110_writereg(state,0x24,0x14);
 481        }
 482        *ber = state->lastber;
 483
 484        return 0;
 485}
 486
 487static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 488{
 489        struct cx24110_state *state = fe->demodulator_priv;
 490
 491/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
 492        u8 signal = cx24110_readreg (state, 0x27)+128;
 493        *signal_strength = (signal << 8) | signal;
 494
 495        return 0;
 496}
 497
 498static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
 499{
 500        struct cx24110_state *state = fe->demodulator_priv;
 501
 502        /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
 503        if(cx24110_readreg(state,0x6a)&0x80) {
 504                /* the Es/N0 error counter has finished one counting window */
 505                state->lastesn0=cx24110_readreg(state,0x69)|
 506                        (cx24110_readreg(state,0x68)<<8);
 507                cx24110_writereg(state,0x6a,0x84); /* start new count window */
 508        }
 509        *snr = state->lastesn0;
 510
 511        return 0;
 512}
 513
 514static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 515{
 516        struct cx24110_state *state = fe->demodulator_priv;
 517
 518        if(cx24110_readreg(state,0x10)&0x40) {
 519                /* the RS error counter has finished one counting window */
 520                cx24110_writereg(state,0x10,0x60); /* select the byer reg */
 521                (void)(cx24110_readreg(state, 0x12) |
 522                        (cx24110_readreg(state, 0x13) << 8) |
 523                        (cx24110_readreg(state, 0x14) << 16));
 524                cx24110_writereg(state,0x10,0x70); /* select the bler reg */
 525                state->lastbler=cx24110_readreg(state,0x12)|
 526                        (cx24110_readreg(state,0x13)<<8)|
 527                        (cx24110_readreg(state,0x14)<<16);
 528                cx24110_writereg(state,0x10,0x20); /* start new count window */
 529        }
 530        *ucblocks = state->lastbler;
 531
 532        return 0;
 533}
 534
 535static int cx24110_set_frontend(struct dvb_frontend *fe)
 536{
 537        struct cx24110_state *state = fe->demodulator_priv;
 538        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 539
 540        if (fe->ops.tuner_ops.set_params) {
 541                fe->ops.tuner_ops.set_params(fe);
 542                if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 543        }
 544
 545        cx24110_set_inversion(state, p->inversion);
 546        cx24110_set_fec(state, p->fec_inner);
 547        cx24110_set_symbolrate(state, p->symbol_rate);
 548        cx24110_writereg(state,0x04,0x05); /* start acquisition */
 549
 550        return 0;
 551}
 552
 553static int cx24110_get_frontend(struct dvb_frontend *fe,
 554                                struct dtv_frontend_properties *p)
 555{
 556        struct cx24110_state *state = fe->demodulator_priv;
 557        s32 afc; unsigned sclk;
 558
 559/* cannot read back tuner settings (freq). Need to have some private storage */
 560
 561        sclk = cx24110_readreg (state, 0x07) & 0x03;
 562/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
 563 * Need 64 bit arithmetic. Is thiss possible in the kernel? */
 564        if (sclk==0) sclk=90999000L/2L;
 565        else if (sclk==1) sclk=60666000L;
 566        else if (sclk==2) sclk=80888000L;
 567        else sclk=90999000L;
 568        sclk>>=8;
 569        afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
 570              ((sclk*cx24110_readreg (state, 0x45))>>8)+
 571              ((sclk*cx24110_readreg (state, 0x46))>>16);
 572
 573        p->frequency += afc;
 574        p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
 575                                INVERSION_ON : INVERSION_OFF;
 576        p->fec_inner = cx24110_get_fec(state);
 577
 578        return 0;
 579}
 580
 581static int cx24110_set_tone(struct dvb_frontend *fe,
 582                            enum fe_sec_tone_mode tone)
 583{
 584        struct cx24110_state *state = fe->demodulator_priv;
 585
 586        return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
 587}
 588
 589static void cx24110_release(struct dvb_frontend* fe)
 590{
 591        struct cx24110_state* state = fe->demodulator_priv;
 592        kfree(state);
 593}
 594
 595static const struct dvb_frontend_ops cx24110_ops;
 596
 597struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
 598                                    struct i2c_adapter* i2c)
 599{
 600        struct cx24110_state* state = NULL;
 601        int ret;
 602
 603        /* allocate memory for the internal state */
 604        state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
 605        if (state == NULL) goto error;
 606
 607        /* setup the state */
 608        state->config = config;
 609        state->i2c = i2c;
 610        state->lastber = 0;
 611        state->lastbler = 0;
 612        state->lastesn0 = 0;
 613
 614        /* check if the demod is there */
 615        ret = cx24110_readreg(state, 0x00);
 616        if ((ret != 0x5a) && (ret != 0x69)) goto error;
 617
 618        /* create dvb_frontend */
 619        memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
 620        state->frontend.demodulator_priv = state;
 621        return &state->frontend;
 622
 623error:
 624        kfree(state);
 625        return NULL;
 626}
 627
 628static const struct dvb_frontend_ops cx24110_ops = {
 629        .delsys = { SYS_DVBS },
 630        .info = {
 631                .name = "Conexant CX24110 DVB-S",
 632                .frequency_min = 950000,
 633                .frequency_max = 2150000,
 634                .frequency_stepsize = 1011,  /* kHz for QPSK frontends */
 635                .frequency_tolerance = 29500,
 636                .symbol_rate_min = 1000000,
 637                .symbol_rate_max = 45000000,
 638                .caps = FE_CAN_INVERSION_AUTO |
 639                        FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 640                        FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 641                        FE_CAN_QPSK | FE_CAN_RECOVER
 642        },
 643
 644        .release = cx24110_release,
 645
 646        .init = cx24110_initfe,
 647        .write = _cx24110_pll_write,
 648        .set_frontend = cx24110_set_frontend,
 649        .get_frontend = cx24110_get_frontend,
 650        .read_status = cx24110_read_status,
 651        .read_ber = cx24110_read_ber,
 652        .read_signal_strength = cx24110_read_signal_strength,
 653        .read_snr = cx24110_read_snr,
 654        .read_ucblocks = cx24110_read_ucblocks,
 655
 656        .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
 657        .set_tone = cx24110_set_tone,
 658        .set_voltage = cx24110_set_voltage,
 659        .diseqc_send_burst = cx24110_diseqc_send_burst,
 660};
 661
 662module_param(debug, int, 0644);
 663MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 664
 665MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
 666MODULE_AUTHOR("Peter Hettkamp");
 667MODULE_LICENSE("GPL");
 668
 669EXPORT_SYMBOL(cx24110_attach);
 670