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21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24
25#include "gpmi-nand.h"
26#include "gpmi-regs.h"
27#include "bch-regs.h"
28
29
30#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
31
32#define MXS_SET_ADDR 0x4
33#define MXS_CLR_ADDR 0x8
34
35
36
37
38
39static int clear_poll_bit(void __iomem *addr, u32 mask)
40{
41 int timeout = 0x400;
42
43
44 writel(mask, addr + MXS_CLR_ADDR);
45
46
47
48
49
50 udelay(1);
51
52
53 while ((readl(addr) & mask) && --timeout)
54 ;
55
56 return !timeout;
57}
58
59#define MODULE_CLKGATE (1 << 30)
60#define MODULE_SFTRST (1 << 31)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
79{
80 int ret;
81 int timeout = 0x400;
82
83
84 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
85 if (unlikely(ret))
86 goto error;
87
88
89 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
90
91 if (!just_enable) {
92
93 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
94 udelay(1);
95
96
97 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
98 ;
99 if (unlikely(!timeout))
100 goto error;
101 }
102
103
104 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
105 if (unlikely(ret))
106 goto error;
107
108
109 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
110 if (unlikely(ret))
111 goto error;
112
113 return 0;
114
115error:
116 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
117 return -ETIMEDOUT;
118}
119
120static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
121{
122 struct clk *clk;
123 int ret;
124 int i;
125
126 for (i = 0; i < GPMI_CLK_MAX; i++) {
127 clk = this->resources.clock[i];
128 if (!clk)
129 break;
130
131 if (v) {
132 ret = clk_prepare_enable(clk);
133 if (ret)
134 goto err_clk;
135 } else {
136 clk_disable_unprepare(clk);
137 }
138 }
139 return 0;
140
141err_clk:
142 for (; i > 0; i--)
143 clk_disable_unprepare(this->resources.clock[i - 1]);
144 return ret;
145}
146
147int gpmi_enable_clk(struct gpmi_nand_data *this)
148{
149 return __gpmi_enable_clk(this, true);
150}
151
152int gpmi_disable_clk(struct gpmi_nand_data *this)
153{
154 return __gpmi_enable_clk(this, false);
155}
156
157int gpmi_init(struct gpmi_nand_data *this)
158{
159 struct resources *r = &this->resources;
160 int ret;
161
162 ret = gpmi_enable_clk(this);
163 if (ret)
164 return ret;
165 ret = gpmi_reset_block(r->gpmi_regs, false);
166 if (ret)
167 goto err_out;
168
169
170
171
172
173 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
174 if (ret)
175 goto err_out;
176
177
178 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
179
180
181 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
182 r->gpmi_regs + HW_GPMI_CTRL1_SET);
183
184
185 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
186
187
188 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
189
190
191
192
193
194 writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
195
196 gpmi_disable_clk(this);
197 return 0;
198err_out:
199 gpmi_disable_clk(this);
200 return ret;
201}
202
203
204void gpmi_dump_info(struct gpmi_nand_data *this)
205{
206 struct resources *r = &this->resources;
207 struct bch_geometry *geo = &this->bch_geometry;
208 u32 reg;
209 int i;
210
211 dev_err(this->dev, "Show GPMI registers :\n");
212 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
213 reg = readl(r->gpmi_regs + i * 0x10);
214 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
215 }
216
217
218 dev_err(this->dev, "Show BCH registers :\n");
219 for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
220 reg = readl(r->bch_regs + i * 0x10);
221 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
222 }
223 dev_err(this->dev, "BCH Geometry :\n"
224 "GF length : %u\n"
225 "ECC Strength : %u\n"
226 "Page Size in Bytes : %u\n"
227 "Metadata Size in Bytes : %u\n"
228 "ECC Chunk Size in Bytes: %u\n"
229 "ECC Chunk Count : %u\n"
230 "Payload Size in Bytes : %u\n"
231 "Auxiliary Size in Bytes: %u\n"
232 "Auxiliary Status Offset: %u\n"
233 "Block Mark Byte Offset : %u\n"
234 "Block Mark Bit Offset : %u\n",
235 geo->gf_len,
236 geo->ecc_strength,
237 geo->page_size,
238 geo->metadata_size,
239 geo->ecc_chunk_size,
240 geo->ecc_chunk_count,
241 geo->payload_size,
242 geo->auxiliary_size,
243 geo->auxiliary_status_offset,
244 geo->block_mark_byte_offset,
245 geo->block_mark_bit_offset);
246}
247
248
249int bch_set_geometry(struct gpmi_nand_data *this)
250{
251 struct resources *r = &this->resources;
252 struct bch_geometry *bch_geo = &this->bch_geometry;
253 unsigned int block_count;
254 unsigned int block_size;
255 unsigned int metadata_size;
256 unsigned int ecc_strength;
257 unsigned int page_size;
258 unsigned int gf_len;
259 int ret;
260
261 ret = common_nfc_set_geometry(this);
262 if (ret)
263 return ret;
264
265 block_count = bch_geo->ecc_chunk_count - 1;
266 block_size = bch_geo->ecc_chunk_size;
267 metadata_size = bch_geo->metadata_size;
268 ecc_strength = bch_geo->ecc_strength >> 1;
269 page_size = bch_geo->page_size;
270 gf_len = bch_geo->gf_len;
271
272 ret = gpmi_enable_clk(this);
273 if (ret)
274 return ret;
275
276
277
278
279
280
281
282
283
284 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
285 if (ret)
286 goto err_out;
287
288
289 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
290 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
291 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
292 | BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
293 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
294 r->bch_regs + HW_BCH_FLASH0LAYOUT0);
295
296 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
297 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
298 | BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
299 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
300 r->bch_regs + HW_BCH_FLASH0LAYOUT1);
301
302
303 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
304
305
306 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
307 r->bch_regs + HW_BCH_CTRL_SET);
308
309 gpmi_disable_clk(this);
310 return 0;
311err_out:
312 gpmi_disable_clk(this);
313 return ret;
314}
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390static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
391 const struct nand_sdr_timings *sdr)
392{
393 struct gpmi_nfc_hardware_timing *hw = &this->hw;
394 unsigned int dll_threshold_ps = this->devdata->max_chain_delay;
395 unsigned int period_ps, reference_period_ps;
396 unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
397 unsigned int tRP_ps;
398 bool use_half_period;
399 int sample_delay_ps, sample_delay_factor;
400 u16 busy_timeout_cycles;
401 u8 wrn_dly_sel;
402
403 if (sdr->tRC_min >= 30000) {
404
405 hw->clk_rate = 22000000;
406 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
407 } else if (sdr->tRC_min >= 25000) {
408
409 hw->clk_rate = 80000000;
410 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
411 } else {
412
413 hw->clk_rate = 100000000;
414 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
415 }
416
417
418 period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
419
420 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
421 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
422 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
423 busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
424
425 hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
426 BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
427 BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles);
428 hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096);
429
430
431
432
433
434
435
436
437 if (period_ps > dll_threshold_ps) {
438 use_half_period = true;
439 reference_period_ps = period_ps / 2;
440 } else {
441 use_half_period = false;
442 reference_period_ps = period_ps;
443 }
444
445 tRP_ps = data_setup_cycles * period_ps;
446 sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8;
447 if (sample_delay_ps > 0)
448 sample_delay_factor = sample_delay_ps / reference_period_ps;
449 else
450 sample_delay_factor = 0;
451
452 hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel);
453 if (sample_delay_factor)
454 hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) |
455 BM_GPMI_CTRL1_DLL_ENABLE |
456 (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
457}
458
459void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
460{
461 struct gpmi_nfc_hardware_timing *hw = &this->hw;
462 struct resources *r = &this->resources;
463 void __iomem *gpmi_regs = r->gpmi_regs;
464 unsigned int dll_wait_time_us;
465
466 clk_set_rate(r->clock[0], hw->clk_rate);
467
468 writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
469 writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
470
471
472
473
474
475 writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR);
476 writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
477
478
479 dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64;
480 if (!dll_wait_time_us)
481 dll_wait_time_us = 1;
482
483
484 udelay(dll_wait_time_us);
485}
486
487int gpmi_setup_data_interface(struct mtd_info *mtd, int chipnr,
488 const struct nand_data_interface *conf)
489{
490 struct nand_chip *chip = mtd_to_nand(mtd);
491 struct gpmi_nand_data *this = nand_get_controller_data(chip);
492 const struct nand_sdr_timings *sdr;
493
494
495 sdr = nand_get_sdr_timings(conf);
496 if (IS_ERR(sdr))
497 return PTR_ERR(sdr);
498
499
500 if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this))
501 return -ENOTSUPP;
502
503
504 if (chipnr < 0)
505 return 0;
506
507
508 gpmi_nfc_compute_timings(this, sdr);
509
510 this->hw.must_apply_timings = true;
511
512 return 0;
513}
514
515
516void gpmi_clear_bch(struct gpmi_nand_data *this)
517{
518 struct resources *r = &this->resources;
519 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
520}
521
522
523int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
524{
525 struct resources *r = &this->resources;
526 uint32_t mask = 0;
527 uint32_t reg = 0;
528
529 if (GPMI_IS_MX23(this)) {
530 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
531 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
532 } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) {
533
534
535
536
537 if (GPMI_IS_MX6(this))
538 chip = 0;
539
540
541 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
542 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
543 } else
544 dev_err(this->dev, "unknown arch.\n");
545 return reg & mask;
546}
547
548int gpmi_send_command(struct gpmi_nand_data *this)
549{
550 struct dma_chan *channel = get_dma_chan(this);
551 struct dma_async_tx_descriptor *desc;
552 struct scatterlist *sgl;
553 int chip = this->current_chip;
554 int ret;
555 u32 pio[3];
556
557
558 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
559 | BM_GPMI_CTRL0_WORD_LENGTH
560 | BF_GPMI_CTRL0_CS(chip, this)
561 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
562 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
563 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
564 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
565 pio[1] = pio[2] = 0;
566 desc = dmaengine_prep_slave_sg(channel,
567 (struct scatterlist *)pio,
568 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
569 if (!desc)
570 return -EINVAL;
571
572
573 sgl = &this->cmd_sgl;
574
575 sg_init_one(sgl, this->cmd_buffer, this->command_length);
576 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
577 desc = dmaengine_prep_slave_sg(channel,
578 sgl, 1, DMA_MEM_TO_DEV,
579 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
580 if (!desc)
581 return -EINVAL;
582
583
584 ret = start_dma_without_bch_irq(this, desc);
585
586 dma_unmap_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
587
588 return ret;
589}
590
591int gpmi_send_data(struct gpmi_nand_data *this, const void *buf, int len)
592{
593 struct dma_async_tx_descriptor *desc;
594 struct dma_chan *channel = get_dma_chan(this);
595 int chip = this->current_chip;
596 int ret;
597 uint32_t command_mode;
598 uint32_t address;
599 u32 pio[2];
600
601
602 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
603 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
604
605 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
606 | BM_GPMI_CTRL0_WORD_LENGTH
607 | BF_GPMI_CTRL0_CS(chip, this)
608 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
609 | BF_GPMI_CTRL0_ADDRESS(address)
610 | BF_GPMI_CTRL0_XFER_COUNT(len);
611 pio[1] = 0;
612 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
613 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
614 if (!desc)
615 return -EINVAL;
616
617
618 prepare_data_dma(this, buf, len, DMA_TO_DEVICE);
619 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
620 1, DMA_MEM_TO_DEV,
621 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
622 if (!desc)
623 return -EINVAL;
624
625
626 ret = start_dma_without_bch_irq(this, desc);
627
628 dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_TO_DEVICE);
629
630 return ret;
631}
632
633int gpmi_read_data(struct gpmi_nand_data *this, void *buf, int len)
634{
635 struct dma_async_tx_descriptor *desc;
636 struct dma_chan *channel = get_dma_chan(this);
637 int chip = this->current_chip;
638 int ret;
639 u32 pio[2];
640 bool direct;
641
642
643 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
644 | BM_GPMI_CTRL0_WORD_LENGTH
645 | BF_GPMI_CTRL0_CS(chip, this)
646 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
647 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
648 | BF_GPMI_CTRL0_XFER_COUNT(len);
649 pio[1] = 0;
650 desc = dmaengine_prep_slave_sg(channel,
651 (struct scatterlist *)pio,
652 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
653 if (!desc)
654 return -EINVAL;
655
656
657 direct = prepare_data_dma(this, buf, len, DMA_FROM_DEVICE);
658 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
659 1, DMA_DEV_TO_MEM,
660 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
661 if (!desc)
662 return -EINVAL;
663
664
665
666 ret = start_dma_without_bch_irq(this, desc);
667
668 dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_FROM_DEVICE);
669 if (!direct)
670 memcpy(buf, this->data_buffer_dma, len);
671
672 return ret;
673}
674
675int gpmi_send_page(struct gpmi_nand_data *this,
676 dma_addr_t payload, dma_addr_t auxiliary)
677{
678 struct bch_geometry *geo = &this->bch_geometry;
679 uint32_t command_mode;
680 uint32_t address;
681 uint32_t ecc_command;
682 uint32_t buffer_mask;
683 struct dma_async_tx_descriptor *desc;
684 struct dma_chan *channel = get_dma_chan(this);
685 int chip = this->current_chip;
686 u32 pio[6];
687
688
689 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
690 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
691 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
692 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
693 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
694
695 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
696 | BM_GPMI_CTRL0_WORD_LENGTH
697 | BF_GPMI_CTRL0_CS(chip, this)
698 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
699 | BF_GPMI_CTRL0_ADDRESS(address)
700 | BF_GPMI_CTRL0_XFER_COUNT(0);
701 pio[1] = 0;
702 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
703 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
704 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
705 pio[3] = geo->page_size;
706 pio[4] = payload;
707 pio[5] = auxiliary;
708
709 desc = dmaengine_prep_slave_sg(channel,
710 (struct scatterlist *)pio,
711 ARRAY_SIZE(pio), DMA_TRANS_NONE,
712 DMA_CTRL_ACK);
713 if (!desc)
714 return -EINVAL;
715
716 return start_dma_with_bch_irq(this, desc);
717}
718
719int gpmi_read_page(struct gpmi_nand_data *this,
720 dma_addr_t payload, dma_addr_t auxiliary)
721{
722 struct bch_geometry *geo = &this->bch_geometry;
723 uint32_t command_mode;
724 uint32_t address;
725 uint32_t ecc_command;
726 uint32_t buffer_mask;
727 struct dma_async_tx_descriptor *desc;
728 struct dma_chan *channel = get_dma_chan(this);
729 int chip = this->current_chip;
730 u32 pio[6];
731
732
733 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
734 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
735
736 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
737 | BM_GPMI_CTRL0_WORD_LENGTH
738 | BF_GPMI_CTRL0_CS(chip, this)
739 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
740 | BF_GPMI_CTRL0_ADDRESS(address)
741 | BF_GPMI_CTRL0_XFER_COUNT(0);
742 pio[1] = 0;
743 desc = dmaengine_prep_slave_sg(channel,
744 (struct scatterlist *)pio, 2,
745 DMA_TRANS_NONE, 0);
746 if (!desc)
747 return -EINVAL;
748
749
750 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
751 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
752 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
753 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
754 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
755
756 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
757 | BM_GPMI_CTRL0_WORD_LENGTH
758 | BF_GPMI_CTRL0_CS(chip, this)
759 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
760 | BF_GPMI_CTRL0_ADDRESS(address)
761 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
762
763 pio[1] = 0;
764 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
765 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
766 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
767 pio[3] = geo->page_size;
768 pio[4] = payload;
769 pio[5] = auxiliary;
770 desc = dmaengine_prep_slave_sg(channel,
771 (struct scatterlist *)pio,
772 ARRAY_SIZE(pio), DMA_TRANS_NONE,
773 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
774 if (!desc)
775 return -EINVAL;
776
777
778 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
779 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
780
781 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
782 | BM_GPMI_CTRL0_WORD_LENGTH
783 | BF_GPMI_CTRL0_CS(chip, this)
784 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
785 | BF_GPMI_CTRL0_ADDRESS(address)
786 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
787 pio[1] = 0;
788 pio[2] = 0;
789 desc = dmaengine_prep_slave_sg(channel,
790 (struct scatterlist *)pio, 3,
791 DMA_TRANS_NONE,
792 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
793 if (!desc)
794 return -EINVAL;
795
796
797 return start_dma_with_bch_irq(this, desc);
798}
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
816 const u8 *src, size_t src_bit_off,
817 size_t nbits)
818{
819 size_t i;
820 size_t nbytes;
821 u32 src_buffer = 0;
822 size_t bits_in_src_buffer = 0;
823
824 if (!nbits)
825 return;
826
827
828
829
830
831 src += src_bit_off / 8;
832 src_bit_off %= 8;
833
834 dst += dst_bit_off / 8;
835 dst_bit_off %= 8;
836
837
838
839
840
841 if (src_bit_off) {
842 src_buffer = src[0] >> src_bit_off;
843 if (nbits >= (8 - src_bit_off)) {
844 bits_in_src_buffer += 8 - src_bit_off;
845 } else {
846 src_buffer &= GENMASK(nbits - 1, 0);
847 bits_in_src_buffer += nbits;
848 }
849 nbits -= bits_in_src_buffer;
850 src++;
851 }
852
853
854 nbytes = nbits / 8;
855
856
857 if (dst_bit_off) {
858 if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) {
859 src_buffer |= src[0] << bits_in_src_buffer;
860 bits_in_src_buffer += 8;
861 src++;
862 nbytes--;
863 }
864
865 if (bits_in_src_buffer >= (8 - dst_bit_off)) {
866 dst[0] &= GENMASK(dst_bit_off - 1, 0);
867 dst[0] |= src_buffer << dst_bit_off;
868 src_buffer >>= (8 - dst_bit_off);
869 bits_in_src_buffer -= (8 - dst_bit_off);
870 dst_bit_off = 0;
871 dst++;
872 if (bits_in_src_buffer > 7) {
873 bits_in_src_buffer -= 8;
874 dst[0] = src_buffer;
875 dst++;
876 src_buffer >>= 8;
877 }
878 }
879 }
880
881 if (!bits_in_src_buffer && !dst_bit_off) {
882
883
884
885
886 if (nbytes)
887 memcpy(dst, src, nbytes);
888 } else {
889
890
891
892
893
894 for (i = 0; i < nbytes; i++) {
895 src_buffer |= src[i] << bits_in_src_buffer;
896 dst[i] = src_buffer;
897 src_buffer >>= 8;
898 }
899 }
900
901 dst += nbytes;
902 src += nbytes;
903
904
905
906
907
908 nbits %= 8;
909
910
911
912
913
914 if (!nbits && !bits_in_src_buffer)
915 return;
916
917
918 if (nbits)
919 src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
920 bits_in_src_buffer;
921 bits_in_src_buffer += nbits;
922
923
924
925
926
927
928
929 if (dst_bit_off)
930 src_buffer = (src_buffer << dst_bit_off) |
931 (*dst & GENMASK(dst_bit_off - 1, 0));
932 bits_in_src_buffer += dst_bit_off;
933
934
935
936
937
938 nbytes = bits_in_src_buffer / 8;
939 if (bits_in_src_buffer % 8) {
940 src_buffer |= (dst[nbytes] &
941 GENMASK(7, bits_in_src_buffer % 8)) <<
942 (nbytes * 8);
943 nbytes++;
944 }
945
946
947 for (i = 0; i < nbytes; i++) {
948 dst[i] = src_buffer;
949 src_buffer >>= 8;
950 }
951}
952