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16#include <linux/ioport.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/rawnand.h>
24#include <linux/mtd/partitions.h>
25
26#include <linux/gpio.h>
27
28#include <asm/mach-jz4740/jz4740_nand.h>
29
30#define JZ_REG_NAND_CTRL 0x50
31#define JZ_REG_NAND_ECC_CTRL 0x100
32#define JZ_REG_NAND_DATA 0x104
33#define JZ_REG_NAND_PAR0 0x108
34#define JZ_REG_NAND_PAR1 0x10C
35#define JZ_REG_NAND_PAR2 0x110
36#define JZ_REG_NAND_IRQ_STAT 0x114
37#define JZ_REG_NAND_IRQ_CTRL 0x118
38#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
39
40#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
41#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
42#define JZ_NAND_ECC_CTRL_RS BIT(2)
43#define JZ_NAND_ECC_CTRL_RESET BIT(1)
44#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
45
46#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
47#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
48#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
49#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
50#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
51#define JZ_NAND_STATUS_ERROR BIT(0)
52
53#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
54#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
55#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
56
57#define JZ_NAND_MEM_CMD_OFFSET 0x08000
58#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
59
60struct jz_nand {
61 struct nand_chip chip;
62 void __iomem *base;
63 struct resource *mem;
64
65 unsigned char banks[JZ_NAND_NUM_BANKS];
66 void __iomem *bank_base[JZ_NAND_NUM_BANKS];
67 struct resource *bank_mem[JZ_NAND_NUM_BANKS];
68
69 int selected_bank;
70
71 struct gpio_desc *busy_gpio;
72 bool is_reading;
73};
74
75static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
76{
77 return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
78}
79
80static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
81{
82 struct jz_nand *nand = mtd_to_jz_nand(mtd);
83 struct nand_chip *chip = mtd_to_nand(mtd);
84 uint32_t ctrl;
85 int banknr;
86
87 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
88 ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
89
90 if (chipnr == -1) {
91 banknr = -1;
92 } else {
93 banknr = nand->banks[chipnr] - 1;
94 chip->IO_ADDR_R = nand->bank_base[banknr];
95 chip->IO_ADDR_W = nand->bank_base[banknr];
96 }
97 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
98
99 nand->selected_bank = banknr;
100}
101
102static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
103{
104 struct jz_nand *nand = mtd_to_jz_nand(mtd);
105 struct nand_chip *chip = mtd_to_nand(mtd);
106 uint32_t reg;
107 void __iomem *bank_base = nand->bank_base[nand->selected_bank];
108
109 BUG_ON(nand->selected_bank < 0);
110
111 if (ctrl & NAND_CTRL_CHANGE) {
112 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
113 if (ctrl & NAND_ALE)
114 bank_base += JZ_NAND_MEM_ADDR_OFFSET;
115 else if (ctrl & NAND_CLE)
116 bank_base += JZ_NAND_MEM_CMD_OFFSET;
117 chip->IO_ADDR_W = bank_base;
118
119 reg = readl(nand->base + JZ_REG_NAND_CTRL);
120 if (ctrl & NAND_NCE)
121 reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
122 else
123 reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
124 writel(reg, nand->base + JZ_REG_NAND_CTRL);
125 }
126 if (dat != NAND_CMD_NONE)
127 writeb(dat, chip->IO_ADDR_W);
128}
129
130static int jz_nand_dev_ready(struct mtd_info *mtd)
131{
132 struct jz_nand *nand = mtd_to_jz_nand(mtd);
133 return gpiod_get_value_cansleep(nand->busy_gpio);
134}
135
136static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
137{
138 struct jz_nand *nand = mtd_to_jz_nand(mtd);
139 uint32_t reg;
140
141 writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
142 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
143
144 reg |= JZ_NAND_ECC_CTRL_RESET;
145 reg |= JZ_NAND_ECC_CTRL_ENABLE;
146 reg |= JZ_NAND_ECC_CTRL_RS;
147
148 switch (mode) {
149 case NAND_ECC_READ:
150 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
151 nand->is_reading = true;
152 break;
153 case NAND_ECC_WRITE:
154 reg |= JZ_NAND_ECC_CTRL_ENCODING;
155 nand->is_reading = false;
156 break;
157 default:
158 break;
159 }
160
161 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
162}
163
164static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
165 uint8_t *ecc_code)
166{
167 struct jz_nand *nand = mtd_to_jz_nand(mtd);
168 uint32_t reg, status;
169 int i;
170 unsigned int timeout = 1000;
171 static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
172 0x8b, 0xff, 0xb7, 0x6f};
173
174 if (nand->is_reading)
175 return 0;
176
177 do {
178 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
179 } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
180
181 if (timeout == 0)
182 return -1;
183
184 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
185 reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
186 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
187
188 for (i = 0; i < 9; ++i)
189 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
190
191
192
193 if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
194 memset(ecc_code, 0xff, 9);
195
196 return 0;
197}
198
199static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
200{
201 int offset = index & 0x7;
202 uint16_t data;
203
204 index += (index >> 3);
205
206 data = dat[index];
207 data |= dat[index+1] << 8;
208
209 mask ^= (data >> offset) & 0x1ff;
210 data &= ~(0x1ff << offset);
211 data |= (mask << offset);
212
213 dat[index] = data & 0xff;
214 dat[index+1] = (data >> 8) & 0xff;
215}
216
217static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
218 uint8_t *read_ecc, uint8_t *calc_ecc)
219{
220 struct jz_nand *nand = mtd_to_jz_nand(mtd);
221 int i, error_count, index;
222 uint32_t reg, status, error;
223 unsigned int timeout = 1000;
224
225 for (i = 0; i < 9; ++i)
226 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
227
228 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
229 reg |= JZ_NAND_ECC_CTRL_PAR_READY;
230 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
231
232 do {
233 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
234 } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
235
236 if (timeout == 0)
237 return -ETIMEDOUT;
238
239 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
240 reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
241 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
242
243 if (status & JZ_NAND_STATUS_ERROR) {
244 if (status & JZ_NAND_STATUS_UNCOR_ERROR)
245 return -EBADMSG;
246
247 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
248
249 for (i = 0; i < error_count; ++i) {
250 error = readl(nand->base + JZ_REG_NAND_ERR(i));
251 index = ((error >> 16) & 0x1ff) - 1;
252 if (index >= 0 && index < 512)
253 jz_nand_correct_data(dat, index, error & 0x1ff);
254 }
255
256 return error_count;
257 }
258
259 return 0;
260}
261
262static int jz_nand_ioremap_resource(struct platform_device *pdev,
263 const char *name, struct resource **res, void *__iomem *base)
264{
265 int ret;
266
267 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
268 if (!*res) {
269 dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
270 ret = -ENXIO;
271 goto err;
272 }
273
274 *res = request_mem_region((*res)->start, resource_size(*res),
275 pdev->name);
276 if (!*res) {
277 dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
278 ret = -EBUSY;
279 goto err;
280 }
281
282 *base = ioremap((*res)->start, resource_size(*res));
283 if (!*base) {
284 dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
285 ret = -EBUSY;
286 goto err_release_mem;
287 }
288
289 return 0;
290
291err_release_mem:
292 release_mem_region((*res)->start, resource_size(*res));
293err:
294 *res = NULL;
295 *base = NULL;
296 return ret;
297}
298
299static inline void jz_nand_iounmap_resource(struct resource *res,
300 void __iomem *base)
301{
302 iounmap(base);
303 release_mem_region(res->start, resource_size(res));
304}
305
306static int jz_nand_detect_bank(struct platform_device *pdev,
307 struct jz_nand *nand, unsigned char bank,
308 size_t chipnr, uint8_t *nand_maf_id,
309 uint8_t *nand_dev_id)
310{
311 int ret;
312 char res_name[6];
313 uint32_t ctrl;
314 struct nand_chip *chip = &nand->chip;
315 struct mtd_info *mtd = nand_to_mtd(chip);
316 u8 id[2];
317
318
319 sprintf(res_name, "bank%d", bank);
320 ret = jz_nand_ioremap_resource(pdev, res_name,
321 &nand->bank_mem[bank - 1],
322 &nand->bank_base[bank - 1]);
323 if (ret)
324 return ret;
325
326
327 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
328 ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
329 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
330
331 if (chipnr == 0) {
332
333 ret = nand_scan_ident(mtd, 1, NULL);
334 if (ret)
335 goto notfound_id;
336
337
338 chip->select_chip(mtd, 0);
339 nand_reset_op(chip);
340 nand_readid_op(chip, 0, id, sizeof(id));
341 *nand_maf_id = id[0];
342 *nand_dev_id = id[1];
343 } else {
344
345 chip->select_chip(mtd, chipnr);
346 nand_reset_op(chip);
347 nand_readid_op(chip, 0, id, sizeof(id));
348 if (*nand_maf_id != id[0] || *nand_dev_id != id[1]) {
349 ret = -ENODEV;
350 goto notfound_id;
351 }
352
353
354 chip->numchips++;
355 mtd->size += chip->chipsize;
356 }
357
358 dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
359 return 0;
360
361notfound_id:
362 dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
363 ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
364 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
365 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
366 nand->bank_base[bank - 1]);
367 return ret;
368}
369
370static int jz_nand_probe(struct platform_device *pdev)
371{
372 int ret;
373 struct jz_nand *nand;
374 struct nand_chip *chip;
375 struct mtd_info *mtd;
376 struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
377 size_t chipnr, bank_idx;
378 uint8_t nand_maf_id = 0, nand_dev_id = 0;
379
380 nand = kzalloc(sizeof(*nand), GFP_KERNEL);
381 if (!nand)
382 return -ENOMEM;
383
384 ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
385 if (ret)
386 goto err_free;
387
388 nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
389 if (IS_ERR(nand->busy_gpio)) {
390 ret = PTR_ERR(nand->busy_gpio);
391 dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
392 ret);
393 goto err_iounmap_mmio;
394 }
395
396 chip = &nand->chip;
397 mtd = nand_to_mtd(chip);
398 mtd->dev.parent = &pdev->dev;
399 mtd->name = "jz4740-nand";
400
401 chip->ecc.hwctl = jz_nand_hwctl;
402 chip->ecc.calculate = jz_nand_calculate_ecc_rs;
403 chip->ecc.correct = jz_nand_correct_ecc_rs;
404 chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
405 chip->ecc.size = 512;
406 chip->ecc.bytes = 9;
407 chip->ecc.strength = 4;
408 chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
409
410 chip->chip_delay = 50;
411 chip->cmd_ctrl = jz_nand_cmd_ctrl;
412 chip->select_chip = jz_nand_select_chip;
413
414 if (nand->busy_gpio)
415 chip->dev_ready = jz_nand_dev_ready;
416
417 platform_set_drvdata(pdev, nand);
418
419
420
421
422
423
424
425
426 chipnr = 0;
427 for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
428 unsigned char bank;
429
430
431
432
433
434 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
435 if (bank == 0)
436 break;
437 if (bank > JZ_NAND_NUM_BANKS) {
438 dev_warn(&pdev->dev,
439 "Skipping non-existing bank: %d\n", bank);
440 continue;
441 }
442
443
444
445
446 nand->banks[chipnr] = bank;
447 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
448 &nand_maf_id, &nand_dev_id) == 0)
449 chipnr++;
450 else
451 nand->banks[chipnr] = 0;
452 }
453 if (chipnr == 0) {
454 dev_err(&pdev->dev, "No NAND chips found\n");
455 goto err_iounmap_mmio;
456 }
457
458 if (pdata && pdata->ident_callback) {
459 pdata->ident_callback(pdev, mtd, &pdata->partitions,
460 &pdata->num_partitions);
461 }
462
463 ret = nand_scan_tail(mtd);
464 if (ret) {
465 dev_err(&pdev->dev, "Failed to scan NAND\n");
466 goto err_unclaim_banks;
467 }
468
469 ret = mtd_device_parse_register(mtd, NULL, NULL,
470 pdata ? pdata->partitions : NULL,
471 pdata ? pdata->num_partitions : 0);
472
473 if (ret) {
474 dev_err(&pdev->dev, "Failed to add mtd device\n");
475 goto err_nand_release;
476 }
477
478 dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
479
480 return 0;
481
482err_nand_release:
483 nand_release(mtd);
484err_unclaim_banks:
485 while (chipnr--) {
486 unsigned char bank = nand->banks[chipnr];
487 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
488 nand->bank_base[bank - 1]);
489 }
490 writel(0, nand->base + JZ_REG_NAND_CTRL);
491err_iounmap_mmio:
492 jz_nand_iounmap_resource(nand->mem, nand->base);
493err_free:
494 kfree(nand);
495 return ret;
496}
497
498static int jz_nand_remove(struct platform_device *pdev)
499{
500 struct jz_nand *nand = platform_get_drvdata(pdev);
501 size_t i;
502
503 nand_release(nand_to_mtd(&nand->chip));
504
505
506 writel(0, nand->base + JZ_REG_NAND_CTRL);
507
508 for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
509 unsigned char bank = nand->banks[i];
510 if (bank != 0) {
511 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
512 nand->bank_base[bank - 1]);
513 }
514 }
515
516 jz_nand_iounmap_resource(nand->mem, nand->base);
517
518 kfree(nand);
519
520 return 0;
521}
522
523static struct platform_driver jz_nand_driver = {
524 .probe = jz_nand_probe,
525 .remove = jz_nand_remove,
526 .driver = {
527 .name = "jz4740-nand",
528 },
529};
530
531module_platform_driver(jz_nand_driver);
532
533MODULE_LICENSE("GPL");
534MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
535MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
536MODULE_ALIAS("platform:jz4740-nand");
537
