1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15#ifndef __INC_HAL8188EPHYREG_H__ 16#define __INC_HAL8188EPHYREG_H__ 17/*--------------------------Define Parameters-------------------------------*/ 18/* */ 19/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 20/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 21/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 22/* 3. RF register 0x00-2E */ 23/* 4. Bit Mask for BB/RF register */ 24/* 5. Other definition for BB/RF R/W */ 25/* */ 26 27 28/* */ 29/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 30/* 1. Page1(0x100) */ 31/* */ 32#define rPMAC_Reset 0x100 33#define rPMAC_TxStart 0x104 34#define rPMAC_TxLegacySIG 0x108 35#define rPMAC_TxHTSIG1 0x10c 36#define rPMAC_TxHTSIG2 0x110 37#define rPMAC_PHYDebug 0x114 38#define rPMAC_TxPacketNum 0x118 39#define rPMAC_TxIdle 0x11c 40#define rPMAC_TxMACHeader0 0x120 41#define rPMAC_TxMACHeader1 0x124 42#define rPMAC_TxMACHeader2 0x128 43#define rPMAC_TxMACHeader3 0x12c 44#define rPMAC_TxMACHeader4 0x130 45#define rPMAC_TxMACHeader5 0x134 46#define rPMAC_TxDataType 0x138 47#define rPMAC_TxRandomSeed 0x13c 48#define rPMAC_CCKPLCPPreamble 0x140 49#define rPMAC_CCKPLCPHeader 0x144 50#define rPMAC_CCKCRC16 0x148 51#define rPMAC_OFDMRxCRC32OK 0x170 52#define rPMAC_OFDMRxCRC32Er 0x174 53#define rPMAC_OFDMRxParityEr 0x178 54#define rPMAC_OFDMRxCRC8Er 0x17c 55#define rPMAC_CCKCRxRC16Er 0x180 56#define rPMAC_CCKCRxRC32Er 0x184 57#define rPMAC_CCKCRxRC32OK 0x188 58#define rPMAC_TxStatus 0x18c 59 60/* 2. Page2(0x200) */ 61/* The following two definition are only used for USB interface. */ 62#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */ 63#define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */ 64 65/* 3. Page8(0x800) */ 66#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ 67 68#define rFPGA0_TxInfo 0x804 /* Status report?? */ 69#define rFPGA0_PSDFunction 0x808 70 71#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 72 73#define rFPGA0_RFTiming1 0x810 /* Useless now */ 74#define rFPGA0_RFTiming2 0x814 75 76#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 77#define rFPGA0_XA_HSSIParameter2 0x824 78#define rFPGA0_XB_HSSIParameter1 0x828 79#define rFPGA0_XB_HSSIParameter2 0x82c 80 81#define rFPGA0_XA_LSSIParameter 0x840 82#define rFPGA0_XB_LSSIParameter 0x844 83 84#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 85#define rFPGA0_RFSleepUpParameter 0x854 86 87#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 88#define rFPGA0_XCD_SwitchControl 0x85c 89 90#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 91#define rFPGA0_XB_RFInterfaceOE 0x864 92 93#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ 94#define rFPGA0_XCD_RFInterfaceSW 0x874 95 96#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 97#define rFPGA0_XCD_RFParameter 0x87c 98 99/* Crystal cap setting RF-R/W protection for parameter4?? */ 100#define rFPGA0_AnalogParameter1 0x880 101#define rFPGA0_AnalogParameter2 0x884 102#define rFPGA0_AnalogParameter3 0x888 103/* enable ad/da clock1 for dual-phy */ 104#define rFPGA0_AdDaClockEn 0x888 105#define rFPGA0_AnalogParameter4 0x88c 106 107#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 108#define rFPGA0_XB_LSSIReadBack 0x8a4 109#define rFPGA0_XC_LSSIReadBack 0x8a8 110#define rFPGA0_XD_LSSIReadBack 0x8ac 111 112#define rFPGA0_PSDReport 0x8b4 /* Useless now */ 113/* Transceiver A HSPI Readback */ 114#define TransceiverA_HSPI_Readback 0x8b8 115/* Transceiver B HSPI Readback */ 116#define TransceiverB_HSPI_Readback 0x8bc 117/* Useless now RF Interface Readback Value */ 118#define rFPGA0_XAB_RFInterfaceRB 0x8e0 119#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 120 121/* 4. Page9(0x900) */ 122/* RF mode & OFDM TxSC RF BW Setting?? */ 123#define rFPGA1_RFMOD 0x900 124 125#define rFPGA1_TxBlock 0x904 /* Useless now */ 126#define rFPGA1_DebugSelect 0x908 /* Useless now */ 127#define rFPGA1_TxInfo 0x90c /* Useless now Status report */ 128 129/* 5. PageA(0xA00) */ 130/* Set Control channel to upper or lower - required only for 40MHz */ 131#define rCCK0_System 0xa00 132 133/* Disable init gain now Select RX path by RSSI */ 134#define rCCK0_AFESetting 0xa04 135/* Disable init gain now Init gain */ 136#define rCCK0_CCA 0xa08 137 138/* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, 139 * RX LNA Threshold useless now. Not the same as 90 series 140 */ 141#define rCCK0_RxAGC1 0xa0c 142#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 143 144#define rCCK0_RxHP 0xa14 145 146/* Timing recovery & Channel estimation threshold */ 147#define rCCK0_DSPParameter1 0xa18 148#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 149 150#define rCCK0_TxFilter1 0xa20 151#define rCCK0_TxFilter2 0xa24 152#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 153#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */ 154#define rCCK0_TRSSIReport 0xa50 155#define rCCK0_RxReport 0xa54 /* 0xa57 */ 156#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 157#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 158 159/* */ 160/* PageB(0xB00) */ 161/* */ 162#define rPdp_AntA 0xb00 163#define rPdp_AntA_4 0xb04 164#define rConfig_Pmpd_AntA 0xb28 165#define rConfig_AntA 0xb68 166#define rConfig_AntB 0xb6c 167#define rPdp_AntB 0xb70 168#define rPdp_AntB_4 0xb74 169#define rConfig_Pmpd_AntB 0xb98 170#define rAPK 0xbd8 171 172/* */ 173/* 6. PageC(0xC00) */ 174/* */ 175#define rOFDM0_LSTF 0xc00 176 177#define rOFDM0_TRxPathEnable 0xc04 178#define rOFDM0_TRMuxPar 0xc08 179#define rOFDM0_TRSWIsolation 0xc0c 180 181/* RxIQ DC offset, Rx digital filter, DC notch filter */ 182#define rOFDM0_XARxAFE 0xc10 183#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 184#define rOFDM0_XBRxAFE 0xc18 185#define rOFDM0_XBRxIQImbalance 0xc1c 186#define rOFDM0_XCRxAFE 0xc20 187#define rOFDM0_XCRxIQImbalance 0xc24 188#define rOFDM0_XDRxAFE 0xc28 189#define rOFDM0_XDRxIQImbalance 0xc2c 190 191#define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/ 192#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 193#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 194#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 195 196#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 197#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 198#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 199#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 200 201#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 202#define rOFDM0_XAAGCCore2 0xc54 203#define rOFDM0_XBAGCCore1 0xc58 204#define rOFDM0_XBAGCCore2 0xc5c 205#define rOFDM0_XCAGCCore1 0xc60 206#define rOFDM0_XCAGCCore2 0xc64 207#define rOFDM0_XDAGCCore1 0xc68 208#define rOFDM0_XDAGCCore2 0xc6c 209 210#define rOFDM0_AGCParameter1 0xc70 211#define rOFDM0_AGCParameter2 0xc74 212#define rOFDM0_AGCRSSITable 0xc78 213#define rOFDM0_HTSTFAGC 0xc7c 214 215#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 216#define rOFDM0_XATxAFE 0xc84 217#define rOFDM0_XBTxIQImbalance 0xc88 218#define rOFDM0_XBTxAFE 0xc8c 219#define rOFDM0_XCTxIQImbalance 0xc90 220#define rOFDM0_XCTxAFE 0xc94 221#define rOFDM0_XDTxIQImbalance 0xc98 222#define rOFDM0_XDTxAFE 0xc9c 223 224#define rOFDM0_RxIQExtAnta 0xca0 225#define rOFDM0_TxCoeff1 0xca4 226#define rOFDM0_TxCoeff2 0xca8 227#define rOFDM0_TxCoeff3 0xcac 228#define rOFDM0_TxCoeff4 0xcb0 229#define rOFDM0_TxCoeff5 0xcb4 230#define rOFDM0_TxCoeff6 0xcb8 231#define rOFDM0_RxHPParameter 0xce0 232#define rOFDM0_TxPseudoNoiseWgt 0xce4 233#define rOFDM0_FrameSync 0xcf0 234#define rOFDM0_DFSReport 0xcf4 235 236 237/* */ 238/* 7. PageD(0xD00) */ 239/* */ 240#define rOFDM1_LSTF 0xd00 241#define rOFDM1_TRxPathEnable 0xd04 242 243#define rOFDM1_CFO 0xd08 /* No setting now */ 244#define rOFDM1_CSI1 0xd10 245#define rOFDM1_SBD 0xd14 246#define rOFDM1_CSI2 0xd18 247#define rOFDM1_CFOTracking 0xd2c 248#define rOFDM1_TRxMesaure1 0xd34 249#define rOFDM1_IntfDet 0xd3c 250#define rOFDM1_PseudoNoiseStateAB 0xd50 251#define rOFDM1_PseudoNoiseStateCD 0xd54 252#define rOFDM1_RxPseudoNoiseWgt 0xd58 253 254#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 255#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 256#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 257 258#define rOFDM_ShortCFOAB 0xdac /* No setting now */ 259#define rOFDM_ShortCFOCD 0xdb0 260#define rOFDM_LongCFOAB 0xdb4 261#define rOFDM_LongCFOCD 0xdb8 262#define rOFDM_TailCFOAB 0xdbc 263#define rOFDM_TailCFOCD 0xdc0 264#define rOFDM_PWMeasure1 0xdc4 265#define rOFDM_PWMeasure2 0xdc8 266#define rOFDM_BWReport 0xdcc 267#define rOFDM_AGCReport 0xdd0 268#define rOFDM_RxSNR 0xdd4 269#define rOFDM_RxEVMCSI 0xdd8 270#define rOFDM_SIGReport 0xddc 271 272 273/* */ 274/* 8. PageE(0xE00) */ 275/* */ 276#define rTxAGC_A_Rate18_06 0xe00 277#define rTxAGC_A_Rate54_24 0xe04 278#define rTxAGC_A_CCK1_Mcs32 0xe08 279#define rTxAGC_A_Mcs03_Mcs00 0xe10 280#define rTxAGC_A_Mcs07_Mcs04 0xe14 281#define rTxAGC_A_Mcs11_Mcs08 0xe18 282#define rTxAGC_A_Mcs15_Mcs12 0xe1c 283 284#define rTxAGC_B_Rate18_06 0x830 285#define rTxAGC_B_Rate54_24 0x834 286#define rTxAGC_B_CCK1_55_Mcs32 0x838 287#define rTxAGC_B_Mcs03_Mcs00 0x83c 288#define rTxAGC_B_Mcs07_Mcs04 0x848 289#define rTxAGC_B_Mcs11_Mcs08 0x84c 290#define rTxAGC_B_Mcs15_Mcs12 0x868 291#define rTxAGC_B_CCK11_A_CCK2_11 0x86c 292 293#define rFPGA0_IQK 0xe28 294#define rTx_IQK_Tone_A 0xe30 295#define rRx_IQK_Tone_A 0xe34 296#define rTx_IQK_PI_A 0xe38 297#define rRx_IQK_PI_A 0xe3c 298 299#define rTx_IQK 0xe40 300#define rRx_IQK 0xe44 301#define rIQK_AGC_Pts 0xe48 302#define rIQK_AGC_Rsp 0xe4c 303#define rTx_IQK_Tone_B 0xe50 304#define rRx_IQK_Tone_B 0xe54 305#define rTx_IQK_PI_B 0xe58 306#define rRx_IQK_PI_B 0xe5c 307#define rIQK_AGC_Cont 0xe60 308 309#define rBlue_Tooth 0xe6c 310#define rRx_Wait_CCA 0xe70 311#define rTx_CCK_RFON 0xe74 312#define rTx_CCK_BBON 0xe78 313#define rTx_OFDM_RFON 0xe7c 314#define rTx_OFDM_BBON 0xe80 315#define rTx_To_Rx 0xe84 316#define rTx_To_Tx 0xe88 317#define rRx_CCK 0xe8c 318 319#define rTx_Power_Before_IQK_A 0xe94 320#define rTx_Power_After_IQK_A 0xe9c 321 322#define rRx_Power_Before_IQK_A 0xea0 323#define rRx_Power_Before_IQK_A_2 0xea4 324#define rRx_Power_After_IQK_A 0xea8 325#define rRx_Power_After_IQK_A_2 0xeac 326 327#define rTx_Power_Before_IQK_B 0xeb4 328#define rTx_Power_After_IQK_B 0xebc 329 330#define rRx_Power_Before_IQK_B 0xec0 331#define rRx_Power_Before_IQK_B_2 0xec4 332#define rRx_Power_After_IQK_B 0xec8 333#define rRx_Power_After_IQK_B_2 0xecc 334 335#define rRx_OFDM 0xed0 336#define rRx_Wait_RIFS 0xed4 337#define rRx_TO_Rx 0xed8 338#define rStandby 0xedc 339#define rSleep 0xee0 340#define rPMPD_ANAEN 0xeec 341 342/* */ 343/* 7. RF Register 0x00-0x2E (RF 8256) */ 344/* RF-0222D 0x00-3F */ 345/* */ 346/* Zebra1 */ 347#define rZebra1_HSSIEnable 0x0 /* Useless now */ 348#define rZebra1_TRxEnable1 0x1 349#define rZebra1_TRxEnable2 0x2 350#define rZebra1_AGC 0x4 351#define rZebra1_ChargePump 0x5 352#define rZebra1_Channel 0x7 /* RF channel switch */ 353 354/* endif */ 355#define rZebra1_TxGain 0x8 /* Useless now */ 356#define rZebra1_TxLPF 0x9 357#define rZebra1_RxLPF 0xb 358#define rZebra1_RxHPFCorner 0xc 359 360/* Zebra4 */ 361#define rGlobalCtrl 0 /* Useless now */ 362#define rRTL8256_TxLPF 19 363#define rRTL8256_RxLPF 11 364 365/* RTL8258 */ 366#define rRTL8258_TxLPF 0x11 /* Useless now */ 367#define rRTL8258_RxLPF 0x13 368#define rRTL8258_RSSILPF 0xa 369 370/* */ 371/* RL6052 Register definition */ 372/* */ 373#define RF_AC 0x00 /* */ 374 375#define RF_IQADJ_G1 0x01 /* */ 376#define RF_IQADJ_G2 0x02 /* */ 377 378#define RF_POW_TRSW 0x05 /* */ 379 380#define RF_GAIN_RX 0x06 /* */ 381#define RF_GAIN_TX 0x07 /* */ 382 383#define RF_TXM_IDAC 0x08 /* */ 384#define RF_IPA_G 0x09 /* */ 385#define RF_TXBIAS_G 0x0A 386#define RF_TXPA_AG 0x0B 387#define RF_IPA_A 0x0C /* */ 388#define RF_TXBIAS_A 0x0D 389#define RF_BS_PA_APSET_G9_G11 0x0E 390#define RF_BS_IQGEN 0x0F /* */ 391 392#define RF_MODE1 0x10 /* */ 393#define RF_MODE2 0x11 /* */ 394 395#define RF_RX_AGC_HP 0x12 /* */ 396#define RF_TX_AGC 0x13 /* */ 397#define RF_BIAS 0x14 /* */ 398#define RF_IPA 0x15 /* */ 399#define RF_TXBIAS 0x16 400#define RF_POW_ABILITY 0x17 /* */ 401#define RF_CHNLBW 0x18 /* RF channel and BW switch */ 402#define RF_TOP 0x19 /* */ 403 404#define RF_RX_G1 0x1A /* */ 405#define RF_RX_G2 0x1B /* */ 406 407#define RF_RX_BB2 0x1C /* */ 408#define RF_RX_BB1 0x1D /* */ 409 410#define RF_RCK1 0x1E /* */ 411#define RF_RCK2 0x1F /* */ 412 413#define RF_TX_G1 0x20 /* */ 414#define RF_TX_G2 0x21 /* */ 415#define RF_TX_G3 0x22 /* */ 416 417#define RF_TX_BB1 0x23 /* */ 418 419#define RF_T_METER_92D 0x42 /* */ 420#define RF_T_METER_88E 0x42 /* */ 421#define RF_T_METER 0x24 /* */ 422 423#define RF_SYN_G1 0x25 /* RF TX Power control */ 424#define RF_SYN_G2 0x26 /* RF TX Power control */ 425#define RF_SYN_G3 0x27 /* RF TX Power control */ 426#define RF_SYN_G4 0x28 /* RF TX Power control */ 427#define RF_SYN_G5 0x29 /* RF TX Power control */ 428#define RF_SYN_G6 0x2A /* RF TX Power control */ 429#define RF_SYN_G7 0x2B /* RF TX Power control */ 430#define RF_SYN_G8 0x2C /* RF TX Power control */ 431 432#define RF_RCK_OS 0x30 /* RF TX PA control */ 433#define RF_TXPA_G1 0x31 /* RF TX PA control */ 434#define RF_TXPA_G2 0x32 /* RF TX PA control */ 435#define RF_TXPA_G3 0x33 /* RF TX PA control */ 436#define RF_TX_BIAS_A 0x35 437#define RF_TX_BIAS_D 0x36 438#define RF_LOBF_9 0x38 439#define RF_RXRF_A3 0x3C /* */ 440#define RF_TRSW 0x3F 441 442#define RF_TXRF_A2 0x41 443#define RF_TXPA_G4 0x46 444#define RF_TXPA_A4 0x4B 445#define RF_0x52 0x52 446#define RF_WE_LUT 0xEF 447 448 449/* */ 450/* Bit Mask */ 451/* */ 452/* 1. Page1(0x100) */ 453#define bBBResetB 0x100 /* Useless now? */ 454#define bGlobalResetB 0x200 455#define bOFDMTxStart 0x4 456#define bCCKTxStart 0x8 457#define bCRC32Debug 0x100 458#define bPMACLoopback 0x10 459#define bTxLSIG 0xffffff 460#define bOFDMTxRate 0xf 461#define bOFDMTxReserved 0x10 462#define bOFDMTxLength 0x1ffe0 463#define bOFDMTxParity 0x20000 464#define bTxHTSIG1 0xffffff 465#define bTxHTMCSRate 0x7f 466#define bTxHTBW 0x80 467#define bTxHTLength 0xffff00 468#define bTxHTSIG2 0xffffff 469#define bTxHTSmoothing 0x1 470#define bTxHTSounding 0x2 471#define bTxHTReserved 0x4 472#define bTxHTAggreation 0x8 473#define bTxHTSTBC 0x30 474#define bTxHTAdvanceCoding 0x40 475#define bTxHTShortGI 0x80 476#define bTxHTNumberHT_LTF 0x300 477#define bTxHTCRC8 0x3fc00 478#define bCounterReset 0x10000 479#define bNumOfOFDMTx 0xffff 480#define bNumOfCCKTx 0xffff0000 481#define bTxIdleInterval 0xffff 482#define bOFDMService 0xffff0000 483#define bTxMACHeader 0xffffffff 484#define bTxDataInit 0xff 485#define bTxHTMode 0x100 486#define bTxDataType 0x30000 487#define bTxRandomSeed 0xffffffff 488#define bCCKTxPreamble 0x1 489#define bCCKTxSFD 0xffff0000 490#define bCCKTxSIG 0xff 491#define bCCKTxService 0xff00 492#define bCCKLengthExt 0x8000 493#define bCCKTxLength 0xffff0000 494#define bCCKTxCRC16 0xffff 495#define bCCKTxStatus 0x1 496#define bOFDMTxStatus 0x2 497 498#define IS_BB_REG_OFFSET_92S(_Offset) \ 499 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 500 501/* 2. Page8(0x800) */ 502#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 503#define bJapanMode 0x2 504#define bCCKTxSC 0x30 505#define bCCKEn 0x1000000 506#define bOFDMEn 0x2000000 507 508#define bOFDMRxADCPhase 0x10000 /* Useless now */ 509#define bOFDMTxDACPhase 0x40000 510#define bXATxAGC 0x3f 511 512#define bAntennaSelect 0x0300 513 514#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 515#define bXCTxAGC 0xf000 516#define bXDTxAGC 0xf0000 517 518#define bPAStart 0xf0000000 /* Useless now */ 519#define bTRStart 0x00f00000 520#define bRFStart 0x0000f000 521#define bBBStart 0x000000f0 522#define bBBCCKStart 0x0000000f 523#define bPAEnd 0xf /* Reg0x814 */ 524#define bTREnd 0x0f000000 525#define bRFEnd 0x000f0000 526#define bCCAMask 0x000000f0 /* T2R */ 527#define bR2RCCAMask 0x00000f00 528#define bHSSI_R2TDelay 0xf8000000 529#define bHSSI_T2RDelay 0xf80000 530#define bContTxHSSI 0x400 /* change gain at continue Tx */ 531#define bIGFromCCK 0x200 532#define bAGCAddress 0x3f 533#define bRxHPTx 0x7000 534#define bRxHPT2R 0x38000 535#define bRxHPCCKIni 0xc0000 536#define bAGCTxCode 0xc00000 537#define bAGCRxCode 0x300000 538 539/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 540#define b3WireDataLength 0x800 541#define b3WireAddressLength 0x400 542 543#define b3WireRFPowerDown 0x1 /* Useless now */ 544#define b5GPAPEPolarity 0x40000000 545#define b2GPAPEPolarity 0x80000000 546#define bRFSW_TxDefaultAnt 0x3 547#define bRFSW_TxOptionAnt 0x30 548#define bRFSW_RxDefaultAnt 0x300 549#define bRFSW_RxOptionAnt 0x3000 550#define bRFSI_3WireData 0x1 551#define bRFSI_3WireClock 0x2 552#define bRFSI_3WireLoad 0x4 553#define bRFSI_3WireRW 0x8 554#define bRFSI_3Wire 0xf 555 556#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 557 558#define bRFSI_TRSW 0x20 /* Useless now */ 559#define bRFSI_TRSWB 0x40 560#define bRFSI_ANTSW 0x100 561#define bRFSI_ANTSWB 0x200 562#define bRFSI_PAPE 0x400 563#define bRFSI_PAPE5G 0x800 564#define bBandSelect 0x1 565#define bHTSIG2_GI 0x80 566#define bHTSIG2_Smoothing 0x01 567#define bHTSIG2_Sounding 0x02 568#define bHTSIG2_Aggreaton 0x08 569#define bHTSIG2_STBC 0x30 570#define bHTSIG2_AdvCoding 0x40 571#define bHTSIG2_NumOfHTLTF 0x300 572#define bHTSIG2_CRC8 0x3fc 573#define bHTSIG1_MCS 0x7f 574#define bHTSIG1_BandWidth 0x80 575#define bHTSIG1_HTLength 0xffff 576#define bLSIG_Rate 0xf 577#define bLSIG_Reserved 0x10 578#define bLSIG_Length 0x1fffe 579#define bLSIG_Parity 0x20 580#define bCCKRxPhase 0x4 581 582#define bLSSIReadAddress 0x7f800000 /* T65 RF */ 583 584#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 585 586#define bLSSIReadBackData 0xfffff /* T65 RF */ 587 588#define bLSSIReadOKFlag 0x1000 /* Useless now */ 589#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 590#define bRegulator0Standby 0x1 591#define bRegulatorPLLStandby 0x2 592#define bRegulator1Standby 0x4 593#define bPLLPowerUp 0x8 594#define bDPLLPowerUp 0x10 595#define bDA10PowerUp 0x20 596#define bAD7PowerUp 0x200 597#define bDA6PowerUp 0x2000 598#define bXtalPowerUp 0x4000 599#define b40MDClkPowerUP 0x8000 600#define bDA6DebugMode 0x20000 601#define bDA6Swing 0x380000 602 603/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 604#define bADClkPhase 0x4000000 605 606#define b80MClkDelay 0x18000000 /* Useless */ 607#define bAFEWatchDogEnable 0x20000000 608 609/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 610#define bXtalCap01 0xc0000000 611#define bXtalCap23 0x3 612#define bXtalCap92x 0x0f000000 613#define bXtalCap 0x0f000000 614 615#define bIntDifClkEnable 0x400 /* Useless */ 616#define bExtSigClkEnable 0x800 617#define bBandgapMbiasPowerUp 0x10000 618#define bAD11SHGain 0xc0000 619#define bAD11InputRange 0x700000 620#define bAD11OPCurrent 0x3800000 621#define bIPathLoopback 0x4000000 622#define bQPathLoopback 0x8000000 623#define bAFELoopback 0x10000000 624#define bDA10Swing 0x7e0 625#define bDA10Reverse 0x800 626#define bDAClkSource 0x1000 627#define bAD7InputRange 0x6000 628#define bAD7Gain 0x38000 629#define bAD7OutputCMMode 0x40000 630#define bAD7InputCMMode 0x380000 631#define bAD7Current 0xc00000 632#define bRegulatorAdjust 0x7000000 633#define bAD11PowerUpAtTx 0x1 634#define bDA10PSAtTx 0x10 635#define bAD11PowerUpAtRx 0x100 636#define bDA10PSAtRx 0x1000 637#define bCCKRxAGCFormat 0x200 638#define bPSDFFTSamplepPoint 0xc000 639#define bPSDAverageNum 0x3000 640#define bIQPathControl 0xc00 641#define bPSDFreq 0x3ff 642#define bPSDAntennaPath 0x30 643#define bPSDIQSwitch 0x40 644#define bPSDRxTrigger 0x400000 645#define bPSDTxTrigger 0x80000000 646#define bPSDSineToneScale 0x7f000000 647#define bPSDReport 0xffff 648 649/* 3. Page9(0x900) */ 650#define bOFDMTxSC 0x30000000 /* Useless */ 651#define bCCKTxOn 0x1 652#define bOFDMTxOn 0x2 653#define bDebugPage 0xfff /* reset debug page and HWord, LWord */ 654#define bDebugItem 0xff /* reset debug page and LWord */ 655#define bAntL 0x10 656#define bAntNonHT 0x100 657#define bAntHT1 0x1000 658#define bAntHT2 0x10000 659#define bAntHT1S1 0x100000 660#define bAntNonHTS1 0x1000000 661 662/* 4. PageA(0xA00) */ 663#define bCCKBBMode 0x3 /* Useless */ 664#define bCCKTxPowerSaving 0x80 665#define bCCKRxPowerSaving 0x40 666 667#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */ 668 669#define bCCKScramble 0x8 /* Useless */ 670#define bCCKAntDiversity 0x8000 671#define bCCKCarrierRecovery 0x4000 672#define bCCKTxRate 0x3000 673#define bCCKDCCancel 0x0800 674#define bCCKISICancel 0x0400 675#define bCCKMatchFilter 0x0200 676#define bCCKEqualizer 0x0100 677#define bCCKPreambleDetect 0x800000 678#define bCCKFastFalseCCA 0x400000 679#define bCCKChEstStart 0x300000 680#define bCCKCCACount 0x080000 681#define bCCKcs_lim 0x070000 682#define bCCKBistMode 0x80000000 683#define bCCKCCAMask 0x40000000 684#define bCCKTxDACPhase 0x4 685#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 686#define bCCKr_cp_mode0 0x0100 687#define bCCKTxDCOffset 0xf0 688#define bCCKRxDCOffset 0xf 689#define bCCKCCAMode 0xc000 690#define bCCKFalseCS_lim 0x3f00 691#define bCCKCS_ratio 0xc00000 692#define bCCKCorgBit_sel 0x300000 693#define bCCKPD_lim 0x0f0000 694#define bCCKNewCCA 0x80000000 695#define bCCKRxHPofIG 0x8000 696#define bCCKRxIG 0x7f00 697#define bCCKLNAPolarity 0x800000 698#define bCCKRx1stGain 0x7f0000 699#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 700#define bCCKRxAGCSatLevel 0x1f000000 701#define bCCKRxAGCSatCount 0xe0 702#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 703#define bCCKFixedRxAGC 0x8000 704#define bCCKAntennaPolarity 0x2000 705#define bCCKTxFilterType 0x0c00 706#define bCCKRxAGCReportType 0x0300 707#define bCCKRxDAGCEn 0x80000000 708#define bCCKRxDAGCPeriod 0x20000000 709#define bCCKRxDAGCSatLevel 0x1f000000 710#define bCCKTimingRecovery 0x800000 711#define bCCKTxC0 0x3f0000 712#define bCCKTxC1 0x3f000000 713#define bCCKTxC2 0x3f 714#define bCCKTxC3 0x3f00 715#define bCCKTxC4 0x3f0000 716#define bCCKTxC5 0x3f000000 717#define bCCKTxC6 0x3f 718#define bCCKTxC7 0x3f00 719#define bCCKDebugPort 0xff0000 720#define bCCKDACDebug 0x0f000000 721#define bCCKFalseAlarmEnable 0x8000 722#define bCCKFalseAlarmRead 0x4000 723#define bCCKTRSSI 0x7f 724#define bCCKRxAGCReport 0xfe 725#define bCCKRxReport_AntSel 0x80000000 726#define bCCKRxReport_MFOff 0x40000000 727#define bCCKRxRxReport_SQLoss 0x20000000 728#define bCCKRxReport_Pktloss 0x10000000 729#define bCCKRxReport_Lockedbit 0x08000000 730#define bCCKRxReport_RateError 0x04000000 731#define bCCKRxReport_RxRate 0x03000000 732#define bCCKRxFACounterLower 0xff 733#define bCCKRxFACounterUpper 0xff000000 734#define bCCKRxHPAGCStart 0xe000 735#define bCCKRxHPAGCFinal 0x1c00 736#define bCCKRxFalseAlarmEnable 0x8000 737#define bCCKFACounterFreeze 0x4000 738#define bCCKTxPathSel 0x10000000 739#define bCCKDefaultRxPath 0xc000000 740#define bCCKOptionRxPath 0x3000000 741 742/* 5. PageC(0xC00) */ 743#define bNumOfSTF 0x3 /* Useless */ 744#define bShift_L 0xc0 745#define bGI_TH 0xc 746#define bRxPathA 0x1 747#define bRxPathB 0x2 748#define bRxPathC 0x4 749#define bRxPathD 0x8 750#define bTxPathA 0x1 751#define bTxPathB 0x2 752#define bTxPathC 0x4 753#define bTxPathD 0x8 754#define bTRSSIFreq 0x200 755#define bADCBackoff 0x3000 756#define bDFIRBackoff 0xc000 757#define bTRSSILatchPhase 0x10000 758#define bRxIDCOffset 0xff 759#define bRxQDCOffset 0xff00 760#define bRxDFIRMode 0x1800000 761#define bRxDCNFType 0xe000000 762#define bRXIQImb_A 0x3ff 763#define bRXIQImb_B 0xfc00 764#define bRXIQImb_C 0x3f0000 765#define bRXIQImb_D 0xffc00000 766#define bDC_dc_Notch 0x60000 767#define bRxNBINotch 0x1f000000 768#define bPD_TH 0xf 769#define bPD_TH_Opt2 0xc000 770#define bPWED_TH 0x700 771#define bIfMF_Win_L 0x800 772#define bPD_Option 0x1000 773#define bMF_Win_L 0xe000 774#define bBW_Search_L 0x30000 775#define bwin_enh_L 0xc0000 776#define bBW_TH 0x700000 777#define bED_TH2 0x3800000 778#define bBW_option 0x4000000 779#define bRatio_TH 0x18000000 780#define bWindow_L 0xe0000000 781#define bSBD_Option 0x1 782#define bFrame_TH 0x1c 783#define bFS_Option 0x60 784#define bDC_Slope_check 0x80 785#define bFGuard_Counter_DC_L 0xe00 786#define bFrame_Weight_Short 0x7000 787#define bSub_Tune 0xe00000 788#define bFrame_DC_Length 0xe000000 789#define bSBD_start_offset 0x30000000 790#define bFrame_TH_2 0x7 791#define bFrame_GI2_TH 0x38 792#define bGI2_Sync_en 0x40 793#define bSarch_Short_Early 0x300 794#define bSarch_Short_Late 0xc00 795#define bSarch_GI2_Late 0x70000 796#define bCFOAntSum 0x1 797#define bCFOAcc 0x2 798#define bCFOStartOffset 0xc 799#define bCFOLookBack 0x70 800#define bCFOSumWeight 0x80 801#define bDAGCEnable 0x10000 802#define bTXIQImb_A 0x3ff 803#define bTXIQImb_B 0xfc00 804#define bTXIQImb_C 0x3f0000 805#define bTXIQImb_D 0xffc00000 806#define bTxIDCOffset 0xff 807#define bTxQDCOffset 0xff00 808#define bTxDFIRMode 0x10000 809#define bTxPesudoNoiseOn 0x4000000 810#define bTxPesudoNoise_A 0xff 811#define bTxPesudoNoise_B 0xff00 812#define bTxPesudoNoise_C 0xff0000 813#define bTxPesudoNoise_D 0xff000000 814#define bCCADropOption 0x20000 815#define bCCADropThres 0xfff00000 816#define bEDCCA_H 0xf 817#define bEDCCA_L 0xf0 818#define bLambda_ED 0x300 819#define bRxInitialGain 0x7f 820#define bRxAntDivEn 0x80 821#define bRxAGCAddressForLNA 0x7f00 822#define bRxHighPowerFlow 0x8000 823#define bRxAGCFreezeThres 0xc0000 824#define bRxFreezeStep_AGC1 0x300000 825#define bRxFreezeStep_AGC2 0xc00000 826#define bRxFreezeStep_AGC3 0x3000000 827#define bRxFreezeStep_AGC0 0xc000000 828#define bRxRssi_Cmp_En 0x10000000 829#define bRxQuickAGCEn 0x20000000 830#define bRxAGCFreezeThresMode 0x40000000 831#define bRxOverFlowCheckType 0x80000000 832#define bRxAGCShift 0x7f 833#define bTRSW_Tri_Only 0x80 834#define bPowerThres 0x300 835#define bRxAGCEn 0x1 836#define bRxAGCTogetherEn 0x2 837#define bRxAGCMin 0x4 838#define bRxHP_Ini 0x7 839#define bRxHP_TRLNA 0x70 840#define bRxHP_RSSI 0x700 841#define bRxHP_BBP1 0x7000 842#define bRxHP_BBP2 0x70000 843#define bRxHP_BBP3 0x700000 844#define bRSSI_H 0x7f0000 /* threshold for high power */ 845#define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */ 846#define bRxSettle_TRSW 0x7 847#define bRxSettle_LNA 0x38 848#define bRxSettle_RSSI 0x1c0 849#define bRxSettle_BBP 0xe00 850#define bRxSettle_RxHP 0x7000 851#define bRxSettle_AntSW_RSSI 0x38000 852#define bRxSettle_AntSW 0xc0000 853#define bRxProcessTime_DAGC 0x300000 854#define bRxSettle_HSSI 0x400000 855#define bRxProcessTime_BBPPW 0x800000 856#define bRxAntennaPowerShift 0x3000000 857#define bRSSITableSelect 0xc000000 858#define bRxHP_Final 0x7000000 859#define bRxHTSettle_BBP 0x7 860#define bRxHTSettle_HSSI 0x8 861#define bRxHTSettle_RxHP 0x70 862#define bRxHTSettle_BBPPW 0x80 863#define bRxHTSettle_Idle 0x300 864#define bRxHTSettle_Reserved 0x1c00 865#define bRxHTRxHPEn 0x8000 866#define bRxHTAGCFreezeThres 0x30000 867#define bRxHTAGCTogetherEn 0x40000 868#define bRxHTAGCMin 0x80000 869#define bRxHTAGCEn 0x100000 870#define bRxHTDAGCEn 0x200000 871#define bRxHTRxHP_BBP 0x1c00000 872#define bRxHTRxHP_Final 0xe0000000 873#define bRxPWRatioTH 0x3 874#define bRxPWRatioEn 0x4 875#define bRxMFHold 0x3800 876#define bRxPD_Delay_TH1 0x38 877#define bRxPD_Delay_TH2 0x1c0 878#define bRxPD_DC_COUNT_MAX 0x600 879#define bRxPD_Delay_TH 0x8000 880#define bRxProcess_Delay 0xf0000 881#define bRxSearchrange_GI2_Early 0x700000 882#define bRxFrame_Guard_Counter_L 0x3800000 883#define bRxSGI_Guard_L 0xc000000 884#define bRxSGI_Search_L 0x30000000 885#define bRxSGI_TH 0xc0000000 886#define bDFSCnt0 0xff 887#define bDFSCnt1 0xff00 888#define bDFSFlag 0xf0000 889#define bMFWeightSum 0x300000 890#define bMinIdxTH 0x7f000000 891#define bDAFormat 0x40000 892#define bTxChEmuEnable 0x01000000 893#define bTRSWIsolation_A 0x7f 894#define bTRSWIsolation_B 0x7f00 895#define bTRSWIsolation_C 0x7f0000 896#define bTRSWIsolation_D 0x7f000000 897#define bExtLNAGain 0x7c00 898 899/* 6. PageE(0xE00) */ 900#define bSTBCEn 0x4 /* Useless */ 901#define bAntennaMapping 0x10 902#define bNss 0x20 903#define bCFOAntSumD 0x200 904#define bPHYCounterReset 0x8000000 905#define bCFOReportGet 0x4000000 906#define bOFDMContinueTx 0x10000000 907#define bOFDMSingleCarrier 0x20000000 908#define bOFDMSingleTone 0x40000000 909#define bHTDetect 0x100 910#define bCFOEn 0x10000 911#define bCFOValue 0xfff00000 912#define bSigTone_Re 0x3f 913#define bSigTone_Im 0x7f00 914#define bCounter_CCA 0xffff 915#define bCounter_ParityFail 0xffff0000 916#define bCounter_RateIllegal 0xffff 917#define bCounter_CRC8Fail 0xffff0000 918#define bCounter_MCSNoSupport 0xffff 919#define bCounter_FastSync 0xffff 920#define bShortCFO 0xfff 921#define bShortCFOTLength 12 /* total */ 922#define bShortCFOFLength 11 /* fraction */ 923#define bLongCFO 0x7ff 924#define bLongCFOTLength 11 925#define bLongCFOFLength 11 926#define bTailCFO 0x1fff 927#define bTailCFOTLength 13 928#define bTailCFOFLength 12 929#define bmax_en_pwdB 0xffff 930#define bCC_power_dB 0xffff0000 931#define bnoise_pwdB 0xffff 932#define bPowerMeasTLength 10 933#define bPowerMeasFLength 3 934#define bRx_HT_BW 0x1 935#define bRxSC 0x6 936#define bRx_HT 0x8 937#define bNB_intf_det_on 0x1 938#define bIntf_win_len_cfg 0x30 939#define bNB_Intf_TH_cfg 0x1c0 940#define bRFGain 0x3f 941#define bTableSel 0x40 942#define bTRSW 0x80 943#define bRxSNR_A 0xff 944#define bRxSNR_B 0xff00 945#define bRxSNR_C 0xff0000 946#define bRxSNR_D 0xff000000 947#define bSNREVMTLength 8 948#define bSNREVMFLength 1 949#define bCSI1st 0xff 950#define bCSI2nd 0xff00 951#define bRxEVM1st 0xff0000 952#define bRxEVM2nd 0xff000000 953#define bSIGEVM 0xff 954#define bPWDB 0xff00 955#define bSGIEN 0x10000 956 957#define bSFactorQAM1 0xf /* Useless */ 958#define bSFactorQAM2 0xf0 959#define bSFactorQAM3 0xf00 960#define bSFactorQAM4 0xf000 961#define bSFactorQAM5 0xf0000 962#define bSFactorQAM6 0xf0000 963#define bSFactorQAM7 0xf00000 964#define bSFactorQAM8 0xf000000 965#define bSFactorQAM9 0xf0000000 966#define bCSIScheme 0x100000 967 968#define bNoiseLvlTopSet 0x3 /* Useless */ 969#define bChSmooth 0x4 970#define bChSmoothCfg1 0x38 971#define bChSmoothCfg2 0x1c0 972#define bChSmoothCfg3 0xe00 973#define bChSmoothCfg4 0x7000 974#define bMRCMode 0x800000 975#define bTHEVMCfg 0x7000000 976 977#define bLoopFitType 0x1 /* Useless */ 978#define bUpdCFO 0x40 979#define bUpdCFOOffData 0x80 980#define bAdvUpdCFO 0x100 981#define bAdvTimeCtrl 0x800 982#define bUpdClko 0x1000 983#define bFC 0x6000 984#define bTrackingMode 0x8000 985#define bPhCmpEnable 0x10000 986#define bUpdClkoLTF 0x20000 987#define bComChCFO 0x40000 988#define bCSIEstiMode 0x80000 989#define bAdvUpdEqz 0x100000 990#define bUChCfg 0x7000000 991#define bUpdEqz 0x8000000 992 993/* Rx Pseduo noise */ 994#define bRxPesudoNoiseOn 0x20000000 /* Useless */ 995#define bRxPesudoNoise_A 0xff 996#define bRxPesudoNoise_B 0xff00 997#define bRxPesudoNoise_C 0xff0000 998#define bRxPesudoNoise_D 0xff000000 999#define bPesudoNoiseState_A 0xffff 1000#define bPesudoNoiseState_B 0xffff0000
1001#define bPesudoNoiseState_C 0xffff 1002#define bPesudoNoiseState_D 0xffff0000 1003 1004/* 7. RF Register */ 1005/* Zebra1 */ 1006#define bZebra1_HSSIEnable 0x8 /* Useless */ 1007#define bZebra1_TRxControl 0xc00 1008#define bZebra1_TRxGainSetting 0x07f 1009#define bZebra1_RxCorner 0xc00 1010#define bZebra1_TxChargePump 0x38 1011#define bZebra1_RxChargePump 0x7 1012#define bZebra1_ChannelNum 0xf80 1013#define bZebra1_TxLPFBW 0x400 1014#define bZebra1_RxLPFBW 0x600 1015 1016/* Zebra4 */ 1017#define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1018#define bRTL8256RegModeCtrl0 0x40 1019#define bRTL8256_TxLPFBW 0x18 1020#define bRTL8256_RxLPFBW 0x600 1021 1022/* RTL8258 */ 1023#define bRTL8258_TxLPFBW 0xc /* Useless */ 1024#define bRTL8258_RxLPFBW 0xc00 1025#define bRTL8258_RSSILPFBW 0xc0 1026 1027 1028/* */ 1029/* Other Definition */ 1030/* */ 1031 1032/* byte endable for sb_write */ 1033#define bByte0 0x1 /* Useless */ 1034#define bByte1 0x2 1035#define bByte2 0x4 1036#define bByte3 0x8 1037#define bWord0 0x3 1038#define bWord1 0xc 1039#define bDWord 0xf 1040 1041/* for PutRegsetting & GetRegSetting BitMask */ 1042#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1043#define bMaskByte1 0xff00 1044#define bMaskByte2 0xff0000 1045#define bMaskByte3 0xff000000 1046#define bMaskHWord 0xffff0000 1047#define bMaskLWord 0x0000ffff 1048#define bMaskDWord 0xffffffff 1049#define bMask12Bits 0xfff 1050#define bMaskH4Bits 0xf0000000 1051#define bMaskOFDM_D 0xffc00000 1052#define bMaskCCK 0x3f3f3f3f 1053 1054/* for PutRFRegsetting & GetRFRegSetting BitMask */ 1055#define bRFRegOffsetMask 0xfffff 1056 1057#define bEnable 0x1 /* Useless */ 1058#define bDisable 0x0 1059 1060#define LeftAntenna 0x0 /* Useless */ 1061#define RightAntenna 0x1 1062 1063#define tCheckTxStatus 500 /* 500ms Useless */ 1064#define tUpdateRxCounter 100 /* 100ms */ 1065 1066#define rateCCK 0 /* Useless */ 1067#define rateOFDM 1 1068#define rateHT 2 1069 1070/* define Register-End */ 1071#define bPMAC_End 0x1ff /* Useless */ 1072#define bFPGAPHY0_End 0x8ff 1073#define bFPGAPHY1_End 0x9ff 1074#define bCCKPHY0_End 0xaff 1075#define bOFDMPHY0_End 0xcff 1076#define bOFDMPHY1_End 0xdff 1077 1078#define bPMACControl 0x0 /* Useless */ 1079#define bWMACControl 0x1 1080#define bWNICControl 0x2 1081 1082#define PathA 0x0 /* Useless */ 1083#define PathB 0x1 1084#define PathC 0x2 1085#define PathD 0x3 1086 1087/*--------------------------Define Parameters-------------------------------*/ 1088 1089 1090#endif 1091