LXR linux/drivers/staging/rtl8712/rtl871x

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * Modifications for inclusion into the Linux staging tree are
  19 * Copyright(c) 2010 Larry Finger. All rights reserved.
  20 *
  21 * Contact information:
  22 * WLAN FAE <wlanfae@realtek.com>
  23 * Larry Finger <Larry.Finger@lwfinger.net>
  24 *
  25 ******************************************************************************/
  26#define _RTL871X_MP_C_
  27
  28#include "osdep_service.h"
  29#include "drv_types.h"
  30#include "rtl871x_mp_phy_regdef.h"
  31#include "rtl8712_cmd.h"
  32
  33static void _init_mp_priv_(struct mp_priv *pmp_priv)
  34{
  35        pmp_priv->mode = _LOOPBOOK_MODE_;
  36        pmp_priv->curr_ch = 1;
  37        pmp_priv->curr_modem = MIXED_PHY;
  38        pmp_priv->curr_rateidx = 0;
  39        pmp_priv->curr_txpoweridx = 0x14;
  40        pmp_priv->antenna_tx = ANTENNA_A;
  41        pmp_priv->antenna_rx = ANTENNA_AB;
  42        pmp_priv->check_mp_pkt = 0;
  43        pmp_priv->tx_pktcount = 0;
  44        pmp_priv->rx_pktcount = 0;
  45        pmp_priv->rx_crcerrpktcount = 0;
  46}
  47
  48static int init_mp_priv(struct mp_priv *pmp_priv)
  49{
  50        int i, res;
  51        struct mp_xmit_frame *pmp_xmitframe;
  52
  53        _init_mp_priv_(pmp_priv);
  54        _init_queue(&pmp_priv->free_mp_xmitqueue);
  55        pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  56        pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
  57                                sizeof(struct mp_xmit_frame) + 4,
  58                                GFP_ATOMIC);
  59        if (!pmp_priv->pallocated_mp_xmitframe_buf) {
  60                res = _FAIL;
  61                goto _exit_init_mp_priv;
  62        }
  63        pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
  64                         4 -
  65                         ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
  66        pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
  67        for (i = 0; i < NR_MP_XMITFRAME; i++) {
  68                INIT_LIST_HEAD(&(pmp_xmitframe->list));
  69                list_add_tail(&(pmp_xmitframe->list),
  70                                 &(pmp_priv->free_mp_xmitqueue.queue));
  71                pmp_xmitframe->pkt = NULL;
  72                pmp_xmitframe->frame_tag = MP_FRAMETAG;
  73                pmp_xmitframe->padapter = pmp_priv->papdater;
  74                pmp_xmitframe++;
  75        }
  76        pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
  77        res = _SUCCESS;
  78_exit_init_mp_priv:
  79        return res;
  80}
  81
  82static int free_mp_priv(struct mp_priv *pmp_priv)
  83{
  84        kfree(pmp_priv->pallocated_mp_xmitframe_buf);
  85        return 0;
  86}
  87
  88void mp871xinit(struct _adapter *padapter)
  89{
  90        struct mp_priv *pmppriv = &padapter->mppriv;
  91
  92        pmppriv->papdater = padapter;
  93        init_mp_priv(pmppriv);
  94}
  95
  96void mp871xdeinit(struct _adapter *padapter)
  97{
  98        struct mp_priv *pmppriv = &padapter->mppriv;
  99
 100        free_mp_priv(pmppriv);
 101}
 102
 103/*
 104 * Special for bb and rf reg read/write
 105 */
 106static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
 107{
 108        u32 cmd32 = 0, val32 = 0;
 109        u8 iocmd_class  = iocmd.cmdclass;
 110        u16 iocmd_value = iocmd.value;
 111        u8 iocmd_idx    = iocmd.index;
 112
 113        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
 114        if (r8712_fw_cmd(pAdapter, cmd32))
 115                r8712_fw_cmd_data(pAdapter, &val32, 1);
 116        else
 117                val32 = 0;
 118        return val32;
 119}
 120
 121static u8 fw_iocmd_write(struct _adapter *pAdapter,
 122                         struct IOCMD_STRUCT iocmd, u32 value)
 123{
 124        u32 cmd32 = 0;
 125        u8 iocmd_class  = iocmd.cmdclass;
 126        u32 iocmd_value = iocmd.value;
 127        u8 iocmd_idx    = iocmd.index;
 128
 129        r8712_fw_cmd_data(pAdapter, &value, 0);
 130        msleep(100);
 131        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
 132        return r8712_fw_cmd(pAdapter, cmd32);
 133}
 134
 135/* offset : 0X800~0XFFF */
 136u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
 137{
 138        u8 shift = offset & 0x0003;     /* 4 byte access */
 139        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 140        u32 bb_val = 0;
 141        struct IOCMD_STRUCT iocmd;
 142
 143        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 144        iocmd.value     = bb_addr;
 145        iocmd.index     = IOCMD_BB_READ_IDX;
 146        bb_val = fw_iocmd_read(pAdapter, iocmd);
 147        if (shift != 0) {
 148                u32 bb_val2 = 0;
 149
 150                bb_val >>= (shift * 8);
 151                iocmd.value += 4;
 152                bb_val2 = fw_iocmd_read(pAdapter, iocmd);
 153                bb_val2 <<= ((4 - shift) * 8);
 154                bb_val |= bb_val2;
 155        }
 156        return bb_val;
 157}
 158
 159/* offset : 0X800~0XFFF */
 160u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
 161{
 162        u8 shift = offset & 0x0003;     /* 4 byte access */
 163        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 164        struct IOCMD_STRUCT iocmd;
 165
 166        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 167        iocmd.value     = bb_addr;
 168        iocmd.index     = IOCMD_BB_WRITE_IDX;
 169        if (shift != 0) {
 170                u32 oldValue = 0;
 171                u32 newValue = value;
 172
 173                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 174                oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
 175                value = oldValue | (newValue << (shift * 8));
 176                if (!fw_iocmd_write(pAdapter, iocmd, value))
 177                        return false;
 178                iocmd.value += 4;
 179                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 180                oldValue &= (0xFFFFFFFF << (shift * 8));
 181                value = oldValue | (newValue >> ((4 - shift) * 8));
 182        }
 183        return fw_iocmd_write(pAdapter, iocmd, value);
 184}
 185
 186/* offset : 0x00 ~ 0xFF */
 187u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
 188{
 189        u16 rf_addr = (path << 8) | offset;
 190        struct IOCMD_STRUCT iocmd;
 191
 192        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 193        iocmd.value     = rf_addr;
 194        iocmd.index     = IOCMD_RF_READ_IDX;
 195        return fw_iocmd_read(pAdapter, iocmd);
 196}
 197
 198u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
 199{
 200        u16 rf_addr = (path << 8) | offset;
 201        struct IOCMD_STRUCT iocmd;
 202
 203        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 204        iocmd.value     = rf_addr;
 205        iocmd.index     = IOCMD_RF_WRIT_IDX;
 206        return fw_iocmd_write(pAdapter, iocmd, value);
 207}
 208
 209static u32 bitshift(u32 bitmask)
 210{
 211        u32 i;
 212
 213        for (i = 0; i <= 31; i++)
 214                if (((bitmask >> i) &  0x1) == 1)
 215                        break;
 216        return i;
 217}
 218
 219static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
 220{
 221        u32 org_value, bit_shift;
 222
 223        org_value = r8712_bb_reg_read(pAdapter, offset);
 224        bit_shift = bitshift(bitmask);
 225        return (org_value & bitmask) >> bit_shift;
 226}
 227
 228static u8 set_bb_reg(struct _adapter *pAdapter,
 229                     u16 offset,
 230                     u32 bitmask,
 231                     u32 value)
 232{
 233        u32 org_value, bit_shift, new_value;
 234
 235        if (bitmask != bMaskDWord) {
 236                org_value = r8712_bb_reg_read(pAdapter, offset);
 237                bit_shift = bitshift(bitmask);
 238                new_value = (org_value & (~bitmask)) | (value << bit_shift);
 239        } else {
 240                new_value = value;
 241        }
 242        return r8712_bb_reg_write(pAdapter, offset, new_value);
 243}
 244
 245static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
 246                      u32 bitmask)
 247{
 248        u32 org_value, bit_shift;
 249
 250        org_value = r8712_rf_reg_read(pAdapter, path, offset);
 251        bit_shift = bitshift(bitmask);
 252        return (org_value & bitmask) >> bit_shift;
 253}
 254
 255static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
 256              u32 value)
 257{
 258        u32 org_value, bit_shift, new_value;
 259
 260        if (bitmask != bMaskDWord) {
 261                org_value = r8712_rf_reg_read(pAdapter, path, offset);
 262                bit_shift = bitshift(bitmask);
 263                new_value = (org_value & (~bitmask)) | (value << bit_shift);
 264        } else {
 265                new_value = value;
 266        }
 267        return r8712_rf_reg_write(pAdapter, path, offset, new_value);
 268}
 269
 270/*
 271 * SetChannel
 272 * Description
 273 *      Use H2C command to change channel,
 274 *      not only modify rf register, but also other setting need to be done.
 275 */
 276void r8712_SetChannel(struct _adapter *pAdapter)
 277{
 278        struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
 279        struct cmd_obj *pcmd = NULL;
 280        struct SetChannel_parm *pparm = NULL;
 281        u16 code = GEN_CMD_CODE(_SetChannel);
 282
 283        pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
 284        if (!pcmd)
 285                return;
 286        pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
 287        if (!pparm) {
 288                kfree(pcmd);
 289                return;
 290        }
 291        pparm->curr_ch = pAdapter->mppriv.curr_ch;
 292        init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
 293        r8712_enqueue_cmd(pcmdpriv, pcmd);
 294}
 295
 296static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
 297{
 298        u16 TxAGC = 0;
 299
 300        TxAGC = TxPower;
 301        set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 302}
 303
 304static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
 305{
 306        u32 TxAGC = 0;
 307
 308        TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
 309                  TxPower);
 310        set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
 311        set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
 312        set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
 313        set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
 314        set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
 315        set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
 316}
 317
 318void r8712_SetTxPower(struct _adapter *pAdapter)
 319{
 320        u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
 321
 322        SetCCKTxPower(pAdapter, TxPower);
 323        SetOFDMTxPower(pAdapter, TxPower);
 324}
 325
 326void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
 327{
 328        u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
 329
 330        TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
 331        TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
 332        TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
 333        tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
 334        set_bb_reg(pAdapter, rFPGA0_TxGainStage,
 335                        (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
 336}
 337
 338void r8712_SetDataRate(struct _adapter *pAdapter)
 339{
 340        u8 path = RF_PATH_A;
 341        u8 offset = RF_SYN_G2;
 342        u32 value;
 343
 344        value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
 345        r8712_rf_reg_write(pAdapter, path, offset, value);
 346}
 347
 348void r8712_SwitchBandwidth(struct _adapter *pAdapter)
 349{
 350        /* 3 1.Set MAC register : BWOPMODE  bit2:1 20MhzBW */
 351        u8 regBwOpMode = 0;
 352        u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
 353
 354        regBwOpMode = r8712_read8(pAdapter, 0x10250203);
 355        if (Bandwidth == HT_CHANNEL_WIDTH_20)
 356                regBwOpMode |= BIT(2);
 357        else
 358                regBwOpMode &= ~(BIT(2));
 359        r8712_write8(pAdapter, 0x10250203, regBwOpMode);
 360        /* 3 2.Set PHY related register */
 361        switch (Bandwidth) {
 362        /* 20 MHz channel*/
 363        case HT_CHANNEL_WIDTH_20:
 364                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 365                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 366                /* Use PHY_REG.txt default value. Do not need to change.
 367                 * Correct the tx power for CCK rate in 40M.
 368                 * It is set in Tx descriptor for 8192x series
 369                 */
 370                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
 371                break;
 372        /* 40 MHz channel*/
 373        case HT_CHANNEL_WIDTH_40:
 374                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 375                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 376                /* Use PHY_REG.txt default value. Do not need to change.
 377                 * Correct the tx power for CCK rate in 40M.
 378                 * Set Control channel to upper or lower. These settings are
 379                 * required only for 40MHz
 380                 */
 381                set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
 382                           (HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
 383                set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
 384                           HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 385                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
 386                break;
 387        default:
 388                break;
 389        }
 390
 391        /* 3 3.Set RF related register */
 392        switch (Bandwidth) {
 393        case HT_CHANNEL_WIDTH_20:
 394                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 395                           BIT(10) | BIT(11), 0x01);
 396                break;
 397        case HT_CHANNEL_WIDTH_40:
 398                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 399                           BIT(10) | BIT(11), 0x00);
 400                break;
 401        default:
 402                break;
 403        }
 404}
 405/*------------------------------Define structure----------------------------*/
 406struct R_ANTENNA_SELECT_OFDM {
 407        u32     r_tx_antenna:4;
 408        u32     r_ant_l:4;
 409        u32     r_ant_non_ht:4;
 410        u32     r_ant_ht1:4;
 411        u32     r_ant_ht2:4;
 412        u32     r_ant_ht_s1:4;
 413        u32     r_ant_non_ht_s1:4;
 414        u32     OFDM_TXSC:2;
 415        u32     Reserved:2;
 416};
 417
 418struct R_ANTENNA_SELECT_CCK {
 419        u8      r_cckrx_enable_2:2;
 420        u8      r_cckrx_enable:2;
 421        u8      r_ccktx_enable:4;
 422};
 423
 424void r8712_SwitchAntenna(struct _adapter *pAdapter)
 425{
 426        u32     ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
 427        u8      ofdm_rx_ant_sel_val = 0;
 428        u8      cck_ant_select_val = 0;
 429        u32     cck_ant_sel_val = 0;
 430        struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
 431
 432        p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
 433
 434        switch (pAdapter->mppriv.antenna_tx) {
 435        case ANTENNA_A:
 436                /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
 437                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 438                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 439                ofdm_tx_en_val = 0x3;
 440                ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
 441                p_cck_txrx->r_ccktx_enable = 0x8;
 442                break;
 443        case ANTENNA_B:
 444                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 445                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 446                ofdm_tx_en_val = 0x3;
 447                ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
 448                p_cck_txrx->r_ccktx_enable = 0x4;
 449                break;
 450        case ANTENNA_AB:        /* For 8192S */
 451                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 452                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 453                ofdm_tx_en_val = 0x3;
 454                ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
 455                p_cck_txrx->r_ccktx_enable = 0xC;
 456                break;
 457        default:
 458                break;
 459        }
 460        /*OFDM Tx*/
 461        set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
 462        /*OFDM Tx*/
 463        set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
 464        switch (pAdapter->mppriv.antenna_rx) {
 465        case ANTENNA_A:
 466                ofdm_rx_ant_sel_val = 0x1;      /* A */
 467                p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
 468                p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
 469                break;
 470        case ANTENNA_B:
 471                ofdm_rx_ant_sel_val = 0x2;      /* B */
 472                p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
 473                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
 474                break;
 475        case ANTENNA_AB:
 476                ofdm_rx_ant_sel_val = 0x3; /* AB */
 477                p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
 478                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
 479                break;
 480        default:
 481                break;
 482        }
 483        /*OFDM Rx*/
 484        set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
 485                   ofdm_rx_ant_sel_val);
 486        /*OFDM Rx*/
 487        set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
 488                   ofdm_rx_ant_sel_val);
 489
 490        cck_ant_sel_val = cck_ant_select_val;
 491        /*CCK TxRx*/
 492        set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
 493}
 494
 495static void TriggerRFThermalMeter(struct _adapter *pAdapter)
 496{
 497        /* 0x24: RF Reg[6:5] */
 498        set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
 499}
 500
 501static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
 502{
 503        /* 0x24: RF Reg[4:0] */
 504        return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
 505}
 506
 507void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
 508{
 509        TriggerRFThermalMeter(pAdapter);
 510        msleep(1000);
 511        *value = ReadRFThermalMeter(pAdapter);
 512}
 513
 514void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
 515{
 516        if (bStart) { /* Start Single Carrier. */
 517                /* 1. if OFDM block on? */
 518                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 519                        /*set OFDM block on*/
 520                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 521                /* 2. set CCK test mode off, set to CCK normal mode */
 522                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 523                /* 3. turn on scramble setting */
 524                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 525                /* 4. Turn On Single Carrier Tx and off the other test modes. */
 526                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 527                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 528                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 529        } else { /* Stop Single Carrier.*/
 530                /* Turn off all test modes.*/
 531                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 532                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 533                           bDisable);
 534                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 535                msleep(20);
 536                /*BB Reset*/
 537                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 538                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 539        }
 540}
 541
 542void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
 543{
 544        u8 rfPath;
 545
 546        switch (pAdapter->mppriv.antenna_tx) {
 547        case ANTENNA_B:
 548                rfPath = RF_PATH_B;
 549                break;
 550        case ANTENNA_A:
 551        default:
 552                rfPath = RF_PATH_A;
 553                break;
 554        }
 555        if (bStart) { /* Start Single Tone.*/
 556                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
 557                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
 558                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 559                           0xd4000);
 560                msleep(100);
 561                /* PAD all on.*/
 562                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
 563                msleep(100);
 564        } else { /* Stop Single Tone.*/
 565                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 566                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 567                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 568                           0x54000);
 569                msleep(100);
 570                /* PAD all on.*/
 571                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
 572                msleep(100);
 573        }
 574}
 575
 576void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
 577{
 578        if (bStart) { /* Start Carrier Suppression.*/
 579                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 580                        /* 1. if CCK block on? */
 581                        if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 582                                /*set CCK block on*/
 583                                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
 584                                           bEnable);
 585                        }
 586                        /* Turn Off All Test Mode */
 587                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
 588                                   bDisable);
 589                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 590                                   bDisable);
 591                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
 592                                   bDisable);
 593                        /*transmit mode*/
 594                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 595                        /*turn off scramble setting*/
 596                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 597                                   bDisable);
 598                        /*Set CCK Tx Test Rate*/
 599                        /*Set FTxRate to 1Mbps*/
 600                        set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
 601                }
 602        } else { /* Stop Carrier Suppression. */
 603                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 604                        /*normal mode*/
 605                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 606                        /*turn on scramble setting*/
 607                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 608                                   bEnable);
 609                        /*BB Reset*/
 610                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 611                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 612                }
 613        }
 614}
 615
 616static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
 617{
 618        u32 cckrate;
 619
 620        if (bStart) {
 621                /* 1. if CCK block on? */
 622                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 623                        /*set CCK block on*/
 624                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 625                }
 626                /* Turn Off All Test Mode */
 627                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 628                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 629                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 630                /*Set CCK Tx Test Rate*/
 631                cckrate  = pAdapter->mppriv.curr_rateidx;
 632                set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 633                /*transmit mode*/
 634                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 635                /*turn on scramble setting*/
 636                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 637        } else {
 638                /*normal mode*/
 639                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 640                /*turn on scramble setting*/
 641                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 642                /*BB Reset*/
 643                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 644                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 645        }
 646} /* mpt_StartCckContTx */
 647
 648static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
 649{
 650        if (bStart) {
 651                /* 1. if OFDM block on? */
 652                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
 653                        /*set OFDM block on*/
 654                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 655                }
 656                /* 2. set CCK test mode off, set to CCK normal mode*/
 657                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 658                /* 3. turn on scramble setting */
 659                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 660                /* 4. Turn On Continue Tx and turn off the other test modes.*/
 661                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 662                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 663                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 664        } else {
 665                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 666                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 667                           bDisable);
 668                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 669                msleep(20);
 670                /*BB Reset*/
 671                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 672                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 673        }
 674} /* mpt_StartOfdmContTx */
 675
 676void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
 677{
 678        /* ADC turn off [bit24-21] adc port0 ~ port1 */
 679        if (bStart) {
 680                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 681                                   r8712_bb_reg_read(pAdapter,
 682                                   rRx_Wait_CCCA) & 0xFE1FFFFF);
 683                msleep(100);
 684        }
 685        if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
 686                SetCCKContinuousTx(pAdapter, bStart);
 687        else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
 688                 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
 689                SetOFDMContinuousTx(pAdapter, bStart);
 690        /* ADC turn on [bit24-21] adc port0 ~ port1 */
 691        if (!bStart)
 692                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 693                                   r8712_bb_reg_read(pAdapter,
 694                                   rRx_Wait_CCCA) | 0x01E00000);
 695}
 696
 697void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
 698{
 699        u32 i, phyrx_set = 0;
 700
 701        for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
 702                phyrx_set = 0;
 703                phyrx_set |= (i << 28);         /*select*/
 704                phyrx_set |= 0x08000000;        /* set counter to zero*/
 705                r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 706        }
 707}
 708
 709static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
 710{
 711        /*selection*/
 712        u32 phyrx_set = 0, count = 0;
 713        u32 SelectBit;
 714
 715        SelectBit = selbit << 28;
 716        phyrx_set |= (SelectBit & 0xF0000000);
 717        r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 718        /*Read packet count*/
 719        count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
 720        return count;
 721}
 722
 723u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
 724{
 725        u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
 726
 727        OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
 728        CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
 729        HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
 730        return OFDM_cnt + CCK_cnt + HT_cnt;
 731}
 732
 733u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
 734{
 735        u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
 736
 737        OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
 738        CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
 739        HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
 740        return OFDM_cnt + CCK_cnt + HT_cnt;
 741}
 742