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32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35#include "mlx5_ifc_fpga.h"
36
37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
76};
77
78enum {
79 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
80 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
81 MLX5_CMD_OP_INIT_HCA = 0x102,
82 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
83 MLX5_CMD_OP_ENABLE_HCA = 0x104,
84 MLX5_CMD_OP_DISABLE_HCA = 0x105,
85 MLX5_CMD_OP_QUERY_PAGES = 0x107,
86 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
87 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
88 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
89 MLX5_CMD_OP_SET_ISSI = 0x10b,
90 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
91 MLX5_CMD_OP_CREATE_MKEY = 0x200,
92 MLX5_CMD_OP_QUERY_MKEY = 0x201,
93 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
94 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
95 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
96 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
97 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
98 MLX5_CMD_OP_CREATE_EQ = 0x301,
99 MLX5_CMD_OP_DESTROY_EQ = 0x302,
100 MLX5_CMD_OP_QUERY_EQ = 0x303,
101 MLX5_CMD_OP_GEN_EQE = 0x304,
102 MLX5_CMD_OP_CREATE_CQ = 0x400,
103 MLX5_CMD_OP_DESTROY_CQ = 0x401,
104 MLX5_CMD_OP_QUERY_CQ = 0x402,
105 MLX5_CMD_OP_MODIFY_CQ = 0x403,
106 MLX5_CMD_OP_CREATE_QP = 0x500,
107 MLX5_CMD_OP_DESTROY_QP = 0x501,
108 MLX5_CMD_OP_RST2INIT_QP = 0x502,
109 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
110 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
111 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
112 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
113 MLX5_CMD_OP_2ERR_QP = 0x507,
114 MLX5_CMD_OP_2RST_QP = 0x50a,
115 MLX5_CMD_OP_QUERY_QP = 0x50b,
116 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
117 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
118 MLX5_CMD_OP_CREATE_PSV = 0x600,
119 MLX5_CMD_OP_DESTROY_PSV = 0x601,
120 MLX5_CMD_OP_CREATE_SRQ = 0x700,
121 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
122 MLX5_CMD_OP_QUERY_SRQ = 0x702,
123 MLX5_CMD_OP_ARM_RQ = 0x703,
124 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
125 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
126 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
127 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
128 MLX5_CMD_OP_CREATE_DCT = 0x710,
129 MLX5_CMD_OP_DESTROY_DCT = 0x711,
130 MLX5_CMD_OP_DRAIN_DCT = 0x712,
131 MLX5_CMD_OP_QUERY_DCT = 0x713,
132 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
133 MLX5_CMD_OP_CREATE_XRQ = 0x717,
134 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
135 MLX5_CMD_OP_QUERY_XRQ = 0x719,
136 MLX5_CMD_OP_ARM_XRQ = 0x71a,
137 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
138 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
139 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
140 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
141 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
142 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
143 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
144 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
146 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
148 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
149 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
154 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
162 MLX5_CMD_OP_ALLOC_PD = 0x800,
163 MLX5_CMD_OP_DEALLOC_PD = 0x801,
164 MLX5_CMD_OP_ALLOC_UAR = 0x802,
165 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
167 MLX5_CMD_OP_ACCESS_REG = 0x805,
168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
171 MLX5_CMD_OP_MAD_IFC = 0x50d,
172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
174 MLX5_CMD_OP_NOP = 0x80d,
175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
177 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
178 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
179 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
180 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
181 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
182 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
183 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
184 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
185 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
186 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
187 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
188 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
189 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
190 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
191 MLX5_CMD_OP_CREATE_LAG = 0x840,
192 MLX5_CMD_OP_MODIFY_LAG = 0x841,
193 MLX5_CMD_OP_QUERY_LAG = 0x842,
194 MLX5_CMD_OP_DESTROY_LAG = 0x843,
195 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
196 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
197 MLX5_CMD_OP_CREATE_TIR = 0x900,
198 MLX5_CMD_OP_MODIFY_TIR = 0x901,
199 MLX5_CMD_OP_DESTROY_TIR = 0x902,
200 MLX5_CMD_OP_QUERY_TIR = 0x903,
201 MLX5_CMD_OP_CREATE_SQ = 0x904,
202 MLX5_CMD_OP_MODIFY_SQ = 0x905,
203 MLX5_CMD_OP_DESTROY_SQ = 0x906,
204 MLX5_CMD_OP_QUERY_SQ = 0x907,
205 MLX5_CMD_OP_CREATE_RQ = 0x908,
206 MLX5_CMD_OP_MODIFY_RQ = 0x909,
207 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
208 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
209 MLX5_CMD_OP_QUERY_RQ = 0x90b,
210 MLX5_CMD_OP_CREATE_RMP = 0x90c,
211 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
212 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
213 MLX5_CMD_OP_QUERY_RMP = 0x90f,
214 MLX5_CMD_OP_CREATE_TIS = 0x912,
215 MLX5_CMD_OP_MODIFY_TIS = 0x913,
216 MLX5_CMD_OP_DESTROY_TIS = 0x914,
217 MLX5_CMD_OP_QUERY_TIS = 0x915,
218 MLX5_CMD_OP_CREATE_RQT = 0x916,
219 MLX5_CMD_OP_MODIFY_RQT = 0x917,
220 MLX5_CMD_OP_DESTROY_RQT = 0x918,
221 MLX5_CMD_OP_QUERY_RQT = 0x919,
222 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
223 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
224 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
225 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
226 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
227 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
228 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
229 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
230 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
231 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
232 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
233 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
234 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
235 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
236 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
237 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
238 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
239 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
240 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
241 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
242 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
243 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
244 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
245 MLX5_CMD_OP_MAX
246};
247
248struct mlx5_ifc_flow_table_fields_supported_bits {
249 u8 outer_dmac[0x1];
250 u8 outer_smac[0x1];
251 u8 outer_ether_type[0x1];
252 u8 outer_ip_version[0x1];
253 u8 outer_first_prio[0x1];
254 u8 outer_first_cfi[0x1];
255 u8 outer_first_vid[0x1];
256 u8 outer_ipv4_ttl[0x1];
257 u8 outer_second_prio[0x1];
258 u8 outer_second_cfi[0x1];
259 u8 outer_second_vid[0x1];
260 u8 reserved_at_b[0x1];
261 u8 outer_sip[0x1];
262 u8 outer_dip[0x1];
263 u8 outer_frag[0x1];
264 u8 outer_ip_protocol[0x1];
265 u8 outer_ip_ecn[0x1];
266 u8 outer_ip_dscp[0x1];
267 u8 outer_udp_sport[0x1];
268 u8 outer_udp_dport[0x1];
269 u8 outer_tcp_sport[0x1];
270 u8 outer_tcp_dport[0x1];
271 u8 outer_tcp_flags[0x1];
272 u8 outer_gre_protocol[0x1];
273 u8 outer_gre_key[0x1];
274 u8 outer_vxlan_vni[0x1];
275 u8 reserved_at_1a[0x5];
276 u8 source_eswitch_port[0x1];
277
278 u8 inner_dmac[0x1];
279 u8 inner_smac[0x1];
280 u8 inner_ether_type[0x1];
281 u8 inner_ip_version[0x1];
282 u8 inner_first_prio[0x1];
283 u8 inner_first_cfi[0x1];
284 u8 inner_first_vid[0x1];
285 u8 reserved_at_27[0x1];
286 u8 inner_second_prio[0x1];
287 u8 inner_second_cfi[0x1];
288 u8 inner_second_vid[0x1];
289 u8 reserved_at_2b[0x1];
290 u8 inner_sip[0x1];
291 u8 inner_dip[0x1];
292 u8 inner_frag[0x1];
293 u8 inner_ip_protocol[0x1];
294 u8 inner_ip_ecn[0x1];
295 u8 inner_ip_dscp[0x1];
296 u8 inner_udp_sport[0x1];
297 u8 inner_udp_dport[0x1];
298 u8 inner_tcp_sport[0x1];
299 u8 inner_tcp_dport[0x1];
300 u8 inner_tcp_flags[0x1];
301 u8 reserved_at_37[0x9];
302
303 u8 reserved_at_40[0x5];
304 u8 outer_first_mpls_over_udp[0x4];
305 u8 outer_first_mpls_over_gre[0x4];
306 u8 inner_first_mpls[0x4];
307 u8 outer_first_mpls[0x4];
308 u8 reserved_at_55[0x2];
309 u8 outer_esp_spi[0x1];
310 u8 reserved_at_58[0x2];
311 u8 bth_dst_qp[0x1];
312
313 u8 reserved_at_5b[0x25];
314};
315
316struct mlx5_ifc_flow_table_prop_layout_bits {
317 u8 ft_support[0x1];
318 u8 reserved_at_1[0x1];
319 u8 flow_counter[0x1];
320 u8 flow_modify_en[0x1];
321 u8 modify_root[0x1];
322 u8 identified_miss_table_mode[0x1];
323 u8 flow_table_modify[0x1];
324 u8 encap[0x1];
325 u8 decap[0x1];
326 u8 reserved_at_9[0x1];
327 u8 pop_vlan[0x1];
328 u8 push_vlan[0x1];
329 u8 reserved_at_c[0x14];
330
331 u8 reserved_at_20[0x2];
332 u8 log_max_ft_size[0x6];
333 u8 log_max_modify_header_context[0x8];
334 u8 max_modify_header_actions[0x8];
335 u8 max_ft_level[0x8];
336
337 u8 reserved_at_40[0x20];
338
339 u8 reserved_at_60[0x18];
340 u8 log_max_ft_num[0x8];
341
342 u8 reserved_at_80[0x18];
343 u8 log_max_destination[0x8];
344
345 u8 log_max_flow_counter[0x8];
346 u8 reserved_at_a8[0x10];
347 u8 log_max_flow[0x8];
348
349 u8 reserved_at_c0[0x40];
350
351 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
352
353 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
354};
355
356struct mlx5_ifc_odp_per_transport_service_cap_bits {
357 u8 send[0x1];
358 u8 receive[0x1];
359 u8 write[0x1];
360 u8 read[0x1];
361 u8 atomic[0x1];
362 u8 srq_receive[0x1];
363 u8 reserved_at_6[0x1a];
364};
365
366struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
367 u8 smac_47_16[0x20];
368
369 u8 smac_15_0[0x10];
370 u8 ethertype[0x10];
371
372 u8 dmac_47_16[0x20];
373
374 u8 dmac_15_0[0x10];
375 u8 first_prio[0x3];
376 u8 first_cfi[0x1];
377 u8 first_vid[0xc];
378
379 u8 ip_protocol[0x8];
380 u8 ip_dscp[0x6];
381 u8 ip_ecn[0x2];
382 u8 cvlan_tag[0x1];
383 u8 svlan_tag[0x1];
384 u8 frag[0x1];
385 u8 ip_version[0x4];
386 u8 tcp_flags[0x9];
387
388 u8 tcp_sport[0x10];
389 u8 tcp_dport[0x10];
390
391 u8 reserved_at_c0[0x18];
392 u8 ttl_hoplimit[0x8];
393
394 u8 udp_sport[0x10];
395 u8 udp_dport[0x10];
396
397 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
398
399 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
400};
401
402struct mlx5_ifc_fte_match_set_misc_bits {
403 u8 reserved_at_0[0x8];
404 u8 source_sqn[0x18];
405
406 u8 source_eswitch_owner_vhca_id[0x10];
407 u8 source_port[0x10];
408
409 u8 outer_second_prio[0x3];
410 u8 outer_second_cfi[0x1];
411 u8 outer_second_vid[0xc];
412 u8 inner_second_prio[0x3];
413 u8 inner_second_cfi[0x1];
414 u8 inner_second_vid[0xc];
415
416 u8 outer_second_cvlan_tag[0x1];
417 u8 inner_second_cvlan_tag[0x1];
418 u8 outer_second_svlan_tag[0x1];
419 u8 inner_second_svlan_tag[0x1];
420 u8 reserved_at_64[0xc];
421 u8 gre_protocol[0x10];
422
423 u8 gre_key_h[0x18];
424 u8 gre_key_l[0x8];
425
426 u8 vxlan_vni[0x18];
427 u8 reserved_at_b8[0x8];
428
429 u8 reserved_at_c0[0x20];
430
431 u8 reserved_at_e0[0xc];
432 u8 outer_ipv6_flow_label[0x14];
433
434 u8 reserved_at_100[0xc];
435 u8 inner_ipv6_flow_label[0x14];
436
437 u8 reserved_at_120[0x28];
438 u8 bth_dst_qp[0x18];
439 u8 reserved_at_160[0x20];
440 u8 outer_esp_spi[0x20];
441 u8 reserved_at_1a0[0x60];
442};
443
444struct mlx5_ifc_fte_match_mpls_bits {
445 u8 mpls_label[0x14];
446 u8 mpls_exp[0x3];
447 u8 mpls_s_bos[0x1];
448 u8 mpls_ttl[0x8];
449};
450
451struct mlx5_ifc_fte_match_set_misc2_bits {
452 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
453
454 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
455
456 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
457
458 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
459
460 u8 reserved_at_80[0x100];
461
462 u8 metadata_reg_a[0x20];
463
464 u8 reserved_at_1a0[0x60];
465};
466
467struct mlx5_ifc_cmd_pas_bits {
468 u8 pa_h[0x20];
469
470 u8 pa_l[0x14];
471 u8 reserved_at_34[0xc];
472};
473
474struct mlx5_ifc_uint64_bits {
475 u8 hi[0x20];
476
477 u8 lo[0x20];
478};
479
480enum {
481 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
482 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
483 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
484 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
485 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
486 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
487 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
488 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
489 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
490 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
491};
492
493struct mlx5_ifc_ads_bits {
494 u8 fl[0x1];
495 u8 free_ar[0x1];
496 u8 reserved_at_2[0xe];
497 u8 pkey_index[0x10];
498
499 u8 reserved_at_20[0x8];
500 u8 grh[0x1];
501 u8 mlid[0x7];
502 u8 rlid[0x10];
503
504 u8 ack_timeout[0x5];
505 u8 reserved_at_45[0x3];
506 u8 src_addr_index[0x8];
507 u8 reserved_at_50[0x4];
508 u8 stat_rate[0x4];
509 u8 hop_limit[0x8];
510
511 u8 reserved_at_60[0x4];
512 u8 tclass[0x8];
513 u8 flow_label[0x14];
514
515 u8 rgid_rip[16][0x8];
516
517 u8 reserved_at_100[0x4];
518 u8 f_dscp[0x1];
519 u8 f_ecn[0x1];
520 u8 reserved_at_106[0x1];
521 u8 f_eth_prio[0x1];
522 u8 ecn[0x2];
523 u8 dscp[0x6];
524 u8 udp_sport[0x10];
525
526 u8 dei_cfi[0x1];
527 u8 eth_prio[0x3];
528 u8 sl[0x4];
529 u8 vhca_port_num[0x8];
530 u8 rmac_47_32[0x10];
531
532 u8 rmac_31_0[0x20];
533};
534
535struct mlx5_ifc_flow_table_nic_cap_bits {
536 u8 nic_rx_multi_path_tirs[0x1];
537 u8 nic_rx_multi_path_tirs_fts[0x1];
538 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
539 u8 reserved_at_3[0x1fd];
540
541 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
542
543 u8 reserved_at_400[0x200];
544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
546
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
548
549 u8 reserved_at_a00[0x200];
550
551 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
552
553 u8 reserved_at_e00[0x7200];
554};
555
556struct mlx5_ifc_flow_table_eswitch_cap_bits {
557 u8 reserved_at_0[0x1c];
558 u8 fdb_multi_path_to_table[0x1];
559 u8 reserved_at_1d[0x1e3];
560
561 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
562
563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
564
565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
566
567 u8 reserved_at_800[0x7800];
568};
569
570struct mlx5_ifc_e_switch_cap_bits {
571 u8 vport_svlan_strip[0x1];
572 u8 vport_cvlan_strip[0x1];
573 u8 vport_svlan_insert[0x1];
574 u8 vport_cvlan_insert_if_not_exist[0x1];
575 u8 vport_cvlan_insert_overwrite[0x1];
576 u8 reserved_at_5[0x18];
577 u8 merged_eswitch[0x1];
578 u8 nic_vport_node_guid_modify[0x1];
579 u8 nic_vport_port_guid_modify[0x1];
580
581 u8 vxlan_encap_decap[0x1];
582 u8 nvgre_encap_decap[0x1];
583 u8 reserved_at_22[0x9];
584 u8 log_max_encap_headers[0x5];
585 u8 reserved_2b[0x6];
586 u8 max_encap_header_size[0xa];
587
588 u8 reserved_40[0x7c0];
589
590};
591
592struct mlx5_ifc_qos_cap_bits {
593 u8 packet_pacing[0x1];
594 u8 esw_scheduling[0x1];
595 u8 esw_bw_share[0x1];
596 u8 esw_rate_limit[0x1];
597 u8 reserved_at_4[0x1];
598 u8 packet_pacing_burst_bound[0x1];
599 u8 packet_pacing_typical_size[0x1];
600 u8 reserved_at_7[0x19];
601
602 u8 reserved_at_20[0x20];
603
604 u8 packet_pacing_max_rate[0x20];
605
606 u8 packet_pacing_min_rate[0x20];
607
608 u8 reserved_at_80[0x10];
609 u8 packet_pacing_rate_table_size[0x10];
610
611 u8 esw_element_type[0x10];
612 u8 esw_tsar_type[0x10];
613
614 u8 reserved_at_c0[0x10];
615 u8 max_qos_para_vport[0x10];
616
617 u8 max_tsar_bw_share[0x20];
618
619 u8 reserved_at_100[0x700];
620};
621
622struct mlx5_ifc_debug_cap_bits {
623 u8 reserved_at_0[0x20];
624
625 u8 reserved_at_20[0x2];
626 u8 stall_detect[0x1];
627 u8 reserved_at_23[0x1d];
628
629 u8 reserved_at_40[0x7c0];
630};
631
632struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
633 u8 csum_cap[0x1];
634 u8 vlan_cap[0x1];
635 u8 lro_cap[0x1];
636 u8 lro_psh_flag[0x1];
637 u8 lro_time_stamp[0x1];
638 u8 reserved_at_5[0x2];
639 u8 wqe_vlan_insert[0x1];
640 u8 self_lb_en_modifiable[0x1];
641 u8 reserved_at_9[0x2];
642 u8 max_lso_cap[0x5];
643 u8 multi_pkt_send_wqe[0x2];
644 u8 wqe_inline_mode[0x2];
645 u8 rss_ind_tbl_cap[0x4];
646 u8 reg_umr_sq[0x1];
647 u8 scatter_fcs[0x1];
648 u8 enhanced_multi_pkt_send_wqe[0x1];
649 u8 tunnel_lso_const_out_ip_id[0x1];
650 u8 reserved_at_1c[0x2];
651 u8 tunnel_stateless_gre[0x1];
652 u8 tunnel_stateless_vxlan[0x1];
653
654 u8 swp[0x1];
655 u8 swp_csum[0x1];
656 u8 swp_lso[0x1];
657 u8 reserved_at_23[0xd];
658 u8 max_vxlan_udp_ports[0x8];
659 u8 reserved_at_38[0x6];
660 u8 max_geneve_opt_len[0x1];
661 u8 tunnel_stateless_geneve_rx[0x1];
662
663 u8 reserved_at_40[0x10];
664 u8 lro_min_mss_size[0x10];
665
666 u8 reserved_at_60[0x120];
667
668 u8 lro_timer_supported_periods[4][0x20];
669
670 u8 reserved_at_200[0x600];
671};
672
673struct mlx5_ifc_roce_cap_bits {
674 u8 roce_apm[0x1];
675 u8 reserved_at_1[0x1f];
676
677 u8 reserved_at_20[0x60];
678
679 u8 reserved_at_80[0xc];
680 u8 l3_type[0x4];
681 u8 reserved_at_90[0x8];
682 u8 roce_version[0x8];
683
684 u8 reserved_at_a0[0x10];
685 u8 r_roce_dest_udp_port[0x10];
686
687 u8 r_roce_max_src_udp_port[0x10];
688 u8 r_roce_min_src_udp_port[0x10];
689
690 u8 reserved_at_e0[0x10];
691 u8 roce_address_table_size[0x10];
692
693 u8 reserved_at_100[0x700];
694};
695
696struct mlx5_ifc_device_mem_cap_bits {
697 u8 memic[0x1];
698 u8 reserved_at_1[0x1f];
699
700 u8 reserved_at_20[0xb];
701 u8 log_min_memic_alloc_size[0x5];
702 u8 reserved_at_30[0x8];
703 u8 log_max_memic_addr_alignment[0x8];
704
705 u8 memic_bar_start_addr[0x40];
706
707 u8 memic_bar_size[0x20];
708
709 u8 max_memic_size[0x20];
710
711 u8 reserved_at_c0[0x740];
712};
713
714enum {
715 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
716 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
717 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
718 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
719 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
720 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
721 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
722 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
723 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
724};
725
726enum {
727 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
728 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
729 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
730 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
731 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
732 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
733 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
734 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
735 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
736};
737
738struct mlx5_ifc_atomic_caps_bits {
739 u8 reserved_at_0[0x40];
740
741 u8 atomic_req_8B_endianness_mode[0x2];
742 u8 reserved_at_42[0x4];
743 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
744
745 u8 reserved_at_47[0x19];
746
747 u8 reserved_at_60[0x20];
748
749 u8 reserved_at_80[0x10];
750 u8 atomic_operations[0x10];
751
752 u8 reserved_at_a0[0x10];
753 u8 atomic_size_qp[0x10];
754
755 u8 reserved_at_c0[0x10];
756 u8 atomic_size_dc[0x10];
757
758 u8 reserved_at_e0[0x720];
759};
760
761struct mlx5_ifc_odp_cap_bits {
762 u8 reserved_at_0[0x40];
763
764 u8 sig[0x1];
765 u8 reserved_at_41[0x1f];
766
767 u8 reserved_at_60[0x20];
768
769 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
770
771 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
772
773 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
774
775 u8 reserved_at_e0[0x720];
776};
777
778struct mlx5_ifc_calc_op {
779 u8 reserved_at_0[0x10];
780 u8 reserved_at_10[0x9];
781 u8 op_swap_endianness[0x1];
782 u8 op_min[0x1];
783 u8 op_xor[0x1];
784 u8 op_or[0x1];
785 u8 op_and[0x1];
786 u8 op_max[0x1];
787 u8 op_add[0x1];
788};
789
790struct mlx5_ifc_vector_calc_cap_bits {
791 u8 calc_matrix[0x1];
792 u8 reserved_at_1[0x1f];
793 u8 reserved_at_20[0x8];
794 u8 max_vec_count[0x8];
795 u8 reserved_at_30[0xd];
796 u8 max_chunk_size[0x3];
797 struct mlx5_ifc_calc_op calc0;
798 struct mlx5_ifc_calc_op calc1;
799 struct mlx5_ifc_calc_op calc2;
800 struct mlx5_ifc_calc_op calc3;
801
802 u8 reserved_at_e0[0x720];
803};
804
805enum {
806 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
807 MLX5_WQ_TYPE_CYCLIC = 0x1,
808 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
809 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
810};
811
812enum {
813 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
814 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
815};
816
817enum {
818 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
819 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
820 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
821 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
822 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
823};
824
825enum {
826 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
827 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
828 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
829 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
830 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
831 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
832};
833
834enum {
835 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
836 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
837};
838
839enum {
840 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
841 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
842 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
843};
844
845enum {
846 MLX5_CAP_PORT_TYPE_IB = 0x0,
847 MLX5_CAP_PORT_TYPE_ETH = 0x1,
848};
849
850enum {
851 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
852 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
853 MLX5_CAP_UMR_FENCE_NONE = 0x2,
854};
855
856struct mlx5_ifc_cmd_hca_cap_bits {
857 u8 reserved_at_0[0x30];
858 u8 vhca_id[0x10];
859
860 u8 reserved_at_40[0x40];
861
862 u8 log_max_srq_sz[0x8];
863 u8 log_max_qp_sz[0x8];
864 u8 reserved_at_90[0xb];
865 u8 log_max_qp[0x5];
866
867 u8 reserved_at_a0[0xb];
868 u8 log_max_srq[0x5];
869 u8 reserved_at_b0[0x10];
870
871 u8 reserved_at_c0[0x8];
872 u8 log_max_cq_sz[0x8];
873 u8 reserved_at_d0[0xb];
874 u8 log_max_cq[0x5];
875
876 u8 log_max_eq_sz[0x8];
877 u8 reserved_at_e8[0x2];
878 u8 log_max_mkey[0x6];
879 u8 reserved_at_f0[0xb];
880 u8 fast_teardown[0x1];
881 u8 log_max_eq[0x4];
882
883 u8 max_indirection[0x8];
884 u8 fixed_buffer_size[0x1];
885 u8 log_max_mrw_sz[0x7];
886 u8 force_teardown[0x1];
887 u8 reserved_at_111[0x1];
888 u8 log_max_bsf_list_size[0x6];
889 u8 umr_extended_translation_offset[0x1];
890 u8 null_mkey[0x1];
891 u8 log_max_klm_list_size[0x6];
892
893 u8 reserved_at_120[0xa];
894 u8 log_max_ra_req_dc[0x6];
895 u8 reserved_at_130[0xa];
896 u8 log_max_ra_res_dc[0x6];
897
898 u8 reserved_at_140[0xa];
899 u8 log_max_ra_req_qp[0x6];
900 u8 reserved_at_150[0xa];
901 u8 log_max_ra_res_qp[0x6];
902
903 u8 end_pad[0x1];
904 u8 cc_query_allowed[0x1];
905 u8 cc_modify_allowed[0x1];
906 u8 start_pad[0x1];
907 u8 cache_line_128byte[0x1];
908 u8 reserved_at_165[0xa];
909 u8 qcam_reg[0x1];
910 u8 gid_table_size[0x10];
911
912 u8 out_of_seq_cnt[0x1];
913 u8 vport_counters[0x1];
914 u8 retransmission_q_counters[0x1];
915 u8 debug[0x1];
916 u8 modify_rq_counter_set_id[0x1];
917 u8 rq_delay_drop[0x1];
918 u8 max_qp_cnt[0xa];
919 u8 pkey_table_size[0x10];
920
921 u8 vport_group_manager[0x1];
922 u8 vhca_group_manager[0x1];
923 u8 ib_virt[0x1];
924 u8 eth_virt[0x1];
925 u8 vnic_env_queue_counters[0x1];
926 u8 ets[0x1];
927 u8 nic_flow_table[0x1];
928 u8 eswitch_manager[0x1];
929 u8 device_memory[0x1];
930 u8 mcam_reg[0x1];
931 u8 pcam_reg[0x1];
932 u8 local_ca_ack_delay[0x5];
933 u8 port_module_event[0x1];
934 u8 enhanced_error_q_counters[0x1];
935 u8 ports_check[0x1];
936 u8 reserved_at_1b3[0x1];
937 u8 disable_link_up[0x1];
938 u8 beacon_led[0x1];
939 u8 port_type[0x2];
940 u8 num_ports[0x8];
941
942 u8 reserved_at_1c0[0x1];
943 u8 pps[0x1];
944 u8 pps_modify[0x1];
945 u8 log_max_msg[0x5];
946 u8 reserved_at_1c8[0x4];
947 u8 max_tc[0x4];
948 u8 temp_warn_event[0x1];
949 u8 dcbx[0x1];
950 u8 general_notification_event[0x1];
951 u8 reserved_at_1d3[0x2];
952 u8 fpga[0x1];
953 u8 rol_s[0x1];
954 u8 rol_g[0x1];
955 u8 reserved_at_1d8[0x1];
956 u8 wol_s[0x1];
957 u8 wol_g[0x1];
958 u8 wol_a[0x1];
959 u8 wol_b[0x1];
960 u8 wol_m[0x1];
961 u8 wol_u[0x1];
962 u8 wol_p[0x1];
963
964 u8 stat_rate_support[0x10];
965 u8 reserved_at_1f0[0xc];
966 u8 cqe_version[0x4];
967
968 u8 compact_address_vector[0x1];
969 u8 striding_rq[0x1];
970 u8 reserved_at_202[0x1];
971 u8 ipoib_enhanced_offloads[0x1];
972 u8 ipoib_basic_offloads[0x1];
973 u8 reserved_at_205[0x1];
974 u8 repeated_block_disabled[0x1];
975 u8 umr_modify_entity_size_disabled[0x1];
976 u8 umr_modify_atomic_disabled[0x1];
977 u8 umr_indirect_mkey_disabled[0x1];
978 u8 umr_fence[0x2];
979 u8 reserved_at_20c[0x3];
980 u8 drain_sigerr[0x1];
981 u8 cmdif_checksum[0x2];
982 u8 sigerr_cqe[0x1];
983 u8 reserved_at_213[0x1];
984 u8 wq_signature[0x1];
985 u8 sctr_data_cqe[0x1];
986 u8 reserved_at_216[0x1];
987 u8 sho[0x1];
988 u8 tph[0x1];
989 u8 rf[0x1];
990 u8 dct[0x1];
991 u8 qos[0x1];
992 u8 eth_net_offloads[0x1];
993 u8 roce[0x1];
994 u8 atomic[0x1];
995 u8 reserved_at_21f[0x1];
996
997 u8 cq_oi[0x1];
998 u8 cq_resize[0x1];
999 u8 cq_moderation[0x1];
1000 u8 reserved_at_223[0x3];
1001 u8 cq_eq_remap[0x1];
1002 u8 pg[0x1];
1003 u8 block_lb_mc[0x1];
1004 u8 reserved_at_229[0x1];
1005 u8 scqe_break_moderation[0x1];
1006 u8 cq_period_start_from_cqe[0x1];
1007 u8 cd[0x1];
1008 u8 reserved_at_22d[0x1];
1009 u8 apm[0x1];
1010 u8 vector_calc[0x1];
1011 u8 umr_ptr_rlky[0x1];
1012 u8 imaicl[0x1];
1013 u8 reserved_at_232[0x4];
1014 u8 qkv[0x1];
1015 u8 pkv[0x1];
1016 u8 set_deth_sqpn[0x1];
1017 u8 reserved_at_239[0x3];
1018 u8 xrc[0x1];
1019 u8 ud[0x1];
1020 u8 uc[0x1];
1021 u8 rc[0x1];
1022
1023 u8 uar_4k[0x1];
1024 u8 reserved_at_241[0x9];
1025 u8 uar_sz[0x6];
1026 u8 reserved_at_250[0x8];
1027 u8 log_pg_sz[0x8];
1028
1029 u8 bf[0x1];
1030 u8 driver_version[0x1];
1031 u8 pad_tx_eth_packet[0x1];
1032 u8 reserved_at_263[0x8];
1033 u8 log_bf_reg_size[0x5];
1034
1035 u8 reserved_at_270[0xb];
1036 u8 lag_master[0x1];
1037 u8 num_lag_ports[0x4];
1038
1039 u8 reserved_at_280[0x10];
1040 u8 max_wqe_sz_sq[0x10];
1041
1042 u8 reserved_at_2a0[0x10];
1043 u8 max_wqe_sz_rq[0x10];
1044
1045 u8 max_flow_counter_31_16[0x10];
1046 u8 max_wqe_sz_sq_dc[0x10];
1047
1048 u8 reserved_at_2e0[0x7];
1049 u8 max_qp_mcg[0x19];
1050
1051 u8 reserved_at_300[0x18];
1052 u8 log_max_mcg[0x8];
1053
1054 u8 reserved_at_320[0x3];
1055 u8 log_max_transport_domain[0x5];
1056 u8 reserved_at_328[0x3];
1057 u8 log_max_pd[0x5];
1058 u8 reserved_at_330[0xb];
1059 u8 log_max_xrcd[0x5];
1060
1061 u8 nic_receive_steering_discard[0x1];
1062 u8 receive_discard_vport_down[0x1];
1063 u8 transmit_discard_vport_down[0x1];
1064 u8 reserved_at_343[0x5];
1065 u8 log_max_flow_counter_bulk[0x8];
1066 u8 max_flow_counter_15_0[0x10];
1067
1068
1069 u8 reserved_at_360[0x3];
1070 u8 log_max_rq[0x5];
1071 u8 reserved_at_368[0x3];
1072 u8 log_max_sq[0x5];
1073 u8 reserved_at_370[0x3];
1074 u8 log_max_tir[0x5];
1075 u8 reserved_at_378[0x3];
1076 u8 log_max_tis[0x5];
1077
1078 u8 basic_cyclic_rcv_wqe[0x1];
1079 u8 reserved_at_381[0x2];
1080 u8 log_max_rmp[0x5];
1081 u8 reserved_at_388[0x3];
1082 u8 log_max_rqt[0x5];
1083 u8 reserved_at_390[0x3];
1084 u8 log_max_rqt_size[0x5];
1085 u8 reserved_at_398[0x3];
1086 u8 log_max_tis_per_sq[0x5];
1087
1088 u8 ext_stride_num_range[0x1];
1089 u8 reserved_at_3a1[0x2];
1090 u8 log_max_stride_sz_rq[0x5];
1091 u8 reserved_at_3a8[0x3];
1092 u8 log_min_stride_sz_rq[0x5];
1093 u8 reserved_at_3b0[0x3];
1094 u8 log_max_stride_sz_sq[0x5];
1095 u8 reserved_at_3b8[0x3];
1096 u8 log_min_stride_sz_sq[0x5];
1097
1098 u8 hairpin[0x1];
1099 u8 reserved_at_3c1[0x2];
1100 u8 log_max_hairpin_queues[0x5];
1101 u8 reserved_at_3c8[0x3];
1102 u8 log_max_hairpin_wq_data_sz[0x5];
1103 u8 reserved_at_3d0[0x3];
1104 u8 log_max_hairpin_num_packets[0x5];
1105 u8 reserved_at_3d8[0x3];
1106 u8 log_max_wq_sz[0x5];
1107
1108 u8 nic_vport_change_event[0x1];
1109 u8 disable_local_lb_uc[0x1];
1110 u8 disable_local_lb_mc[0x1];
1111 u8 log_min_hairpin_wq_data_sz[0x5];
1112 u8 reserved_at_3e8[0x3];
1113 u8 log_max_vlan_list[0x5];
1114 u8 reserved_at_3f0[0x3];
1115 u8 log_max_current_mc_list[0x5];
1116 u8 reserved_at_3f8[0x3];
1117 u8 log_max_current_uc_list[0x5];
1118
1119 u8 reserved_at_400[0x60];
1120
1121 u8 reserved_at_460[0x10];
1122 u8 max_num_eqs[0x10];
1123
1124 u8 reserved_at_480[0x3];
1125 u8 log_max_l2_table[0x5];
1126 u8 reserved_at_488[0x8];
1127 u8 log_uar_page_sz[0x10];
1128
1129 u8 reserved_at_4a0[0x20];
1130 u8 device_frequency_mhz[0x20];
1131 u8 device_frequency_khz[0x20];
1132
1133 u8 reserved_at_500[0x20];
1134 u8 num_of_uars_per_page[0x20];
1135
1136 u8 flex_parser_protocols[0x20];
1137 u8 reserved_at_560[0x20];
1138
1139 u8 reserved_at_580[0x3c];
1140 u8 mini_cqe_resp_stride_index[0x1];
1141 u8 cqe_128_always[0x1];
1142 u8 cqe_compression_128[0x1];
1143 u8 cqe_compression[0x1];
1144
1145 u8 cqe_compression_timeout[0x10];
1146 u8 cqe_compression_max_num[0x10];
1147
1148 u8 reserved_at_5e0[0x10];
1149 u8 tag_matching[0x1];
1150 u8 rndv_offload_rc[0x1];
1151 u8 rndv_offload_dc[0x1];
1152 u8 log_tag_matching_list_sz[0x5];
1153 u8 reserved_at_5f8[0x3];
1154 u8 log_max_xrq[0x5];
1155
1156 u8 affiliate_nic_vport_criteria[0x8];
1157 u8 native_port_num[0x8];
1158 u8 num_vhca_ports[0x8];
1159 u8 reserved_at_618[0x6];
1160 u8 sw_owner_id[0x1];
1161 u8 reserved_at_61f[0x1e1];
1162};
1163
1164enum mlx5_flow_destination_type {
1165 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1166 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1167 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1168
1169 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1170 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1171};
1172
1173struct mlx5_ifc_dest_format_struct_bits {
1174 u8 destination_type[0x8];
1175 u8 destination_id[0x18];
1176 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1177 u8 reserved_at_21[0xf];
1178 u8 destination_eswitch_owner_vhca_id[0x10];
1179};
1180
1181struct mlx5_ifc_flow_counter_list_bits {
1182 u8 flow_counter_id[0x20];
1183
1184 u8 reserved_at_20[0x20];
1185};
1186
1187union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1188 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1189 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1190 u8 reserved_at_0[0x40];
1191};
1192
1193struct mlx5_ifc_fte_match_param_bits {
1194 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1195
1196 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1197
1198 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1199
1200 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1201
1202 u8 reserved_at_800[0x800];
1203};
1204
1205enum {
1206 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1207 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1208 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1209 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1210 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1211};
1212
1213struct mlx5_ifc_rx_hash_field_select_bits {
1214 u8 l3_prot_type[0x1];
1215 u8 l4_prot_type[0x1];
1216 u8 selected_fields[0x1e];
1217};
1218
1219enum {
1220 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1221 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1222};
1223
1224enum {
1225 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1226 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1227};
1228
1229struct mlx5_ifc_wq_bits {
1230 u8 wq_type[0x4];
1231 u8 wq_signature[0x1];
1232 u8 end_padding_mode[0x2];
1233 u8 cd_slave[0x1];
1234 u8 reserved_at_8[0x18];
1235
1236 u8 hds_skip_first_sge[0x1];
1237 u8 log2_hds_buf_size[0x3];
1238 u8 reserved_at_24[0x7];
1239 u8 page_offset[0x5];
1240 u8 lwm[0x10];
1241
1242 u8 reserved_at_40[0x8];
1243 u8 pd[0x18];
1244
1245 u8 reserved_at_60[0x8];
1246 u8 uar_page[0x18];
1247
1248 u8 dbr_addr[0x40];
1249
1250 u8 hw_counter[0x20];
1251
1252 u8 sw_counter[0x20];
1253
1254 u8 reserved_at_100[0xc];
1255 u8 log_wq_stride[0x4];
1256 u8 reserved_at_110[0x3];
1257 u8 log_wq_pg_sz[0x5];
1258 u8 reserved_at_118[0x3];
1259 u8 log_wq_sz[0x5];
1260
1261 u8 reserved_at_120[0x3];
1262 u8 log_hairpin_num_packets[0x5];
1263 u8 reserved_at_128[0x3];
1264 u8 log_hairpin_data_sz[0x5];
1265
1266 u8 reserved_at_130[0x4];
1267 u8 log_wqe_num_of_strides[0x4];
1268 u8 two_byte_shift_en[0x1];
1269 u8 reserved_at_139[0x4];
1270 u8 log_wqe_stride_size[0x3];
1271
1272 u8 reserved_at_140[0x4c0];
1273
1274 struct mlx5_ifc_cmd_pas_bits pas[0];
1275};
1276
1277struct mlx5_ifc_rq_num_bits {
1278 u8 reserved_at_0[0x8];
1279 u8 rq_num[0x18];
1280};
1281
1282struct mlx5_ifc_mac_address_layout_bits {
1283 u8 reserved_at_0[0x10];
1284 u8 mac_addr_47_32[0x10];
1285
1286 u8 mac_addr_31_0[0x20];
1287};
1288
1289struct mlx5_ifc_vlan_layout_bits {
1290 u8 reserved_at_0[0x14];
1291 u8 vlan[0x0c];
1292
1293 u8 reserved_at_20[0x20];
1294};
1295
1296struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1297 u8 reserved_at_0[0xa0];
1298
1299 u8 min_time_between_cnps[0x20];
1300
1301 u8 reserved_at_c0[0x12];
1302 u8 cnp_dscp[0x6];
1303 u8 reserved_at_d8[0x4];
1304 u8 cnp_prio_mode[0x1];
1305 u8 cnp_802p_prio[0x3];
1306
1307 u8 reserved_at_e0[0x720];
1308};
1309
1310struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1311 u8 reserved_at_0[0x60];
1312
1313 u8 reserved_at_60[0x4];
1314 u8 clamp_tgt_rate[0x1];
1315 u8 reserved_at_65[0x3];
1316 u8 clamp_tgt_rate_after_time_inc[0x1];
1317 u8 reserved_at_69[0x17];
1318
1319 u8 reserved_at_80[0x20];
1320
1321 u8 rpg_time_reset[0x20];
1322
1323 u8 rpg_byte_reset[0x20];
1324
1325 u8 rpg_threshold[0x20];
1326
1327 u8 rpg_max_rate[0x20];
1328
1329 u8 rpg_ai_rate[0x20];
1330
1331 u8 rpg_hai_rate[0x20];
1332
1333 u8 rpg_gd[0x20];
1334
1335 u8 rpg_min_dec_fac[0x20];
1336
1337 u8 rpg_min_rate[0x20];
1338
1339 u8 reserved_at_1c0[0xe0];
1340
1341 u8 rate_to_set_on_first_cnp[0x20];
1342
1343 u8 dce_tcp_g[0x20];
1344
1345 u8 dce_tcp_rtt[0x20];
1346
1347 u8 rate_reduce_monitor_period[0x20];
1348
1349 u8 reserved_at_320[0x20];
1350
1351 u8 initial_alpha_value[0x20];
1352
1353 u8 reserved_at_360[0x4a0];
1354};
1355
1356struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1357 u8 reserved_at_0[0x80];
1358
1359 u8 rppp_max_rps[0x20];
1360
1361 u8 rpg_time_reset[0x20];
1362
1363 u8 rpg_byte_reset[0x20];
1364
1365 u8 rpg_threshold[0x20];
1366
1367 u8 rpg_max_rate[0x20];
1368
1369 u8 rpg_ai_rate[0x20];
1370
1371 u8 rpg_hai_rate[0x20];
1372
1373 u8 rpg_gd[0x20];
1374
1375 u8 rpg_min_dec_fac[0x20];
1376
1377 u8 rpg_min_rate[0x20];
1378
1379 u8 reserved_at_1c0[0x640];
1380};
1381
1382enum {
1383 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1384 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1385 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1386};
1387
1388struct mlx5_ifc_resize_field_select_bits {
1389 u8 resize_field_select[0x20];
1390};
1391
1392enum {
1393 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1394 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1395 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1396 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1397};
1398
1399struct mlx5_ifc_modify_field_select_bits {
1400 u8 modify_field_select[0x20];
1401};
1402
1403struct mlx5_ifc_field_select_r_roce_np_bits {
1404 u8 field_select_r_roce_np[0x20];
1405};
1406
1407struct mlx5_ifc_field_select_r_roce_rp_bits {
1408 u8 field_select_r_roce_rp[0x20];
1409};
1410
1411enum {
1412 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1413 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1414 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1422};
1423
1424struct mlx5_ifc_field_select_802_1qau_rp_bits {
1425 u8 field_select_8021qaurp[0x20];
1426};
1427
1428struct mlx5_ifc_phys_layer_cntrs_bits {
1429 u8 time_since_last_clear_high[0x20];
1430
1431 u8 time_since_last_clear_low[0x20];
1432
1433 u8 symbol_errors_high[0x20];
1434
1435 u8 symbol_errors_low[0x20];
1436
1437 u8 sync_headers_errors_high[0x20];
1438
1439 u8 sync_headers_errors_low[0x20];
1440
1441 u8 edpl_bip_errors_lane0_high[0x20];
1442
1443 u8 edpl_bip_errors_lane0_low[0x20];
1444
1445 u8 edpl_bip_errors_lane1_high[0x20];
1446
1447 u8 edpl_bip_errors_lane1_low[0x20];
1448
1449 u8 edpl_bip_errors_lane2_high[0x20];
1450
1451 u8 edpl_bip_errors_lane2_low[0x20];
1452
1453 u8 edpl_bip_errors_lane3_high[0x20];
1454
1455 u8 edpl_bip_errors_lane3_low[0x20];
1456
1457 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1458
1459 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1460
1461 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1462
1463 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1464
1465 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1466
1467 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1468
1469 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1470
1471 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1472
1473 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1474
1475 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1476
1477 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1478
1479 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1480
1481 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1482
1483 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1484
1485 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1486
1487 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1488
1489 u8 rs_fec_corrected_blocks_high[0x20];
1490
1491 u8 rs_fec_corrected_blocks_low[0x20];
1492
1493 u8 rs_fec_uncorrectable_blocks_high[0x20];
1494
1495 u8 rs_fec_uncorrectable_blocks_low[0x20];
1496
1497 u8 rs_fec_no_errors_blocks_high[0x20];
1498
1499 u8 rs_fec_no_errors_blocks_low[0x20];
1500
1501 u8 rs_fec_single_error_blocks_high[0x20];
1502
1503 u8 rs_fec_single_error_blocks_low[0x20];
1504
1505 u8 rs_fec_corrected_symbols_total_high[0x20];
1506
1507 u8 rs_fec_corrected_symbols_total_low[0x20];
1508
1509 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1510
1511 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1512
1513 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1514
1515 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1516
1517 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1518
1519 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1520
1521 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1522
1523 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1524
1525 u8 link_down_events[0x20];
1526
1527 u8 successful_recovery_events[0x20];
1528
1529 u8 reserved_at_640[0x180];
1530};
1531
1532struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1533 u8 time_since_last_clear_high[0x20];
1534
1535 u8 time_since_last_clear_low[0x20];
1536
1537 u8 phy_received_bits_high[0x20];
1538
1539 u8 phy_received_bits_low[0x20];
1540
1541 u8 phy_symbol_errors_high[0x20];
1542
1543 u8 phy_symbol_errors_low[0x20];
1544
1545 u8 phy_corrected_bits_high[0x20];
1546
1547 u8 phy_corrected_bits_low[0x20];
1548
1549 u8 phy_corrected_bits_lane0_high[0x20];
1550
1551 u8 phy_corrected_bits_lane0_low[0x20];
1552
1553 u8 phy_corrected_bits_lane1_high[0x20];
1554
1555 u8 phy_corrected_bits_lane1_low[0x20];
1556
1557 u8 phy_corrected_bits_lane2_high[0x20];
1558
1559 u8 phy_corrected_bits_lane2_low[0x20];
1560
1561 u8 phy_corrected_bits_lane3_high[0x20];
1562
1563 u8 phy_corrected_bits_lane3_low[0x20];
1564
1565 u8 reserved_at_200[0x5c0];
1566};
1567
1568struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1569 u8 symbol_error_counter[0x10];
1570
1571 u8 link_error_recovery_counter[0x8];
1572
1573 u8 link_downed_counter[0x8];
1574
1575 u8 port_rcv_errors[0x10];
1576
1577 u8 port_rcv_remote_physical_errors[0x10];
1578
1579 u8 port_rcv_switch_relay_errors[0x10];
1580
1581 u8 port_xmit_discards[0x10];
1582
1583 u8 port_xmit_constraint_errors[0x8];
1584
1585 u8 port_rcv_constraint_errors[0x8];
1586
1587 u8 reserved_at_70[0x8];
1588
1589 u8 link_overrun_errors[0x8];
1590
1591 u8 reserved_at_80[0x10];
1592
1593 u8 vl_15_dropped[0x10];
1594
1595 u8 reserved_at_a0[0x80];
1596
1597 u8 port_xmit_wait[0x20];
1598};
1599
1600struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1601 u8 transmit_queue_high[0x20];
1602
1603 u8 transmit_queue_low[0x20];
1604
1605 u8 reserved_at_40[0x780];
1606};
1607
1608struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1609 u8 rx_octets_high[0x20];
1610
1611 u8 rx_octets_low[0x20];
1612
1613 u8 reserved_at_40[0xc0];
1614
1615 u8 rx_frames_high[0x20];
1616
1617 u8 rx_frames_low[0x20];
1618
1619 u8 tx_octets_high[0x20];
1620
1621 u8 tx_octets_low[0x20];
1622
1623 u8 reserved_at_180[0xc0];
1624
1625 u8 tx_frames_high[0x20];
1626
1627 u8 tx_frames_low[0x20];
1628
1629 u8 rx_pause_high[0x20];
1630
1631 u8 rx_pause_low[0x20];
1632
1633 u8 rx_pause_duration_high[0x20];
1634
1635 u8 rx_pause_duration_low[0x20];
1636
1637 u8 tx_pause_high[0x20];
1638
1639 u8 tx_pause_low[0x20];
1640
1641 u8 tx_pause_duration_high[0x20];
1642
1643 u8 tx_pause_duration_low[0x20];
1644
1645 u8 rx_pause_transition_high[0x20];
1646
1647 u8 rx_pause_transition_low[0x20];
1648
1649 u8 reserved_at_3c0[0x40];
1650
1651 u8 device_stall_minor_watermark_cnt_high[0x20];
1652
1653 u8 device_stall_minor_watermark_cnt_low[0x20];
1654
1655 u8 device_stall_critical_watermark_cnt_high[0x20];
1656
1657 u8 device_stall_critical_watermark_cnt_low[0x20];
1658
1659 u8 reserved_at_480[0x340];
1660};
1661
1662struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1663 u8 port_transmit_wait_high[0x20];
1664
1665 u8 port_transmit_wait_low[0x20];
1666
1667 u8 reserved_at_40[0x100];
1668
1669 u8 rx_buffer_almost_full_high[0x20];
1670
1671 u8 rx_buffer_almost_full_low[0x20];
1672
1673 u8 rx_buffer_full_high[0x20];
1674
1675 u8 rx_buffer_full_low[0x20];
1676
1677 u8 reserved_at_1c0[0x600];
1678};
1679
1680struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1681 u8 dot3stats_alignment_errors_high[0x20];
1682
1683 u8 dot3stats_alignment_errors_low[0x20];
1684
1685 u8 dot3stats_fcs_errors_high[0x20];
1686
1687 u8 dot3stats_fcs_errors_low[0x20];
1688
1689 u8 dot3stats_single_collision_frames_high[0x20];
1690
1691 u8 dot3stats_single_collision_frames_low[0x20];
1692
1693 u8 dot3stats_multiple_collision_frames_high[0x20];
1694
1695 u8 dot3stats_multiple_collision_frames_low[0x20];
1696
1697 u8 dot3stats_sqe_test_errors_high[0x20];
1698
1699 u8 dot3stats_sqe_test_errors_low[0x20];
1700
1701 u8 dot3stats_deferred_transmissions_high[0x20];
1702
1703 u8 dot3stats_deferred_transmissions_low[0x20];
1704
1705 u8 dot3stats_late_collisions_high[0x20];
1706
1707 u8 dot3stats_late_collisions_low[0x20];
1708
1709 u8 dot3stats_excessive_collisions_high[0x20];
1710
1711 u8 dot3stats_excessive_collisions_low[0x20];
1712
1713 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1714
1715 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1716
1717 u8 dot3stats_carrier_sense_errors_high[0x20];
1718
1719 u8 dot3stats_carrier_sense_errors_low[0x20];
1720
1721 u8 dot3stats_frame_too_longs_high[0x20];
1722
1723 u8 dot3stats_frame_too_longs_low[0x20];
1724
1725 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1726
1727 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1728
1729 u8 dot3stats_symbol_errors_high[0x20];
1730
1731 u8 dot3stats_symbol_errors_low[0x20];
1732
1733 u8 dot3control_in_unknown_opcodes_high[0x20];
1734
1735 u8 dot3control_in_unknown_opcodes_low[0x20];
1736
1737 u8 dot3in_pause_frames_high[0x20];
1738
1739 u8 dot3in_pause_frames_low[0x20];
1740
1741 u8 dot3out_pause_frames_high[0x20];
1742
1743 u8 dot3out_pause_frames_low[0x20];
1744
1745 u8 reserved_at_400[0x3c0];
1746};
1747
1748struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1749 u8 ether_stats_drop_events_high[0x20];
1750
1751 u8 ether_stats_drop_events_low[0x20];
1752
1753 u8 ether_stats_octets_high[0x20];
1754
1755 u8 ether_stats_octets_low[0x20];
1756
1757 u8 ether_stats_pkts_high[0x20];
1758
1759 u8 ether_stats_pkts_low[0x20];
1760
1761 u8 ether_stats_broadcast_pkts_high[0x20];
1762
1763 u8 ether_stats_broadcast_pkts_low[0x20];
1764
1765 u8 ether_stats_multicast_pkts_high[0x20];
1766
1767 u8 ether_stats_multicast_pkts_low[0x20];
1768
1769 u8 ether_stats_crc_align_errors_high[0x20];
1770
1771 u8 ether_stats_crc_align_errors_low[0x20];
1772
1773 u8 ether_stats_undersize_pkts_high[0x20];
1774
1775 u8 ether_stats_undersize_pkts_low[0x20];
1776
1777 u8 ether_stats_oversize_pkts_high[0x20];
1778
1779 u8 ether_stats_oversize_pkts_low[0x20];
1780
1781 u8 ether_stats_fragments_high[0x20];
1782
1783 u8 ether_stats_fragments_low[0x20];
1784
1785 u8 ether_stats_jabbers_high[0x20];
1786
1787 u8 ether_stats_jabbers_low[0x20];
1788
1789 u8 ether_stats_collisions_high[0x20];
1790
1791 u8 ether_stats_collisions_low[0x20];
1792
1793 u8 ether_stats_pkts64octets_high[0x20];
1794
1795 u8 ether_stats_pkts64octets_low[0x20];
1796
1797 u8 ether_stats_pkts65to127octets_high[0x20];
1798
1799 u8 ether_stats_pkts65to127octets_low[0x20];
1800
1801 u8 ether_stats_pkts128to255octets_high[0x20];
1802
1803 u8 ether_stats_pkts128to255octets_low[0x20];
1804
1805 u8 ether_stats_pkts256to511octets_high[0x20];
1806
1807 u8 ether_stats_pkts256to511octets_low[0x20];
1808
1809 u8 ether_stats_pkts512to1023octets_high[0x20];
1810
1811 u8 ether_stats_pkts512to1023octets_low[0x20];
1812
1813 u8 ether_stats_pkts1024to1518octets_high[0x20];
1814
1815 u8 ether_stats_pkts1024to1518octets_low[0x20];
1816
1817 u8 ether_stats_pkts1519to2047octets_high[0x20];
1818
1819 u8 ether_stats_pkts1519to2047octets_low[0x20];
1820
1821 u8 ether_stats_pkts2048to4095octets_high[0x20];
1822
1823 u8 ether_stats_pkts2048to4095octets_low[0x20];
1824
1825 u8 ether_stats_pkts4096to8191octets_high[0x20];
1826
1827 u8 ether_stats_pkts4096to8191octets_low[0x20];
1828
1829 u8 ether_stats_pkts8192to10239octets_high[0x20];
1830
1831 u8 ether_stats_pkts8192to10239octets_low[0x20];
1832
1833 u8 reserved_at_540[0x280];
1834};
1835
1836struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1837 u8 if_in_octets_high[0x20];
1838
1839 u8 if_in_octets_low[0x20];
1840
1841 u8 if_in_ucast_pkts_high[0x20];
1842
1843 u8 if_in_ucast_pkts_low[0x20];
1844
1845 u8 if_in_discards_high[0x20];
1846
1847 u8 if_in_discards_low[0x20];
1848
1849 u8 if_in_errors_high[0x20];
1850
1851 u8 if_in_errors_low[0x20];
1852
1853 u8 if_in_unknown_protos_high[0x20];
1854
1855 u8 if_in_unknown_protos_low[0x20];
1856
1857 u8 if_out_octets_high[0x20];
1858
1859 u8 if_out_octets_low[0x20];
1860
1861 u8 if_out_ucast_pkts_high[0x20];
1862
1863 u8 if_out_ucast_pkts_low[0x20];
1864
1865 u8 if_out_discards_high[0x20];
1866
1867 u8 if_out_discards_low[0x20];
1868
1869 u8 if_out_errors_high[0x20];
1870
1871 u8 if_out_errors_low[0x20];
1872
1873 u8 if_in_multicast_pkts_high[0x20];
1874
1875 u8 if_in_multicast_pkts_low[0x20];
1876
1877 u8 if_in_broadcast_pkts_high[0x20];
1878
1879 u8 if_in_broadcast_pkts_low[0x20];
1880
1881 u8 if_out_multicast_pkts_high[0x20];
1882
1883 u8 if_out_multicast_pkts_low[0x20];
1884
1885 u8 if_out_broadcast_pkts_high[0x20];
1886
1887 u8 if_out_broadcast_pkts_low[0x20];
1888
1889 u8 reserved_at_340[0x480];
1890};
1891
1892struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1893 u8 a_frames_transmitted_ok_high[0x20];
1894
1895 u8 a_frames_transmitted_ok_low[0x20];
1896
1897 u8 a_frames_received_ok_high[0x20];
1898
1899 u8 a_frames_received_ok_low[0x20];
1900
1901 u8 a_frame_check_sequence_errors_high[0x20];
1902
1903 u8 a_frame_check_sequence_errors_low[0x20];
1904
1905 u8 a_alignment_errors_high[0x20];
1906
1907 u8 a_alignment_errors_low[0x20];
1908
1909 u8 a_octets_transmitted_ok_high[0x20];
1910
1911 u8 a_octets_transmitted_ok_low[0x20];
1912
1913 u8 a_octets_received_ok_high[0x20];
1914
1915 u8 a_octets_received_ok_low[0x20];
1916
1917 u8 a_multicast_frames_xmitted_ok_high[0x20];
1918
1919 u8 a_multicast_frames_xmitted_ok_low[0x20];
1920
1921 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1922
1923 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1924
1925 u8 a_multicast_frames_received_ok_high[0x20];
1926
1927 u8 a_multicast_frames_received_ok_low[0x20];
1928
1929 u8 a_broadcast_frames_received_ok_high[0x20];
1930
1931 u8 a_broadcast_frames_received_ok_low[0x20];
1932
1933 u8 a_in_range_length_errors_high[0x20];
1934
1935 u8 a_in_range_length_errors_low[0x20];
1936
1937 u8 a_out_of_range_length_field_high[0x20];
1938
1939 u8 a_out_of_range_length_field_low[0x20];
1940
1941 u8 a_frame_too_long_errors_high[0x20];
1942
1943 u8 a_frame_too_long_errors_low[0x20];
1944
1945 u8 a_symbol_error_during_carrier_high[0x20];
1946
1947 u8 a_symbol_error_during_carrier_low[0x20];
1948
1949 u8 a_mac_control_frames_transmitted_high[0x20];
1950
1951 u8 a_mac_control_frames_transmitted_low[0x20];
1952
1953 u8 a_mac_control_frames_received_high[0x20];
1954
1955 u8 a_mac_control_frames_received_low[0x20];
1956
1957 u8 a_unsupported_opcodes_received_high[0x20];
1958
1959 u8 a_unsupported_opcodes_received_low[0x20];
1960
1961 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1962
1963 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1964
1965 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1966
1967 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1968
1969 u8 reserved_at_4c0[0x300];
1970};
1971
1972struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1973 u8 life_time_counter_high[0x20];
1974
1975 u8 life_time_counter_low[0x20];
1976
1977 u8 rx_errors[0x20];
1978
1979 u8 tx_errors[0x20];
1980
1981 u8 l0_to_recovery_eieos[0x20];
1982
1983 u8 l0_to_recovery_ts[0x20];
1984
1985 u8 l0_to_recovery_framing[0x20];
1986
1987 u8 l0_to_recovery_retrain[0x20];
1988
1989 u8 crc_error_dllp[0x20];
1990
1991 u8 crc_error_tlp[0x20];
1992
1993 u8 tx_overflow_buffer_pkt_high[0x20];
1994
1995 u8 tx_overflow_buffer_pkt_low[0x20];
1996
1997 u8 outbound_stalled_reads[0x20];
1998
1999 u8 outbound_stalled_writes[0x20];
2000
2001 u8 outbound_stalled_reads_events[0x20];
2002
2003 u8 outbound_stalled_writes_events[0x20];
2004
2005 u8 reserved_at_200[0x5c0];
2006};
2007
2008struct mlx5_ifc_cmd_inter_comp_event_bits {
2009 u8 command_completion_vector[0x20];
2010
2011 u8 reserved_at_20[0xc0];
2012};
2013
2014struct mlx5_ifc_stall_vl_event_bits {
2015 u8 reserved_at_0[0x18];
2016 u8 port_num[0x1];
2017 u8 reserved_at_19[0x3];
2018 u8 vl[0x4];
2019
2020 u8 reserved_at_20[0xa0];
2021};
2022
2023struct mlx5_ifc_db_bf_congestion_event_bits {
2024 u8 event_subtype[0x8];
2025 u8 reserved_at_8[0x8];
2026 u8 congestion_level[0x8];
2027 u8 reserved_at_18[0x8];
2028
2029 u8 reserved_at_20[0xa0];
2030};
2031
2032struct mlx5_ifc_gpio_event_bits {
2033 u8 reserved_at_0[0x60];
2034
2035 u8 gpio_event_hi[0x20];
2036
2037 u8 gpio_event_lo[0x20];
2038
2039 u8 reserved_at_a0[0x40];
2040};
2041
2042struct mlx5_ifc_port_state_change_event_bits {
2043 u8 reserved_at_0[0x40];
2044
2045 u8 port_num[0x4];
2046 u8 reserved_at_44[0x1c];
2047
2048 u8 reserved_at_60[0x80];
2049};
2050
2051struct mlx5_ifc_dropped_packet_logged_bits {
2052 u8 reserved_at_0[0xe0];
2053};
2054
2055enum {
2056 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2057 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2058};
2059
2060struct mlx5_ifc_cq_error_bits {
2061 u8 reserved_at_0[0x8];
2062 u8 cqn[0x18];
2063
2064 u8 reserved_at_20[0x20];
2065
2066 u8 reserved_at_40[0x18];
2067 u8 syndrome[0x8];
2068
2069 u8 reserved_at_60[0x80];
2070};
2071
2072struct mlx5_ifc_rdma_page_fault_event_bits {
2073 u8 bytes_committed[0x20];
2074
2075 u8 r_key[0x20];
2076
2077 u8 reserved_at_40[0x10];
2078 u8 packet_len[0x10];
2079
2080 u8 rdma_op_len[0x20];
2081
2082 u8 rdma_va[0x40];
2083
2084 u8 reserved_at_c0[0x5];
2085 u8 rdma[0x1];
2086 u8 write[0x1];
2087 u8 requestor[0x1];
2088 u8 qp_number[0x18];
2089};
2090
2091struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2092 u8 bytes_committed[0x20];
2093
2094 u8 reserved_at_20[0x10];
2095 u8 wqe_index[0x10];
2096
2097 u8 reserved_at_40[0x10];
2098 u8 len[0x10];
2099
2100 u8 reserved_at_60[0x60];
2101
2102 u8 reserved_at_c0[0x5];
2103 u8 rdma[0x1];
2104 u8 write_read[0x1];
2105 u8 requestor[0x1];
2106 u8 qpn[0x18];
2107};
2108
2109struct mlx5_ifc_qp_events_bits {
2110 u8 reserved_at_0[0xa0];
2111
2112 u8 type[0x8];
2113 u8 reserved_at_a8[0x18];
2114
2115 u8 reserved_at_c0[0x8];
2116 u8 qpn_rqn_sqn[0x18];
2117};
2118
2119struct mlx5_ifc_dct_events_bits {
2120 u8 reserved_at_0[0xc0];
2121
2122 u8 reserved_at_c0[0x8];
2123 u8 dct_number[0x18];
2124};
2125
2126struct mlx5_ifc_comp_event_bits {
2127 u8 reserved_at_0[0xc0];
2128
2129 u8 reserved_at_c0[0x8];
2130 u8 cq_number[0x18];
2131};
2132
2133enum {
2134 MLX5_QPC_STATE_RST = 0x0,
2135 MLX5_QPC_STATE_INIT = 0x1,
2136 MLX5_QPC_STATE_RTR = 0x2,
2137 MLX5_QPC_STATE_RTS = 0x3,
2138 MLX5_QPC_STATE_SQER = 0x4,
2139 MLX5_QPC_STATE_ERR = 0x6,
2140 MLX5_QPC_STATE_SQD = 0x7,
2141 MLX5_QPC_STATE_SUSPENDED = 0x9,
2142};
2143
2144enum {
2145 MLX5_QPC_ST_RC = 0x0,
2146 MLX5_QPC_ST_UC = 0x1,
2147 MLX5_QPC_ST_UD = 0x2,
2148 MLX5_QPC_ST_XRC = 0x3,
2149 MLX5_QPC_ST_DCI = 0x5,
2150 MLX5_QPC_ST_QP0 = 0x7,
2151 MLX5_QPC_ST_QP1 = 0x8,
2152 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2153 MLX5_QPC_ST_REG_UMR = 0xc,
2154};
2155
2156enum {
2157 MLX5_QPC_PM_STATE_ARMED = 0x0,
2158 MLX5_QPC_PM_STATE_REARM = 0x1,
2159 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2160 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2161};
2162
2163enum {
2164 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2165};
2166
2167enum {
2168 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2169 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2170};
2171
2172enum {
2173 MLX5_QPC_MTU_256_BYTES = 0x1,
2174 MLX5_QPC_MTU_512_BYTES = 0x2,
2175 MLX5_QPC_MTU_1K_BYTES = 0x3,
2176 MLX5_QPC_MTU_2K_BYTES = 0x4,
2177 MLX5_QPC_MTU_4K_BYTES = 0x5,
2178 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2179};
2180
2181enum {
2182 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2183 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2184 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2185 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2186 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2187 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2188 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2189 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2190};
2191
2192enum {
2193 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2194 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2195 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2196};
2197
2198enum {
2199 MLX5_QPC_CS_RES_DISABLE = 0x0,
2200 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2201 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2202};
2203
2204struct mlx5_ifc_qpc_bits {
2205 u8 state[0x4];
2206 u8 lag_tx_port_affinity[0x4];
2207 u8 st[0x8];
2208 u8 reserved_at_10[0x3];
2209 u8 pm_state[0x2];
2210 u8 reserved_at_15[0x3];
2211 u8 offload_type[0x4];
2212 u8 end_padding_mode[0x2];
2213 u8 reserved_at_1e[0x2];
2214
2215 u8 wq_signature[0x1];
2216 u8 block_lb_mc[0x1];
2217 u8 atomic_like_write_en[0x1];
2218 u8 latency_sensitive[0x1];
2219 u8 reserved_at_24[0x1];
2220 u8 drain_sigerr[0x1];
2221 u8 reserved_at_26[0x2];
2222 u8 pd[0x18];
2223
2224 u8 mtu[0x3];
2225 u8 log_msg_max[0x5];
2226 u8 reserved_at_48[0x1];
2227 u8 log_rq_size[0x4];
2228 u8 log_rq_stride[0x3];
2229 u8 no_sq[0x1];
2230 u8 log_sq_size[0x4];
2231 u8 reserved_at_55[0x6];
2232 u8 rlky[0x1];
2233 u8 ulp_stateless_offload_mode[0x4];
2234
2235 u8 counter_set_id[0x8];
2236 u8 uar_page[0x18];
2237
2238 u8 reserved_at_80[0x8];
2239 u8 user_index[0x18];
2240
2241 u8 reserved_at_a0[0x3];
2242 u8 log_page_size[0x5];
2243 u8 remote_qpn[0x18];
2244
2245 struct mlx5_ifc_ads_bits primary_address_path;
2246
2247 struct mlx5_ifc_ads_bits secondary_address_path;
2248
2249 u8 log_ack_req_freq[0x4];
2250 u8 reserved_at_384[0x4];
2251 u8 log_sra_max[0x3];
2252 u8 reserved_at_38b[0x2];
2253 u8 retry_count[0x3];
2254 u8 rnr_retry[0x3];
2255 u8 reserved_at_393[0x1];
2256 u8 fre[0x1];
2257 u8 cur_rnr_retry[0x3];
2258 u8 cur_retry_count[0x3];
2259 u8 reserved_at_39b[0x5];
2260
2261 u8 reserved_at_3a0[0x20];
2262
2263 u8 reserved_at_3c0[0x8];
2264 u8 next_send_psn[0x18];
2265
2266 u8 reserved_at_3e0[0x8];
2267 u8 cqn_snd[0x18];
2268
2269 u8 reserved_at_400[0x8];
2270 u8 deth_sqpn[0x18];
2271
2272 u8 reserved_at_420[0x20];
2273
2274 u8 reserved_at_440[0x8];
2275 u8 last_acked_psn[0x18];
2276
2277 u8 reserved_at_460[0x8];
2278 u8 ssn[0x18];
2279
2280 u8 reserved_at_480[0x8];
2281 u8 log_rra_max[0x3];
2282 u8 reserved_at_48b[0x1];
2283 u8 atomic_mode[0x4];
2284 u8 rre[0x1];
2285 u8 rwe[0x1];
2286 u8 rae[0x1];
2287 u8 reserved_at_493[0x1];
2288 u8 page_offset[0x6];
2289 u8 reserved_at_49a[0x3];
2290 u8 cd_slave_receive[0x1];
2291 u8 cd_slave_send[0x1];
2292 u8 cd_master[0x1];
2293
2294 u8 reserved_at_4a0[0x3];
2295 u8 min_rnr_nak[0x5];
2296 u8 next_rcv_psn[0x18];
2297
2298 u8 reserved_at_4c0[0x8];
2299 u8 xrcd[0x18];
2300
2301 u8 reserved_at_4e0[0x8];
2302 u8 cqn_rcv[0x18];
2303
2304 u8 dbr_addr[0x40];
2305
2306 u8 q_key[0x20];
2307
2308 u8 reserved_at_560[0x5];
2309 u8 rq_type[0x3];
2310 u8 srqn_rmpn_xrqn[0x18];
2311
2312 u8 reserved_at_580[0x8];
2313 u8 rmsn[0x18];
2314
2315 u8 hw_sq_wqebb_counter[0x10];
2316 u8 sw_sq_wqebb_counter[0x10];
2317
2318 u8 hw_rq_counter[0x20];
2319
2320 u8 sw_rq_counter[0x20];
2321
2322 u8 reserved_at_600[0x20];
2323
2324 u8 reserved_at_620[0xf];
2325 u8 cgs[0x1];
2326 u8 cs_req[0x8];
2327 u8 cs_res[0x8];
2328
2329 u8 dc_access_key[0x40];
2330
2331 u8 reserved_at_680[0xc0];
2332};
2333
2334struct mlx5_ifc_roce_addr_layout_bits {
2335 u8 source_l3_address[16][0x8];
2336
2337 u8 reserved_at_80[0x3];
2338 u8 vlan_valid[0x1];
2339 u8 vlan_id[0xc];
2340 u8 source_mac_47_32[0x10];
2341
2342 u8 source_mac_31_0[0x20];
2343
2344 u8 reserved_at_c0[0x14];
2345 u8 roce_l3_type[0x4];
2346 u8 roce_version[0x8];
2347
2348 u8 reserved_at_e0[0x20];
2349};
2350
2351union mlx5_ifc_hca_cap_union_bits {
2352 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2353 struct mlx5_ifc_odp_cap_bits odp_cap;
2354 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2355 struct mlx5_ifc_roce_cap_bits roce_cap;
2356 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2357 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2358 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2359 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2360 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2361 struct mlx5_ifc_qos_cap_bits qos_cap;
2362 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2363 u8 reserved_at_0[0x8000];
2364};
2365
2366enum {
2367 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2368 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2369 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2370 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2371 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2372 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2373 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2374 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2375 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2376};
2377
2378struct mlx5_ifc_vlan_bits {
2379 u8 ethtype[0x10];
2380 u8 prio[0x3];
2381 u8 cfi[0x1];
2382 u8 vid[0xc];
2383};
2384
2385struct mlx5_ifc_flow_context_bits {
2386 struct mlx5_ifc_vlan_bits push_vlan;
2387
2388 u8 group_id[0x20];
2389
2390 u8 reserved_at_40[0x8];
2391 u8 flow_tag[0x18];
2392
2393 u8 reserved_at_60[0x10];
2394 u8 action[0x10];
2395
2396 u8 reserved_at_80[0x8];
2397 u8 destination_list_size[0x18];
2398
2399 u8 reserved_at_a0[0x8];
2400 u8 flow_counter_list_size[0x18];
2401
2402 u8 encap_id[0x20];
2403
2404 u8 modify_header_id[0x20];
2405
2406 u8 reserved_at_100[0x100];
2407
2408 struct mlx5_ifc_fte_match_param_bits match_value;
2409
2410 u8 reserved_at_1200[0x600];
2411
2412 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2413};
2414
2415enum {
2416 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2417 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2418};
2419
2420struct mlx5_ifc_xrc_srqc_bits {
2421 u8 state[0x4];
2422 u8 log_xrc_srq_size[0x4];
2423 u8 reserved_at_8[0x18];
2424
2425 u8 wq_signature[0x1];
2426 u8 cont_srq[0x1];
2427 u8 reserved_at_22[0x1];
2428 u8 rlky[0x1];
2429 u8 basic_cyclic_rcv_wqe[0x1];
2430 u8 log_rq_stride[0x3];
2431 u8 xrcd[0x18];
2432
2433 u8 page_offset[0x6];
2434 u8 reserved_at_46[0x2];
2435 u8 cqn[0x18];
2436
2437 u8 reserved_at_60[0x20];
2438
2439 u8 user_index_equal_xrc_srqn[0x1];
2440 u8 reserved_at_81[0x1];
2441 u8 log_page_size[0x6];
2442 u8 user_index[0x18];
2443
2444 u8 reserved_at_a0[0x20];
2445
2446 u8 reserved_at_c0[0x8];
2447 u8 pd[0x18];
2448
2449 u8 lwm[0x10];
2450 u8 wqe_cnt[0x10];
2451
2452 u8 reserved_at_100[0x40];
2453
2454 u8 db_record_addr_h[0x20];
2455
2456 u8 db_record_addr_l[0x1e];
2457 u8 reserved_at_17e[0x2];
2458
2459 u8 reserved_at_180[0x80];
2460};
2461
2462struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2463 u8 counter_error_queues[0x20];
2464
2465 u8 total_error_queues[0x20];
2466
2467 u8 send_queue_priority_update_flow[0x20];
2468
2469 u8 reserved_at_60[0x20];
2470
2471 u8 nic_receive_steering_discard[0x40];
2472
2473 u8 receive_discard_vport_down[0x40];
2474
2475 u8 transmit_discard_vport_down[0x40];
2476
2477 u8 reserved_at_140[0xec0];
2478};
2479
2480struct mlx5_ifc_traffic_counter_bits {
2481 u8 packets[0x40];
2482
2483 u8 octets[0x40];
2484};
2485
2486struct mlx5_ifc_tisc_bits {
2487 u8 strict_lag_tx_port_affinity[0x1];
2488 u8 reserved_at_1[0x3];
2489 u8 lag_tx_port_affinity[0x04];
2490
2491 u8 reserved_at_8[0x4];
2492 u8 prio[0x4];
2493 u8 reserved_at_10[0x10];
2494
2495 u8 reserved_at_20[0x100];
2496
2497 u8 reserved_at_120[0x8];
2498 u8 transport_domain[0x18];
2499
2500 u8 reserved_at_140[0x8];
2501 u8 underlay_qpn[0x18];
2502 u8 reserved_at_160[0x3a0];
2503};
2504
2505enum {
2506 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2507 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2508};
2509
2510enum {
2511 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2512 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2513};
2514
2515enum {
2516 MLX5_RX_HASH_FN_NONE = 0x0,
2517 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2518 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2519};
2520
2521enum {
2522 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2523 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2524};
2525
2526struct mlx5_ifc_tirc_bits {
2527 u8 reserved_at_0[0x20];
2528
2529 u8 disp_type[0x4];
2530 u8 reserved_at_24[0x1c];
2531
2532 u8 reserved_at_40[0x40];
2533
2534 u8 reserved_at_80[0x4];
2535 u8 lro_timeout_period_usecs[0x10];
2536 u8 lro_enable_mask[0x4];
2537 u8 lro_max_ip_payload_size[0x8];
2538
2539 u8 reserved_at_a0[0x40];
2540
2541 u8 reserved_at_e0[0x8];
2542 u8 inline_rqn[0x18];
2543
2544 u8 rx_hash_symmetric[0x1];
2545 u8 reserved_at_101[0x1];
2546 u8 tunneled_offload_en[0x1];
2547 u8 reserved_at_103[0x5];
2548 u8 indirect_table[0x18];
2549
2550 u8 rx_hash_fn[0x4];
2551 u8 reserved_at_124[0x2];
2552 u8 self_lb_block[0x2];
2553 u8 transport_domain[0x18];
2554
2555 u8 rx_hash_toeplitz_key[10][0x20];
2556
2557 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2558
2559 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2560
2561 u8 reserved_at_2c0[0x4c0];
2562};
2563
2564enum {
2565 MLX5_SRQC_STATE_GOOD = 0x0,
2566 MLX5_SRQC_STATE_ERROR = 0x1,
2567};
2568
2569struct mlx5_ifc_srqc_bits {
2570 u8 state[0x4];
2571 u8 log_srq_size[0x4];
2572 u8 reserved_at_8[0x18];
2573
2574 u8 wq_signature[0x1];
2575 u8 cont_srq[0x1];
2576 u8 reserved_at_22[0x1];
2577 u8 rlky[0x1];
2578 u8 reserved_at_24[0x1];
2579 u8 log_rq_stride[0x3];
2580 u8 xrcd[0x18];
2581
2582 u8 page_offset[0x6];
2583 u8 reserved_at_46[0x2];
2584 u8 cqn[0x18];
2585
2586 u8 reserved_at_60[0x20];
2587
2588 u8 reserved_at_80[0x2];
2589 u8 log_page_size[0x6];
2590 u8 reserved_at_88[0x18];
2591
2592 u8 reserved_at_a0[0x20];
2593
2594 u8 reserved_at_c0[0x8];
2595 u8 pd[0x18];
2596
2597 u8 lwm[0x10];
2598 u8 wqe_cnt[0x10];
2599
2600 u8 reserved_at_100[0x40];
2601
2602 u8 dbr_addr[0x40];
2603
2604 u8 reserved_at_180[0x80];
2605};
2606
2607enum {
2608 MLX5_SQC_STATE_RST = 0x0,
2609 MLX5_SQC_STATE_RDY = 0x1,
2610 MLX5_SQC_STATE_ERR = 0x3,
2611};
2612
2613struct mlx5_ifc_sqc_bits {
2614 u8 rlky[0x1];
2615 u8 cd_master[0x1];
2616 u8 fre[0x1];
2617 u8 flush_in_error_en[0x1];
2618 u8 allow_multi_pkt_send_wqe[0x1];
2619 u8 min_wqe_inline_mode[0x3];
2620 u8 state[0x4];
2621 u8 reg_umr[0x1];
2622 u8 allow_swp[0x1];
2623 u8 hairpin[0x1];
2624 u8 reserved_at_f[0x11];
2625
2626 u8 reserved_at_20[0x8];
2627 u8 user_index[0x18];
2628
2629 u8 reserved_at_40[0x8];
2630 u8 cqn[0x18];
2631
2632 u8 reserved_at_60[0x8];
2633 u8 hairpin_peer_rq[0x18];
2634
2635 u8 reserved_at_80[0x10];
2636 u8 hairpin_peer_vhca[0x10];
2637
2638 u8 reserved_at_a0[0x50];
2639
2640 u8 packet_pacing_rate_limit_index[0x10];
2641 u8 tis_lst_sz[0x10];
2642 u8 reserved_at_110[0x10];
2643
2644 u8 reserved_at_120[0x40];
2645
2646 u8 reserved_at_160[0x8];
2647 u8 tis_num_0[0x18];
2648
2649 struct mlx5_ifc_wq_bits wq;
2650};
2651
2652enum {
2653 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2654 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2655 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2656 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2657};
2658
2659struct mlx5_ifc_scheduling_context_bits {
2660 u8 element_type[0x8];
2661 u8 reserved_at_8[0x18];
2662
2663 u8 element_attributes[0x20];
2664
2665 u8 parent_element_id[0x20];
2666
2667 u8 reserved_at_60[0x40];
2668
2669 u8 bw_share[0x20];
2670
2671 u8 max_average_bw[0x20];
2672
2673 u8 reserved_at_e0[0x120];
2674};
2675
2676struct mlx5_ifc_rqtc_bits {
2677 u8 reserved_at_0[0xa0];
2678
2679 u8 reserved_at_a0[0x10];
2680 u8 rqt_max_size[0x10];
2681
2682 u8 reserved_at_c0[0x10];
2683 u8 rqt_actual_size[0x10];
2684
2685 u8 reserved_at_e0[0x6a0];
2686
2687 struct mlx5_ifc_rq_num_bits rq_num[0];
2688};
2689
2690enum {
2691 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2692 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2693};
2694
2695enum {
2696 MLX5_RQC_STATE_RST = 0x0,
2697 MLX5_RQC_STATE_RDY = 0x1,
2698 MLX5_RQC_STATE_ERR = 0x3,
2699};
2700
2701struct mlx5_ifc_rqc_bits {
2702 u8 rlky[0x1];
2703 u8 delay_drop_en[0x1];
2704 u8 scatter_fcs[0x1];
2705 u8 vsd[0x1];
2706 u8 mem_rq_type[0x4];
2707 u8 state[0x4];
2708 u8 reserved_at_c[0x1];
2709 u8 flush_in_error_en[0x1];
2710 u8 hairpin[0x1];
2711 u8 reserved_at_f[0x11];
2712
2713 u8 reserved_at_20[0x8];
2714 u8 user_index[0x18];
2715
2716 u8 reserved_at_40[0x8];
2717 u8 cqn[0x18];
2718
2719 u8 counter_set_id[0x8];
2720 u8 reserved_at_68[0x18];
2721
2722 u8 reserved_at_80[0x8];
2723 u8 rmpn[0x18];
2724
2725 u8 reserved_at_a0[0x8];
2726 u8 hairpin_peer_sq[0x18];
2727
2728 u8 reserved_at_c0[0x10];
2729 u8 hairpin_peer_vhca[0x10];
2730
2731 u8 reserved_at_e0[0xa0];
2732
2733 struct mlx5_ifc_wq_bits wq;
2734};
2735
2736enum {
2737 MLX5_RMPC_STATE_RDY = 0x1,
2738 MLX5_RMPC_STATE_ERR = 0x3,
2739};
2740
2741struct mlx5_ifc_rmpc_bits {
2742 u8 reserved_at_0[0x8];
2743 u8 state[0x4];
2744 u8 reserved_at_c[0x14];
2745
2746 u8 basic_cyclic_rcv_wqe[0x1];
2747 u8 reserved_at_21[0x1f];
2748
2749 u8 reserved_at_40[0x140];
2750
2751 struct mlx5_ifc_wq_bits wq;
2752};
2753
2754struct mlx5_ifc_nic_vport_context_bits {
2755 u8 reserved_at_0[0x5];
2756 u8 min_wqe_inline_mode[0x3];
2757 u8 reserved_at_8[0x15];
2758 u8 disable_mc_local_lb[0x1];
2759 u8 disable_uc_local_lb[0x1];
2760 u8 roce_en[0x1];
2761
2762 u8 arm_change_event[0x1];
2763 u8 reserved_at_21[0x1a];
2764 u8 event_on_mtu[0x1];
2765 u8 event_on_promisc_change[0x1];
2766 u8 event_on_vlan_change[0x1];
2767 u8 event_on_mc_address_change[0x1];
2768 u8 event_on_uc_address_change[0x1];
2769
2770 u8 reserved_at_40[0xc];
2771
2772 u8 affiliation_criteria[0x4];
2773 u8 affiliated_vhca_id[0x10];
2774
2775 u8 reserved_at_60[0xd0];
2776
2777 u8 mtu[0x10];
2778
2779 u8 system_image_guid[0x40];
2780 u8 port_guid[0x40];
2781 u8 node_guid[0x40];
2782
2783 u8 reserved_at_200[0x140];
2784 u8 qkey_violation_counter[0x10];
2785 u8 reserved_at_350[0x430];
2786
2787 u8 promisc_uc[0x1];
2788 u8 promisc_mc[0x1];
2789 u8 promisc_all[0x1];
2790 u8 reserved_at_783[0x2];
2791 u8 allowed_list_type[0x3];
2792 u8 reserved_at_788[0xc];
2793 u8 allowed_list_size[0xc];
2794
2795 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2796
2797 u8 reserved_at_7e0[0x20];
2798
2799 u8 current_uc_mac_address[0][0x40];
2800};
2801
2802enum {
2803 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2804 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2805 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2806 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2807 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2808};
2809
2810struct mlx5_ifc_mkc_bits {
2811 u8 reserved_at_0[0x1];
2812 u8 free[0x1];
2813 u8 reserved_at_2[0x1];
2814 u8 access_mode_4_2[0x3];
2815 u8 reserved_at_6[0x7];
2816 u8 relaxed_ordering_write[0x1];
2817 u8 reserved_at_e[0x1];
2818 u8 small_fence_on_rdma_read_response[0x1];
2819 u8 umr_en[0x1];
2820 u8 a[0x1];
2821 u8 rw[0x1];
2822 u8 rr[0x1];
2823 u8 lw[0x1];
2824 u8 lr[0x1];
2825 u8 access_mode_1_0[0x2];
2826 u8 reserved_at_18[0x8];
2827
2828 u8 qpn[0x18];
2829 u8 mkey_7_0[0x8];
2830
2831 u8 reserved_at_40[0x20];
2832
2833 u8 length64[0x1];
2834 u8 bsf_en[0x1];
2835 u8 sync_umr[0x1];
2836 u8 reserved_at_63[0x2];
2837 u8 expected_sigerr_count[0x1];
2838 u8 reserved_at_66[0x1];
2839 u8 en_rinval[0x1];
2840 u8 pd[0x18];
2841
2842 u8 start_addr[0x40];
2843
2844 u8 len[0x40];
2845
2846 u8 bsf_octword_size[0x20];
2847
2848 u8 reserved_at_120[0x80];
2849
2850 u8 translations_octword_size[0x20];
2851
2852 u8 reserved_at_1c0[0x1b];
2853 u8 log_page_size[0x5];
2854
2855 u8 reserved_at_1e0[0x20];
2856};
2857
2858struct mlx5_ifc_pkey_bits {
2859 u8 reserved_at_0[0x10];
2860 u8 pkey[0x10];
2861};
2862
2863struct mlx5_ifc_array128_auto_bits {
2864 u8 array128_auto[16][0x8];
2865};
2866
2867struct mlx5_ifc_hca_vport_context_bits {
2868 u8 field_select[0x20];
2869
2870 u8 reserved_at_20[0xe0];
2871
2872 u8 sm_virt_aware[0x1];
2873 u8 has_smi[0x1];
2874 u8 has_raw[0x1];
2875 u8 grh_required[0x1];
2876 u8 reserved_at_104[0xc];
2877 u8 port_physical_state[0x4];
2878 u8 vport_state_policy[0x4];
2879 u8 port_state[0x4];
2880 u8 vport_state[0x4];
2881
2882 u8 reserved_at_120[0x20];
2883
2884 u8 system_image_guid[0x40];
2885
2886 u8 port_guid[0x40];
2887
2888 u8 node_guid[0x40];
2889
2890 u8 cap_mask1[0x20];
2891
2892 u8 cap_mask1_field_select[0x20];
2893
2894 u8 cap_mask2[0x20];
2895
2896 u8 cap_mask2_field_select[0x20];
2897
2898 u8 reserved_at_280[0x80];
2899
2900 u8 lid[0x10];
2901 u8 reserved_at_310[0x4];
2902 u8 init_type_reply[0x4];
2903 u8 lmc[0x3];
2904 u8 subnet_timeout[0x5];
2905
2906 u8 sm_lid[0x10];
2907 u8 sm_sl[0x4];
2908 u8 reserved_at_334[0xc];
2909
2910 u8 qkey_violation_counter[0x10];
2911 u8 pkey_violation_counter[0x10];
2912
2913 u8 reserved_at_360[0xca0];
2914};
2915
2916struct mlx5_ifc_esw_vport_context_bits {
2917 u8 reserved_at_0[0x3];
2918 u8 vport_svlan_strip[0x1];
2919 u8 vport_cvlan_strip[0x1];
2920 u8 vport_svlan_insert[0x1];
2921 u8 vport_cvlan_insert[0x2];
2922 u8 reserved_at_8[0x18];
2923
2924 u8 reserved_at_20[0x20];
2925
2926 u8 svlan_cfi[0x1];
2927 u8 svlan_pcp[0x3];
2928 u8 svlan_id[0xc];
2929 u8 cvlan_cfi[0x1];
2930 u8 cvlan_pcp[0x3];
2931 u8 cvlan_id[0xc];
2932
2933 u8 reserved_at_60[0x7a0];
2934};
2935
2936enum {
2937 MLX5_EQC_STATUS_OK = 0x0,
2938 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2939};
2940
2941enum {
2942 MLX5_EQC_ST_ARMED = 0x9,
2943 MLX5_EQC_ST_FIRED = 0xa,
2944};
2945
2946struct mlx5_ifc_eqc_bits {
2947 u8 status[0x4];
2948 u8 reserved_at_4[0x9];
2949 u8 ec[0x1];
2950 u8 oi[0x1];
2951 u8 reserved_at_f[0x5];
2952 u8 st[0x4];
2953 u8 reserved_at_18[0x8];
2954
2955 u8 reserved_at_20[0x20];
2956
2957 u8 reserved_at_40[0x14];
2958 u8 page_offset[0x6];
2959 u8 reserved_at_5a[0x6];
2960
2961 u8 reserved_at_60[0x3];
2962 u8 log_eq_size[0x5];
2963 u8 uar_page[0x18];
2964
2965 u8 reserved_at_80[0x20];
2966
2967 u8 reserved_at_a0[0x18];
2968 u8 intr[0x8];
2969
2970 u8 reserved_at_c0[0x3];
2971 u8 log_page_size[0x5];
2972 u8 reserved_at_c8[0x18];
2973
2974 u8 reserved_at_e0[0x60];
2975
2976 u8 reserved_at_140[0x8];
2977 u8 consumer_counter[0x18];
2978
2979 u8 reserved_at_160[0x8];
2980 u8 producer_counter[0x18];
2981
2982 u8 reserved_at_180[0x80];
2983};
2984
2985enum {
2986 MLX5_DCTC_STATE_ACTIVE = 0x0,
2987 MLX5_DCTC_STATE_DRAINING = 0x1,
2988 MLX5_DCTC_STATE_DRAINED = 0x2,
2989};
2990
2991enum {
2992 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2993 MLX5_DCTC_CS_RES_NA = 0x1,
2994 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2995};
2996
2997enum {
2998 MLX5_DCTC_MTU_256_BYTES = 0x1,
2999 MLX5_DCTC_MTU_512_BYTES = 0x2,
3000 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3001 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3002 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3003};
3004
3005struct mlx5_ifc_dctc_bits {
3006 u8 reserved_at_0[0x4];
3007 u8 state[0x4];
3008 u8 reserved_at_8[0x18];
3009
3010 u8 reserved_at_20[0x8];
3011 u8 user_index[0x18];
3012
3013 u8 reserved_at_40[0x8];
3014 u8 cqn[0x18];
3015
3016 u8 counter_set_id[0x8];
3017 u8 atomic_mode[0x4];
3018 u8 rre[0x1];
3019 u8 rwe[0x1];
3020 u8 rae[0x1];
3021 u8 atomic_like_write_en[0x1];
3022 u8 latency_sensitive[0x1];
3023 u8 rlky[0x1];
3024 u8 free_ar[0x1];
3025 u8 reserved_at_73[0xd];
3026
3027 u8 reserved_at_80[0x8];
3028 u8 cs_res[0x8];
3029 u8 reserved_at_90[0x3];
3030 u8 min_rnr_nak[0x5];
3031 u8 reserved_at_98[0x8];
3032
3033 u8 reserved_at_a0[0x8];
3034 u8 srqn_xrqn[0x18];
3035
3036 u8 reserved_at_c0[0x8];
3037 u8 pd[0x18];
3038
3039 u8 tclass[0x8];
3040 u8 reserved_at_e8[0x4];
3041 u8 flow_label[0x14];
3042
3043 u8 dc_access_key[0x40];
3044
3045 u8 reserved_at_140[0x5];
3046 u8 mtu[0x3];
3047 u8 port[0x8];
3048 u8 pkey_index[0x10];
3049
3050 u8 reserved_at_160[0x8];
3051 u8 my_addr_index[0x8];
3052 u8 reserved_at_170[0x8];
3053 u8 hop_limit[0x8];
3054
3055 u8 dc_access_key_violation_count[0x20];
3056
3057 u8 reserved_at_1a0[0x14];
3058 u8 dei_cfi[0x1];
3059 u8 eth_prio[0x3];
3060 u8 ecn[0x2];
3061 u8 dscp[0x6];
3062
3063 u8 reserved_at_1c0[0x40];
3064};
3065
3066enum {
3067 MLX5_CQC_STATUS_OK = 0x0,
3068 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3069 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3070};
3071
3072enum {
3073 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3074 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3075};
3076
3077enum {
3078 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3079 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3080 MLX5_CQC_ST_FIRED = 0xa,
3081};
3082
3083enum {
3084 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3085 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3086 MLX5_CQ_PERIOD_NUM_MODES
3087};
3088
3089struct mlx5_ifc_cqc_bits {
3090 u8 status[0x4];
3091 u8 reserved_at_4[0x4];
3092 u8 cqe_sz[0x3];
3093 u8 cc[0x1];
3094 u8 reserved_at_c[0x1];
3095 u8 scqe_break_moderation_en[0x1];
3096 u8 oi[0x1];
3097 u8 cq_period_mode[0x2];
3098 u8 cqe_comp_en[0x1];
3099 u8 mini_cqe_res_format[0x2];
3100 u8 st[0x4];
3101 u8 reserved_at_18[0x8];
3102
3103 u8 reserved_at_20[0x20];
3104
3105 u8 reserved_at_40[0x14];
3106 u8 page_offset[0x6];
3107 u8 reserved_at_5a[0x6];
3108
3109 u8 reserved_at_60[0x3];
3110 u8 log_cq_size[0x5];
3111 u8 uar_page[0x18];
3112
3113 u8 reserved_at_80[0x4];
3114 u8 cq_period[0xc];
3115 u8 cq_max_count[0x10];
3116
3117 u8 reserved_at_a0[0x18];
3118 u8 c_eqn[0x8];
3119
3120 u8 reserved_at_c0[0x3];
3121 u8 log_page_size[0x5];
3122 u8 reserved_at_c8[0x18];
3123
3124 u8 reserved_at_e0[0x20];
3125
3126 u8 reserved_at_100[0x8];
3127 u8 last_notified_index[0x18];
3128
3129 u8 reserved_at_120[0x8];
3130 u8 last_solicit_index[0x18];
3131
3132 u8 reserved_at_140[0x8];
3133 u8 consumer_counter[0x18];
3134
3135 u8 reserved_at_160[0x8];
3136 u8 producer_counter[0x18];
3137
3138 u8 reserved_at_180[0x40];
3139
3140 u8 dbr_addr[0x40];
3141};
3142
3143union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3144 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3145 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3146 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3147 u8 reserved_at_0[0x800];
3148};
3149
3150struct mlx5_ifc_query_adapter_param_block_bits {
3151 u8 reserved_at_0[0xc0];
3152
3153 u8 reserved_at_c0[0x8];
3154 u8 ieee_vendor_id[0x18];
3155
3156 u8 reserved_at_e0[0x10];
3157 u8 vsd_vendor_id[0x10];
3158
3159 u8 vsd[208][0x8];
3160
3161 u8 vsd_contd_psid[16][0x8];
3162};
3163
3164enum {
3165 MLX5_XRQC_STATE_GOOD = 0x0,
3166 MLX5_XRQC_STATE_ERROR = 0x1,
3167};
3168
3169enum {
3170 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3171 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3172};
3173
3174enum {
3175 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3176};
3177
3178struct mlx5_ifc_tag_matching_topology_context_bits {
3179 u8 log_matching_list_sz[0x4];
3180 u8 reserved_at_4[0xc];
3181 u8 append_next_index[0x10];
3182
3183 u8 sw_phase_cnt[0x10];
3184 u8 hw_phase_cnt[0x10];
3185
3186 u8 reserved_at_40[0x40];
3187};
3188
3189struct mlx5_ifc_xrqc_bits {
3190 u8 state[0x4];
3191 u8 rlkey[0x1];
3192 u8 reserved_at_5[0xf];
3193 u8 topology[0x4];
3194 u8 reserved_at_18[0x4];
3195 u8 offload[0x4];
3196
3197 u8 reserved_at_20[0x8];
3198 u8 user_index[0x18];
3199
3200 u8 reserved_at_40[0x8];
3201 u8 cqn[0x18];
3202
3203 u8 reserved_at_60[0xa0];
3204
3205 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3206
3207 u8 reserved_at_180[0x280];
3208
3209 struct mlx5_ifc_wq_bits wq;
3210};
3211
3212union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3213 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3214 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3215 u8 reserved_at_0[0x20];
3216};
3217
3218union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3219 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3220 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3221 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3222 u8 reserved_at_0[0x20];
3223};
3224
3225union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3226 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3227 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3228 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3229 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3230 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3231 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3232 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3233 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3234 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3235 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3236 u8 reserved_at_0[0x7c0];
3237};
3238
3239union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3240 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3241 u8 reserved_at_0[0x7c0];
3242};
3243
3244union mlx5_ifc_event_auto_bits {
3245 struct mlx5_ifc_comp_event_bits comp_event;
3246 struct mlx5_ifc_dct_events_bits dct_events;
3247 struct mlx5_ifc_qp_events_bits qp_events;
3248 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3249 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3250 struct mlx5_ifc_cq_error_bits cq_error;
3251 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3252 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3253 struct mlx5_ifc_gpio_event_bits gpio_event;
3254 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3255 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3256 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3257 u8 reserved_at_0[0xe0];
3258};
3259
3260struct mlx5_ifc_health_buffer_bits {
3261 u8 reserved_at_0[0x100];
3262
3263 u8 assert_existptr[0x20];
3264
3265 u8 assert_callra[0x20];
3266
3267 u8 reserved_at_140[0x40];
3268
3269 u8 fw_version[0x20];
3270
3271 u8 hw_id[0x20];
3272
3273 u8 reserved_at_1c0[0x20];
3274
3275 u8 irisc_index[0x8];
3276 u8 synd[0x8];
3277 u8 ext_synd[0x10];
3278};
3279
3280struct mlx5_ifc_register_loopback_control_bits {
3281 u8 no_lb[0x1];
3282 u8 reserved_at_1[0x7];
3283 u8 port[0x8];
3284 u8 reserved_at_10[0x10];
3285
3286 u8 reserved_at_20[0x60];
3287};
3288
3289struct mlx5_ifc_vport_tc_element_bits {
3290 u8 traffic_class[0x4];
3291 u8 reserved_at_4[0xc];
3292 u8 vport_number[0x10];
3293};
3294
3295struct mlx5_ifc_vport_element_bits {
3296 u8 reserved_at_0[0x10];
3297 u8 vport_number[0x10];
3298};
3299
3300enum {
3301 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3302 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3303 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3304};
3305
3306struct mlx5_ifc_tsar_element_bits {
3307 u8 reserved_at_0[0x8];
3308 u8 tsar_type[0x8];
3309 u8 reserved_at_10[0x10];
3310};
3311
3312enum {
3313 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3314 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3315};
3316
3317struct mlx5_ifc_teardown_hca_out_bits {
3318 u8 status[0x8];
3319 u8 reserved_at_8[0x18];
3320
3321 u8 syndrome[0x20];
3322
3323 u8 reserved_at_40[0x3f];
3324
3325 u8 state[0x1];
3326};
3327
3328enum {
3329 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3330 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3331 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3332};
3333
3334struct mlx5_ifc_teardown_hca_in_bits {
3335 u8 opcode[0x10];
3336 u8 reserved_at_10[0x10];
3337
3338 u8 reserved_at_20[0x10];
3339 u8 op_mod[0x10];
3340
3341 u8 reserved_at_40[0x10];
3342 u8 profile[0x10];
3343
3344 u8 reserved_at_60[0x20];
3345};
3346
3347struct mlx5_ifc_sqerr2rts_qp_out_bits {
3348 u8 status[0x8];
3349 u8 reserved_at_8[0x18];
3350
3351 u8 syndrome[0x20];
3352
3353 u8 reserved_at_40[0x40];
3354};
3355
3356struct mlx5_ifc_sqerr2rts_qp_in_bits {
3357 u8 opcode[0x10];
3358 u8 reserved_at_10[0x10];
3359
3360 u8 reserved_at_20[0x10];
3361 u8 op_mod[0x10];
3362
3363 u8 reserved_at_40[0x8];
3364 u8 qpn[0x18];
3365
3366 u8 reserved_at_60[0x20];
3367
3368 u8 opt_param_mask[0x20];
3369
3370 u8 reserved_at_a0[0x20];
3371
3372 struct mlx5_ifc_qpc_bits qpc;
3373
3374 u8 reserved_at_800[0x80];
3375};
3376
3377struct mlx5_ifc_sqd2rts_qp_out_bits {
3378 u8 status[0x8];
3379 u8 reserved_at_8[0x18];
3380
3381 u8 syndrome[0x20];
3382
3383 u8 reserved_at_40[0x40];
3384};
3385
3386struct mlx5_ifc_sqd2rts_qp_in_bits {
3387 u8 opcode[0x10];
3388 u8 reserved_at_10[0x10];
3389
3390 u8 reserved_at_20[0x10];
3391 u8 op_mod[0x10];
3392
3393 u8 reserved_at_40[0x8];
3394 u8 qpn[0x18];
3395
3396 u8 reserved_at_60[0x20];
3397
3398 u8 opt_param_mask[0x20];
3399
3400 u8 reserved_at_a0[0x20];
3401
3402 struct mlx5_ifc_qpc_bits qpc;
3403
3404 u8 reserved_at_800[0x80];
3405};
3406
3407struct mlx5_ifc_set_roce_address_out_bits {
3408 u8 status[0x8];
3409 u8 reserved_at_8[0x18];
3410
3411 u8 syndrome[0x20];
3412
3413 u8 reserved_at_40[0x40];
3414};
3415
3416struct mlx5_ifc_set_roce_address_in_bits {
3417 u8 opcode[0x10];
3418 u8 reserved_at_10[0x10];
3419
3420 u8 reserved_at_20[0x10];
3421 u8 op_mod[0x10];
3422
3423 u8 roce_address_index[0x10];
3424 u8 reserved_at_50[0xc];
3425 u8 vhca_port_num[0x4];
3426
3427 u8 reserved_at_60[0x20];
3428
3429 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3430};
3431
3432struct mlx5_ifc_set_mad_demux_out_bits {
3433 u8 status[0x8];
3434 u8 reserved_at_8[0x18];
3435
3436 u8 syndrome[0x20];
3437
3438 u8 reserved_at_40[0x40];
3439};
3440
3441enum {
3442 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3443 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3444};
3445
3446struct mlx5_ifc_set_mad_demux_in_bits {
3447 u8 opcode[0x10];
3448 u8 reserved_at_10[0x10];
3449
3450 u8 reserved_at_20[0x10];
3451 u8 op_mod[0x10];
3452
3453 u8 reserved_at_40[0x20];
3454
3455 u8 reserved_at_60[0x6];
3456 u8 demux_mode[0x2];
3457 u8 reserved_at_68[0x18];
3458};
3459
3460struct mlx5_ifc_set_l2_table_entry_out_bits {
3461 u8 status[0x8];
3462 u8 reserved_at_8[0x18];
3463
3464 u8 syndrome[0x20];
3465
3466 u8 reserved_at_40[0x40];
3467};
3468
3469struct mlx5_ifc_set_l2_table_entry_in_bits {
3470 u8 opcode[0x10];
3471 u8 reserved_at_10[0x10];
3472
3473 u8 reserved_at_20[0x10];
3474 u8 op_mod[0x10];
3475
3476 u8 reserved_at_40[0x60];
3477
3478 u8 reserved_at_a0[0x8];
3479 u8 table_index[0x18];
3480
3481 u8 reserved_at_c0[0x20];
3482
3483 u8 reserved_at_e0[0x13];
3484 u8 vlan_valid[0x1];
3485 u8 vlan[0xc];
3486
3487 struct mlx5_ifc_mac_address_layout_bits mac_address;
3488
3489 u8 reserved_at_140[0xc0];
3490};
3491
3492struct mlx5_ifc_set_issi_out_bits {
3493 u8 status[0x8];
3494 u8 reserved_at_8[0x18];
3495
3496 u8 syndrome[0x20];
3497
3498 u8 reserved_at_40[0x40];
3499};
3500
3501struct mlx5_ifc_set_issi_in_bits {
3502 u8 opcode[0x10];
3503 u8 reserved_at_10[0x10];
3504
3505 u8 reserved_at_20[0x10];
3506 u8 op_mod[0x10];
3507
3508 u8 reserved_at_40[0x10];
3509 u8 current_issi[0x10];
3510
3511 u8 reserved_at_60[0x20];
3512};
3513
3514struct mlx5_ifc_set_hca_cap_out_bits {
3515 u8 status[0x8];
3516 u8 reserved_at_8[0x18];
3517
3518 u8 syndrome[0x20];
3519
3520 u8 reserved_at_40[0x40];
3521};
3522
3523struct mlx5_ifc_set_hca_cap_in_bits {
3524 u8 opcode[0x10];
3525 u8 reserved_at_10[0x10];
3526
3527 u8 reserved_at_20[0x10];
3528 u8 op_mod[0x10];
3529
3530 u8 reserved_at_40[0x40];
3531
3532 union mlx5_ifc_hca_cap_union_bits capability;
3533};
3534
3535enum {
3536 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3537 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3538 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3539 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3540};
3541
3542struct mlx5_ifc_set_fte_out_bits {
3543 u8 status[0x8];
3544 u8 reserved_at_8[0x18];
3545
3546 u8 syndrome[0x20];
3547
3548 u8 reserved_at_40[0x40];
3549};
3550
3551struct mlx5_ifc_set_fte_in_bits {
3552 u8 opcode[0x10];
3553 u8 reserved_at_10[0x10];
3554
3555 u8 reserved_at_20[0x10];
3556 u8 op_mod[0x10];
3557
3558 u8 other_vport[0x1];
3559 u8 reserved_at_41[0xf];
3560 u8 vport_number[0x10];
3561
3562 u8 reserved_at_60[0x20];
3563
3564 u8 table_type[0x8];
3565 u8 reserved_at_88[0x18];
3566
3567 u8 reserved_at_a0[0x8];
3568 u8 table_id[0x18];
3569
3570 u8 reserved_at_c0[0x18];
3571 u8 modify_enable_mask[0x8];
3572
3573 u8 reserved_at_e0[0x20];
3574
3575 u8 flow_index[0x20];
3576
3577 u8 reserved_at_120[0xe0];
3578
3579 struct mlx5_ifc_flow_context_bits flow_context;
3580};
3581
3582struct mlx5_ifc_rts2rts_qp_out_bits {
3583 u8 status[0x8];
3584 u8 reserved_at_8[0x18];
3585
3586 u8 syndrome[0x20];
3587
3588 u8 reserved_at_40[0x40];
3589};
3590
3591struct mlx5_ifc_rts2rts_qp_in_bits {
3592 u8 opcode[0x10];
3593 u8 reserved_at_10[0x10];
3594
3595 u8 reserved_at_20[0x10];
3596 u8 op_mod[0x10];
3597
3598 u8 reserved_at_40[0x8];
3599 u8 qpn[0x18];
3600
3601 u8 reserved_at_60[0x20];
3602
3603 u8 opt_param_mask[0x20];
3604
3605 u8 reserved_at_a0[0x20];
3606
3607 struct mlx5_ifc_qpc_bits qpc;
3608
3609 u8 reserved_at_800[0x80];
3610};
3611
3612struct mlx5_ifc_rtr2rts_qp_out_bits {
3613 u8 status[0x8];
3614 u8 reserved_at_8[0x18];
3615
3616 u8 syndrome[0x20];
3617
3618 u8 reserved_at_40[0x40];
3619};
3620
3621struct mlx5_ifc_rtr2rts_qp_in_bits {
3622 u8 opcode[0x10];
3623 u8 reserved_at_10[0x10];
3624
3625 u8 reserved_at_20[0x10];
3626 u8 op_mod[0x10];
3627
3628 u8 reserved_at_40[0x8];
3629 u8 qpn[0x18];
3630
3631 u8 reserved_at_60[0x20];
3632
3633 u8 opt_param_mask[0x20];
3634
3635 u8 reserved_at_a0[0x20];
3636
3637 struct mlx5_ifc_qpc_bits qpc;
3638
3639 u8 reserved_at_800[0x80];
3640};
3641
3642struct mlx5_ifc_rst2init_qp_out_bits {
3643 u8 status[0x8];
3644 u8 reserved_at_8[0x18];
3645
3646 u8 syndrome[0x20];
3647
3648 u8 reserved_at_40[0x40];
3649};
3650
3651struct mlx5_ifc_rst2init_qp_in_bits {
3652 u8 opcode[0x10];
3653 u8 reserved_at_10[0x10];
3654
3655 u8 reserved_at_20[0x10];
3656 u8 op_mod[0x10];
3657
3658 u8 reserved_at_40[0x8];
3659 u8 qpn[0x18];
3660
3661 u8 reserved_at_60[0x20];
3662
3663 u8 opt_param_mask[0x20];
3664
3665 u8 reserved_at_a0[0x20];
3666
3667 struct mlx5_ifc_qpc_bits qpc;
3668
3669 u8 reserved_at_800[0x80];
3670};
3671
3672struct mlx5_ifc_query_xrq_out_bits {
3673 u8 status[0x8];
3674 u8 reserved_at_8[0x18];
3675
3676 u8 syndrome[0x20];
3677
3678 u8 reserved_at_40[0x40];
3679
3680 struct mlx5_ifc_xrqc_bits xrq_context;
3681};
3682
3683struct mlx5_ifc_query_xrq_in_bits {
3684 u8 opcode[0x10];
3685 u8 reserved_at_10[0x10];
3686
3687 u8 reserved_at_20[0x10];
3688 u8 op_mod[0x10];
3689
3690 u8 reserved_at_40[0x8];
3691 u8 xrqn[0x18];
3692
3693 u8 reserved_at_60[0x20];
3694};
3695
3696struct mlx5_ifc_query_xrc_srq_out_bits {
3697 u8 status[0x8];
3698 u8 reserved_at_8[0x18];
3699
3700 u8 syndrome[0x20];
3701
3702 u8 reserved_at_40[0x40];
3703
3704 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3705
3706 u8 reserved_at_280[0x600];
3707
3708 u8 pas[0][0x40];
3709};
3710
3711struct mlx5_ifc_query_xrc_srq_in_bits {
3712 u8 opcode[0x10];
3713 u8 reserved_at_10[0x10];
3714
3715 u8 reserved_at_20[0x10];
3716 u8 op_mod[0x10];
3717
3718 u8 reserved_at_40[0x8];
3719 u8 xrc_srqn[0x18];
3720
3721 u8 reserved_at_60[0x20];
3722};
3723
3724enum {
3725 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3726 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3727};
3728
3729struct mlx5_ifc_query_vport_state_out_bits {
3730 u8 status[0x8];
3731 u8 reserved_at_8[0x18];
3732
3733 u8 syndrome[0x20];
3734
3735 u8 reserved_at_40[0x20];
3736
3737 u8 reserved_at_60[0x18];
3738 u8 admin_state[0x4];
3739 u8 state[0x4];
3740};
3741
3742enum {
3743 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3744 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3745};
3746
3747struct mlx5_ifc_query_vport_state_in_bits {
3748 u8 opcode[0x10];
3749 u8 reserved_at_10[0x10];
3750
3751 u8 reserved_at_20[0x10];
3752 u8 op_mod[0x10];
3753
3754 u8 other_vport[0x1];
3755 u8 reserved_at_41[0xf];
3756 u8 vport_number[0x10];
3757
3758 u8 reserved_at_60[0x20];
3759};
3760
3761struct mlx5_ifc_query_vnic_env_out_bits {
3762 u8 status[0x8];
3763 u8 reserved_at_8[0x18];
3764
3765 u8 syndrome[0x20];
3766
3767 u8 reserved_at_40[0x40];
3768
3769 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3770};
3771
3772enum {
3773 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3774};
3775
3776struct mlx5_ifc_query_vnic_env_in_bits {
3777 u8 opcode[0x10];
3778 u8 reserved_at_10[0x10];
3779
3780 u8 reserved_at_20[0x10];
3781 u8 op_mod[0x10];
3782
3783 u8 other_vport[0x1];
3784 u8 reserved_at_41[0xf];
3785 u8 vport_number[0x10];
3786
3787 u8 reserved_at_60[0x20];
3788};
3789
3790struct mlx5_ifc_query_vport_counter_out_bits {
3791 u8 status[0x8];
3792 u8 reserved_at_8[0x18];
3793
3794 u8 syndrome[0x20];
3795
3796 u8 reserved_at_40[0x40];
3797
3798 struct mlx5_ifc_traffic_counter_bits received_errors;
3799
3800 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3801
3802 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3803
3804 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3805
3806 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3807
3808 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3809
3810 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3811
3812 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3813
3814 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3815
3816 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3817
3818 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3819
3820 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3821
3822 u8 reserved_at_680[0xa00];
3823};
3824
3825enum {
3826 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3827};
3828
3829struct mlx5_ifc_query_vport_counter_in_bits {
3830 u8 opcode[0x10];
3831 u8 reserved_at_10[0x10];
3832
3833 u8 reserved_at_20[0x10];
3834 u8 op_mod[0x10];
3835
3836 u8 other_vport[0x1];
3837 u8 reserved_at_41[0xb];
3838 u8 port_num[0x4];
3839 u8 vport_number[0x10];
3840
3841 u8 reserved_at_60[0x60];
3842
3843 u8 clear[0x1];
3844 u8 reserved_at_c1[0x1f];
3845
3846 u8 reserved_at_e0[0x20];
3847};
3848
3849struct mlx5_ifc_query_tis_out_bits {
3850 u8 status[0x8];
3851 u8 reserved_at_8[0x18];
3852
3853 u8 syndrome[0x20];
3854
3855 u8 reserved_at_40[0x40];
3856
3857 struct mlx5_ifc_tisc_bits tis_context;
3858};
3859
3860struct mlx5_ifc_query_tis_in_bits {
3861 u8 opcode[0x10];
3862 u8 reserved_at_10[0x10];
3863
3864 u8 reserved_at_20[0x10];
3865 u8 op_mod[0x10];
3866
3867 u8 reserved_at_40[0x8];
3868 u8 tisn[0x18];
3869
3870 u8 reserved_at_60[0x20];
3871};
3872
3873struct mlx5_ifc_query_tir_out_bits {
3874 u8 status[0x8];
3875 u8 reserved_at_8[0x18];
3876
3877 u8 syndrome[0x20];
3878
3879 u8 reserved_at_40[0xc0];
3880
3881 struct mlx5_ifc_tirc_bits tir_context;
3882};
3883
3884struct mlx5_ifc_query_tir_in_bits {
3885 u8 opcode[0x10];
3886 u8 reserved_at_10[0x10];
3887
3888 u8 reserved_at_20[0x10];
3889 u8 op_mod[0x10];
3890
3891 u8 reserved_at_40[0x8];
3892 u8 tirn[0x18];
3893
3894 u8 reserved_at_60[0x20];
3895};
3896
3897struct mlx5_ifc_query_srq_out_bits {
3898 u8 status[0x8];
3899 u8 reserved_at_8[0x18];
3900
3901 u8 syndrome[0x20];
3902
3903 u8 reserved_at_40[0x40];
3904
3905 struct mlx5_ifc_srqc_bits srq_context_entry;
3906
3907 u8 reserved_at_280[0x600];
3908
3909 u8 pas[0][0x40];
3910};
3911
3912struct mlx5_ifc_query_srq_in_bits {
3913 u8 opcode[0x10];
3914 u8 reserved_at_10[0x10];
3915
3916 u8 reserved_at_20[0x10];
3917 u8 op_mod[0x10];
3918
3919 u8 reserved_at_40[0x8];
3920 u8 srqn[0x18];
3921
3922 u8 reserved_at_60[0x20];
3923};
3924
3925struct mlx5_ifc_query_sq_out_bits {
3926 u8 status[0x8];
3927 u8 reserved_at_8[0x18];
3928
3929 u8 syndrome[0x20];
3930
3931 u8 reserved_at_40[0xc0];
3932
3933 struct mlx5_ifc_sqc_bits sq_context;
3934};
3935
3936struct mlx5_ifc_query_sq_in_bits {
3937 u8 opcode[0x10];
3938 u8 reserved_at_10[0x10];
3939
3940 u8 reserved_at_20[0x10];
3941 u8 op_mod[0x10];
3942
3943 u8 reserved_at_40[0x8];
3944 u8 sqn[0x18];
3945
3946 u8 reserved_at_60[0x20];
3947};
3948
3949struct mlx5_ifc_query_special_contexts_out_bits {
3950 u8 status[0x8];
3951 u8 reserved_at_8[0x18];
3952
3953 u8 syndrome[0x20];
3954
3955 u8 dump_fill_mkey[0x20];
3956
3957 u8 resd_lkey[0x20];
3958
3959 u8 null_mkey[0x20];
3960
3961 u8 reserved_at_a0[0x60];
3962};
3963
3964struct mlx5_ifc_query_special_contexts_in_bits {
3965 u8 opcode[0x10];
3966 u8 reserved_at_10[0x10];
3967
3968 u8 reserved_at_20[0x10];
3969 u8 op_mod[0x10];
3970
3971 u8 reserved_at_40[0x40];
3972};
3973
3974struct mlx5_ifc_query_scheduling_element_out_bits {
3975 u8 opcode[0x10];
3976 u8 reserved_at_10[0x10];
3977
3978 u8 reserved_at_20[0x10];
3979 u8 op_mod[0x10];
3980
3981 u8 reserved_at_40[0xc0];
3982
3983 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3984
3985 u8 reserved_at_300[0x100];
3986};
3987
3988enum {
3989 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3990};
3991
3992struct mlx5_ifc_query_scheduling_element_in_bits {
3993 u8 opcode[0x10];
3994 u8 reserved_at_10[0x10];
3995
3996 u8 reserved_at_20[0x10];
3997 u8 op_mod[0x10];
3998
3999 u8 scheduling_hierarchy[0x8];
4000 u8 reserved_at_48[0x18];
4001
4002 u8 scheduling_element_id[0x20];
4003
4004 u8 reserved_at_80[0x180];
4005};
4006
4007struct mlx5_ifc_query_rqt_out_bits {
4008 u8 status[0x8];
4009 u8 reserved_at_8[0x18];
4010
4011 u8 syndrome[0x20];
4012
4013 u8 reserved_at_40[0xc0];
4014
4015 struct mlx5_ifc_rqtc_bits rqt_context;
4016};
4017
4018struct mlx5_ifc_query_rqt_in_bits {
4019 u8 opcode[0x10];
4020 u8 reserved_at_10[0x10];
4021
4022 u8 reserved_at_20[0x10];
4023 u8 op_mod[0x10];
4024
4025 u8 reserved_at_40[0x8];
4026 u8 rqtn[0x18];
4027
4028 u8 reserved_at_60[0x20];
4029};
4030
4031struct mlx5_ifc_query_rq_out_bits {
4032 u8 status[0x8];
4033 u8 reserved_at_8[0x18];
4034
4035 u8 syndrome[0x20];
4036
4037 u8 reserved_at_40[0xc0];
4038
4039 struct mlx5_ifc_rqc_bits rq_context;
4040};
4041
4042struct mlx5_ifc_query_rq_in_bits {
4043 u8 opcode[0x10];
4044 u8 reserved_at_10[0x10];
4045
4046 u8 reserved_at_20[0x10];
4047 u8 op_mod[0x10];
4048
4049 u8 reserved_at_40[0x8];
4050 u8 rqn[0x18];
4051
4052 u8 reserved_at_60[0x20];
4053};
4054
4055struct mlx5_ifc_query_roce_address_out_bits {
4056 u8 status[0x8];
4057 u8 reserved_at_8[0x18];
4058
4059 u8 syndrome[0x20];
4060
4061 u8 reserved_at_40[0x40];
4062
4063 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4064};
4065
4066struct mlx5_ifc_query_roce_address_in_bits {
4067 u8 opcode[0x10];
4068 u8 reserved_at_10[0x10];
4069
4070 u8 reserved_at_20[0x10];
4071 u8 op_mod[0x10];
4072
4073 u8 roce_address_index[0x10];
4074 u8 reserved_at_50[0xc];
4075 u8 vhca_port_num[0x4];
4076
4077 u8 reserved_at_60[0x20];
4078};
4079
4080struct mlx5_ifc_query_rmp_out_bits {
4081 u8 status[0x8];
4082 u8 reserved_at_8[0x18];
4083
4084 u8 syndrome[0x20];
4085
4086 u8 reserved_at_40[0xc0];
4087
4088 struct mlx5_ifc_rmpc_bits rmp_context;
4089};
4090
4091struct mlx5_ifc_query_rmp_in_bits {
4092 u8 opcode[0x10];
4093 u8 reserved_at_10[0x10];
4094
4095 u8 reserved_at_20[0x10];
4096 u8 op_mod[0x10];
4097
4098 u8 reserved_at_40[0x8];
4099 u8 rmpn[0x18];
4100
4101 u8 reserved_at_60[0x20];
4102};
4103
4104struct mlx5_ifc_query_qp_out_bits {
4105 u8 status[0x8];
4106 u8 reserved_at_8[0x18];
4107
4108 u8 syndrome[0x20];
4109
4110 u8 reserved_at_40[0x40];
4111
4112 u8 opt_param_mask[0x20];
4113
4114 u8 reserved_at_a0[0x20];
4115
4116 struct mlx5_ifc_qpc_bits qpc;
4117
4118 u8 reserved_at_800[0x80];
4119
4120 u8 pas[0][0x40];
4121};
4122
4123struct mlx5_ifc_query_qp_in_bits {
4124 u8 opcode[0x10];
4125 u8 reserved_at_10[0x10];
4126
4127 u8 reserved_at_20[0x10];
4128 u8 op_mod[0x10];
4129
4130 u8 reserved_at_40[0x8];
4131 u8 qpn[0x18];
4132
4133 u8 reserved_at_60[0x20];
4134};
4135
4136struct mlx5_ifc_query_q_counter_out_bits {
4137 u8 status[0x8];
4138 u8 reserved_at_8[0x18];
4139
4140 u8 syndrome[0x20];
4141
4142 u8 reserved_at_40[0x40];
4143
4144 u8 rx_write_requests[0x20];
4145
4146 u8 reserved_at_a0[0x20];
4147
4148 u8 rx_read_requests[0x20];
4149
4150 u8 reserved_at_e0[0x20];
4151
4152 u8 rx_atomic_requests[0x20];
4153
4154 u8 reserved_at_120[0x20];
4155
4156 u8 rx_dct_connect[0x20];
4157
4158 u8 reserved_at_160[0x20];
4159
4160 u8 out_of_buffer[0x20];
4161
4162 u8 reserved_at_1a0[0x20];
4163
4164 u8 out_of_sequence[0x20];
4165
4166 u8 reserved_at_1e0[0x20];
4167
4168 u8 duplicate_request[0x20];
4169
4170 u8 reserved_at_220[0x20];
4171
4172 u8 rnr_nak_retry_err[0x20];
4173
4174 u8 reserved_at_260[0x20];
4175
4176 u8 packet_seq_err[0x20];
4177
4178 u8 reserved_at_2a0[0x20];
4179
4180 u8 implied_nak_seq_err[0x20];
4181
4182 u8 reserved_at_2e0[0x20];
4183
4184 u8 local_ack_timeout_err[0x20];
4185
4186 u8 reserved_at_320[0xa0];
4187
4188 u8 resp_local_length_error[0x20];
4189
4190 u8 req_local_length_error[0x20];
4191
4192 u8 resp_local_qp_error[0x20];
4193
4194 u8 local_operation_error[0x20];
4195
4196 u8 resp_local_protection[0x20];
4197
4198 u8 req_local_protection[0x20];
4199
4200 u8 resp_cqe_error[0x20];
4201
4202 u8 req_cqe_error[0x20];
4203
4204 u8 req_mw_binding[0x20];
4205
4206 u8 req_bad_response[0x20];
4207
4208 u8 req_remote_invalid_request[0x20];
4209
4210 u8 resp_remote_invalid_request[0x20];
4211
4212 u8 req_remote_access_errors[0x20];
4213
4214 u8 resp_remote_access_errors[0x20];
4215
4216 u8 req_remote_operation_errors[0x20];
4217
4218 u8 req_transport_retries_exceeded[0x20];
4219
4220 u8 cq_overflow[0x20];
4221
4222 u8 resp_cqe_flush_error[0x20];
4223
4224 u8 req_cqe_flush_error[0x20];
4225
4226 u8 reserved_at_620[0x1e0];
4227};
4228
4229struct mlx5_ifc_query_q_counter_in_bits {
4230 u8 opcode[0x10];
4231 u8 reserved_at_10[0x10];
4232
4233 u8 reserved_at_20[0x10];
4234 u8 op_mod[0x10];
4235
4236 u8 reserved_at_40[0x80];
4237
4238 u8 clear[0x1];
4239 u8 reserved_at_c1[0x1f];
4240
4241 u8 reserved_at_e0[0x18];
4242 u8 counter_set_id[0x8];
4243};
4244
4245struct mlx5_ifc_query_pages_out_bits {
4246 u8 status[0x8];
4247 u8 reserved_at_8[0x18];
4248
4249 u8 syndrome[0x20];
4250
4251 u8 reserved_at_40[0x10];
4252 u8 function_id[0x10];
4253
4254 u8 num_pages[0x20];
4255};
4256
4257enum {
4258 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4259 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4260 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4261};
4262
4263struct mlx5_ifc_query_pages_in_bits {
4264 u8 opcode[0x10];
4265 u8 reserved_at_10[0x10];
4266
4267 u8 reserved_at_20[0x10];
4268 u8 op_mod[0x10];
4269
4270 u8 reserved_at_40[0x10];
4271 u8 function_id[0x10];
4272
4273 u8 reserved_at_60[0x20];
4274};
4275
4276struct mlx5_ifc_query_nic_vport_context_out_bits {
4277 u8 status[0x8];
4278 u8 reserved_at_8[0x18];
4279
4280 u8 syndrome[0x20];
4281
4282 u8 reserved_at_40[0x40];
4283
4284 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4285};
4286
4287struct mlx5_ifc_query_nic_vport_context_in_bits {
4288 u8 opcode[0x10];
4289 u8 reserved_at_10[0x10];
4290
4291 u8 reserved_at_20[0x10];
4292 u8 op_mod[0x10];
4293
4294 u8 other_vport[0x1];
4295 u8 reserved_at_41[0xf];
4296 u8 vport_number[0x10];
4297
4298 u8 reserved_at_60[0x5];
4299 u8 allowed_list_type[0x3];
4300 u8 reserved_at_68[0x18];
4301};
4302
4303struct mlx5_ifc_query_mkey_out_bits {
4304 u8 status[0x8];
4305 u8 reserved_at_8[0x18];
4306
4307 u8 syndrome[0x20];
4308
4309 u8 reserved_at_40[0x40];
4310
4311 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4312
4313 u8 reserved_at_280[0x600];
4314
4315 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4316
4317 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4318};
4319
4320struct mlx5_ifc_query_mkey_in_bits {
4321 u8 opcode[0x10];
4322 u8 reserved_at_10[0x10];
4323
4324 u8 reserved_at_20[0x10];
4325 u8 op_mod[0x10];
4326
4327 u8 reserved_at_40[0x8];
4328 u8 mkey_index[0x18];
4329
4330 u8 pg_access[0x1];
4331 u8 reserved_at_61[0x1f];
4332};
4333
4334struct mlx5_ifc_query_mad_demux_out_bits {
4335 u8 status[0x8];
4336 u8 reserved_at_8[0x18];
4337
4338 u8 syndrome[0x20];
4339
4340 u8 reserved_at_40[0x40];
4341
4342 u8 mad_dumux_parameters_block[0x20];
4343};
4344
4345struct mlx5_ifc_query_mad_demux_in_bits {
4346 u8 opcode[0x10];
4347 u8 reserved_at_10[0x10];
4348
4349 u8 reserved_at_20[0x10];
4350 u8 op_mod[0x10];
4351
4352 u8 reserved_at_40[0x40];
4353};
4354
4355struct mlx5_ifc_query_l2_table_entry_out_bits {
4356 u8 status[0x8];
4357 u8 reserved_at_8[0x18];
4358
4359 u8 syndrome[0x20];
4360
4361 u8 reserved_at_40[0xa0];
4362
4363 u8 reserved_at_e0[0x13];
4364 u8 vlan_valid[0x1];
4365 u8 vlan[0xc];
4366
4367 struct mlx5_ifc_mac_address_layout_bits mac_address;
4368
4369 u8 reserved_at_140[0xc0];
4370};
4371
4372struct mlx5_ifc_query_l2_table_entry_in_bits {
4373 u8 opcode[0x10];
4374 u8 reserved_at_10[0x10];
4375
4376 u8 reserved_at_20[0x10];
4377 u8 op_mod[0x10];
4378
4379 u8 reserved_at_40[0x60];
4380
4381 u8 reserved_at_a0[0x8];
4382 u8 table_index[0x18];
4383
4384 u8 reserved_at_c0[0x140];
4385};
4386
4387struct mlx5_ifc_query_issi_out_bits {
4388 u8 status[0x8];
4389 u8 reserved_at_8[0x18];
4390
4391 u8 syndrome[0x20];
4392
4393 u8 reserved_at_40[0x10];
4394 u8 current_issi[0x10];
4395
4396 u8 reserved_at_60[0xa0];
4397
4398 u8 reserved_at_100[76][0x8];
4399 u8 supported_issi_dw0[0x20];
4400};
4401
4402struct mlx5_ifc_query_issi_in_bits {
4403 u8 opcode[0x10];
4404 u8 reserved_at_10[0x10];
4405
4406 u8 reserved_at_20[0x10];
4407 u8 op_mod[0x10];
4408
4409 u8 reserved_at_40[0x40];
4410};
4411
4412struct mlx5_ifc_set_driver_version_out_bits {
4413 u8 status[0x8];
4414 u8 reserved_0[0x18];
4415
4416 u8 syndrome[0x20];
4417 u8 reserved_1[0x40];
4418};
4419
4420struct mlx5_ifc_set_driver_version_in_bits {
4421 u8 opcode[0x10];
4422 u8 reserved_0[0x10];
4423
4424 u8 reserved_1[0x10];
4425 u8 op_mod[0x10];
4426
4427 u8 reserved_2[0x40];
4428 u8 driver_version[64][0x8];
4429};
4430
4431struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4432 u8 status[0x8];
4433 u8 reserved_at_8[0x18];
4434
4435 u8 syndrome[0x20];
4436
4437 u8 reserved_at_40[0x40];
4438
4439 struct mlx5_ifc_pkey_bits pkey[0];
4440};
4441
4442struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4443 u8 opcode[0x10];
4444 u8 reserved_at_10[0x10];
4445
4446 u8 reserved_at_20[0x10];
4447 u8 op_mod[0x10];
4448
4449 u8 other_vport[0x1];
4450 u8 reserved_at_41[0xb];
4451 u8 port_num[0x4];
4452 u8 vport_number[0x10];
4453
4454 u8 reserved_at_60[0x10];
4455 u8 pkey_index[0x10];
4456};
4457
4458enum {
4459 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4460 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4461 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4462};
4463
4464struct mlx5_ifc_query_hca_vport_gid_out_bits {
4465 u8 status[0x8];
4466 u8 reserved_at_8[0x18];
4467
4468 u8 syndrome[0x20];
4469
4470 u8 reserved_at_40[0x20];
4471
4472 u8 gids_num[0x10];
4473 u8 reserved_at_70[0x10];
4474
4475 struct mlx5_ifc_array128_auto_bits gid[0];
4476};
4477
4478struct mlx5_ifc_query_hca_vport_gid_in_bits {
4479 u8 opcode[0x10];
4480 u8 reserved_at_10[0x10];
4481
4482 u8 reserved_at_20[0x10];
4483 u8 op_mod[0x10];
4484
4485 u8 other_vport[0x1];
4486 u8 reserved_at_41[0xb];
4487 u8 port_num[0x4];
4488 u8 vport_number[0x10];
4489
4490 u8 reserved_at_60[0x10];
4491 u8 gid_index[0x10];
4492};
4493
4494struct mlx5_ifc_query_hca_vport_context_out_bits {
4495 u8 status[0x8];
4496 u8 reserved_at_8[0x18];
4497
4498 u8 syndrome[0x20];
4499
4500 u8 reserved_at_40[0x40];
4501
4502 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4503};
4504
4505struct mlx5_ifc_query_hca_vport_context_in_bits {
4506 u8 opcode[0x10];
4507 u8 reserved_at_10[0x10];
4508
4509 u8 reserved_at_20[0x10];
4510 u8 op_mod[0x10];
4511
4512 u8 other_vport[0x1];
4513 u8 reserved_at_41[0xb];
4514 u8 port_num[0x4];
4515 u8 vport_number[0x10];
4516
4517 u8 reserved_at_60[0x20];
4518};
4519
4520struct mlx5_ifc_query_hca_cap_out_bits {
4521 u8 status[0x8];
4522 u8 reserved_at_8[0x18];
4523
4524 u8 syndrome[0x20];
4525
4526 u8 reserved_at_40[0x40];
4527
4528 union mlx5_ifc_hca_cap_union_bits capability;
4529};
4530
4531struct mlx5_ifc_query_hca_cap_in_bits {
4532 u8 opcode[0x10];
4533 u8 reserved_at_10[0x10];
4534
4535 u8 reserved_at_20[0x10];
4536 u8 op_mod[0x10];
4537
4538 u8 reserved_at_40[0x40];
4539};
4540
4541struct mlx5_ifc_query_flow_table_out_bits {
4542 u8 status[0x8];
4543 u8 reserved_at_8[0x18];
4544
4545 u8 syndrome[0x20];
4546
4547 u8 reserved_at_40[0x80];
4548
4549 u8 reserved_at_c0[0x8];
4550 u8 level[0x8];
4551 u8 reserved_at_d0[0x8];
4552 u8 log_size[0x8];
4553
4554 u8 reserved_at_e0[0x120];
4555};
4556
4557struct mlx5_ifc_query_flow_table_in_bits {
4558 u8 opcode[0x10];
4559 u8 reserved_at_10[0x10];
4560
4561 u8 reserved_at_20[0x10];
4562 u8 op_mod[0x10];
4563
4564 u8 reserved_at_40[0x40];
4565
4566 u8 table_type[0x8];
4567 u8 reserved_at_88[0x18];
4568
4569 u8 reserved_at_a0[0x8];
4570 u8 table_id[0x18];
4571
4572 u8 reserved_at_c0[0x140];
4573};
4574
4575struct mlx5_ifc_query_fte_out_bits {
4576 u8 status[0x8];
4577 u8 reserved_at_8[0x18];
4578
4579 u8 syndrome[0x20];
4580
4581 u8 reserved_at_40[0x1c0];
4582
4583 struct mlx5_ifc_flow_context_bits flow_context;
4584};
4585
4586struct mlx5_ifc_query_fte_in_bits {
4587 u8 opcode[0x10];
4588 u8 reserved_at_10[0x10];
4589
4590 u8 reserved_at_20[0x10];
4591 u8 op_mod[0x10];
4592
4593 u8 reserved_at_40[0x40];
4594
4595 u8 table_type[0x8];
4596 u8 reserved_at_88[0x18];
4597
4598 u8 reserved_at_a0[0x8];
4599 u8 table_id[0x18];
4600
4601 u8 reserved_at_c0[0x40];
4602
4603 u8 flow_index[0x20];
4604
4605 u8 reserved_at_120[0xe0];
4606};
4607
4608enum {
4609 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4610 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4611 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4612 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4613};
4614
4615struct mlx5_ifc_query_flow_group_out_bits {
4616 u8 status[0x8];
4617 u8 reserved_at_8[0x18];
4618
4619 u8 syndrome[0x20];
4620
4621 u8 reserved_at_40[0xa0];
4622
4623 u8 start_flow_index[0x20];
4624
4625 u8 reserved_at_100[0x20];
4626
4627 u8 end_flow_index[0x20];
4628
4629 u8 reserved_at_140[0xa0];
4630
4631 u8 reserved_at_1e0[0x18];
4632 u8 match_criteria_enable[0x8];
4633
4634 struct mlx5_ifc_fte_match_param_bits match_criteria;
4635
4636 u8 reserved_at_1200[0xe00];
4637};
4638
4639struct mlx5_ifc_query_flow_group_in_bits {
4640 u8 opcode[0x10];
4641 u8 reserved_at_10[0x10];
4642
4643 u8 reserved_at_20[0x10];
4644 u8 op_mod[0x10];
4645
4646 u8 reserved_at_40[0x40];
4647
4648 u8 table_type[0x8];
4649 u8 reserved_at_88[0x18];
4650
4651 u8 reserved_at_a0[0x8];
4652 u8 table_id[0x18];
4653
4654 u8 group_id[0x20];
4655
4656 u8 reserved_at_e0[0x120];
4657};
4658
4659struct mlx5_ifc_query_flow_counter_out_bits {
4660 u8 status[0x8];
4661 u8 reserved_at_8[0x18];
4662
4663 u8 syndrome[0x20];
4664
4665 u8 reserved_at_40[0x40];
4666
4667 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4668};
4669
4670struct mlx5_ifc_query_flow_counter_in_bits {
4671 u8 opcode[0x10];
4672 u8 reserved_at_10[0x10];
4673
4674 u8 reserved_at_20[0x10];
4675 u8 op_mod[0x10];
4676
4677 u8 reserved_at_40[0x80];
4678
4679 u8 clear[0x1];
4680 u8 reserved_at_c1[0xf];
4681 u8 num_of_counters[0x10];
4682
4683 u8 flow_counter_id[0x20];
4684};
4685
4686struct mlx5_ifc_query_esw_vport_context_out_bits {
4687 u8 status[0x8];
4688 u8 reserved_at_8[0x18];
4689
4690 u8 syndrome[0x20];
4691
4692 u8 reserved_at_40[0x40];
4693
4694 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4695};
4696
4697struct mlx5_ifc_query_esw_vport_context_in_bits {
4698 u8 opcode[0x10];
4699 u8 reserved_at_10[0x10];
4700
4701 u8 reserved_at_20[0x10];
4702 u8 op_mod[0x10];
4703
4704 u8 other_vport[0x1];
4705 u8 reserved_at_41[0xf];
4706 u8 vport_number[0x10];
4707
4708 u8 reserved_at_60[0x20];
4709};
4710
4711struct mlx5_ifc_modify_esw_vport_context_out_bits {
4712 u8 status[0x8];
4713 u8 reserved_at_8[0x18];
4714
4715 u8 syndrome[0x20];
4716
4717 u8 reserved_at_40[0x40];
4718};
4719
4720struct mlx5_ifc_esw_vport_context_fields_select_bits {
4721 u8 reserved_at_0[0x1c];
4722 u8 vport_cvlan_insert[0x1];
4723 u8 vport_svlan_insert[0x1];
4724 u8 vport_cvlan_strip[0x1];
4725 u8 vport_svlan_strip[0x1];
4726};
4727
4728struct mlx5_ifc_modify_esw_vport_context_in_bits {
4729 u8 opcode[0x10];
4730 u8 reserved_at_10[0x10];
4731
4732 u8 reserved_at_20[0x10];
4733 u8 op_mod[0x10];
4734
4735 u8 other_vport[0x1];
4736 u8 reserved_at_41[0xf];
4737 u8 vport_number[0x10];
4738
4739 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4740
4741 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4742};
4743
4744struct mlx5_ifc_query_eq_out_bits {
4745 u8 status[0x8];
4746 u8 reserved_at_8[0x18];
4747
4748 u8 syndrome[0x20];
4749
4750 u8 reserved_at_40[0x40];
4751
4752 struct mlx5_ifc_eqc_bits eq_context_entry;
4753
4754 u8 reserved_at_280[0x40];
4755
4756 u8 event_bitmask[0x40];
4757
4758 u8 reserved_at_300[0x580];
4759
4760 u8 pas[0][0x40];
4761};
4762
4763struct mlx5_ifc_query_eq_in_bits {
4764 u8 opcode[0x10];
4765 u8 reserved_at_10[0x10];
4766
4767 u8 reserved_at_20[0x10];
4768 u8 op_mod[0x10];
4769
4770 u8 reserved_at_40[0x18];
4771 u8 eq_number[0x8];
4772
4773 u8 reserved_at_60[0x20];
4774};
4775
4776struct mlx5_ifc_encap_header_in_bits {
4777 u8 reserved_at_0[0x5];
4778 u8 header_type[0x3];
4779 u8 reserved_at_8[0xe];
4780 u8 encap_header_size[0xa];
4781
4782 u8 reserved_at_20[0x10];
4783 u8 encap_header[2][0x8];
4784
4785 u8 more_encap_header[0][0x8];
4786};
4787
4788struct mlx5_ifc_query_encap_header_out_bits {
4789 u8 status[0x8];
4790 u8 reserved_at_8[0x18];
4791
4792 u8 syndrome[0x20];
4793
4794 u8 reserved_at_40[0xa0];
4795
4796 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4797};
4798
4799struct mlx5_ifc_query_encap_header_in_bits {
4800 u8 opcode[0x10];
4801 u8 reserved_at_10[0x10];
4802
4803 u8 reserved_at_20[0x10];
4804 u8 op_mod[0x10];
4805
4806 u8 encap_id[0x20];
4807
4808 u8 reserved_at_60[0xa0];
4809};
4810
4811struct mlx5_ifc_alloc_encap_header_out_bits {
4812 u8 status[0x8];
4813 u8 reserved_at_8[0x18];
4814
4815 u8 syndrome[0x20];
4816
4817 u8 encap_id[0x20];
4818
4819 u8 reserved_at_60[0x20];
4820};
4821
4822struct mlx5_ifc_alloc_encap_header_in_bits {
4823 u8 opcode[0x10];
4824 u8 reserved_at_10[0x10];
4825
4826 u8 reserved_at_20[0x10];
4827 u8 op_mod[0x10];
4828
4829 u8 reserved_at_40[0xa0];
4830
4831 struct mlx5_ifc_encap_header_in_bits encap_header;
4832};
4833
4834struct mlx5_ifc_dealloc_encap_header_out_bits {
4835 u8 status[0x8];
4836 u8 reserved_at_8[0x18];
4837
4838 u8 syndrome[0x20];
4839
4840 u8 reserved_at_40[0x40];
4841};
4842
4843struct mlx5_ifc_dealloc_encap_header_in_bits {
4844 u8 opcode[0x10];
4845 u8 reserved_at_10[0x10];
4846
4847 u8 reserved_20[0x10];
4848 u8 op_mod[0x10];
4849
4850 u8 encap_id[0x20];
4851
4852 u8 reserved_60[0x20];
4853};
4854
4855struct mlx5_ifc_set_action_in_bits {
4856 u8 action_type[0x4];
4857 u8 field[0xc];
4858 u8 reserved_at_10[0x3];
4859 u8 offset[0x5];
4860 u8 reserved_at_18[0x3];
4861 u8 length[0x5];
4862
4863 u8 data[0x20];
4864};
4865
4866struct mlx5_ifc_add_action_in_bits {
4867 u8 action_type[0x4];
4868 u8 field[0xc];
4869 u8 reserved_at_10[0x10];
4870
4871 u8 data[0x20];
4872};
4873
4874union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4875 struct mlx5_ifc_set_action_in_bits set_action_in;
4876 struct mlx5_ifc_add_action_in_bits add_action_in;
4877 u8 reserved_at_0[0x40];
4878};
4879
4880enum {
4881 MLX5_ACTION_TYPE_SET = 0x1,
4882 MLX5_ACTION_TYPE_ADD = 0x2,
4883};
4884
4885enum {
4886 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4887 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4888 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4889 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4890 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4891 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4892 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4893 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4894 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4895 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4896 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4897 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4898 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4899 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4900 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4901 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4902 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4903 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4904 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4905 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4906 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4907 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4908 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4909};
4910
4911struct mlx5_ifc_alloc_modify_header_context_out_bits {
4912 u8 status[0x8];
4913 u8 reserved_at_8[0x18];
4914
4915 u8 syndrome[0x20];
4916
4917 u8 modify_header_id[0x20];
4918
4919 u8 reserved_at_60[0x20];
4920};
4921
4922struct mlx5_ifc_alloc_modify_header_context_in_bits {
4923 u8 opcode[0x10];
4924 u8 reserved_at_10[0x10];
4925
4926 u8 reserved_at_20[0x10];
4927 u8 op_mod[0x10];
4928
4929 u8 reserved_at_40[0x20];
4930
4931 u8 table_type[0x8];
4932 u8 reserved_at_68[0x10];
4933 u8 num_of_actions[0x8];
4934
4935 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4936};
4937
4938struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4939 u8 status[0x8];
4940 u8 reserved_at_8[0x18];
4941
4942 u8 syndrome[0x20];
4943
4944 u8 reserved_at_40[0x40];
4945};
4946
4947struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4948 u8 opcode[0x10];
4949 u8 reserved_at_10[0x10];
4950
4951 u8 reserved_at_20[0x10];
4952 u8 op_mod[0x10];
4953
4954 u8 modify_header_id[0x20];
4955
4956 u8 reserved_at_60[0x20];
4957};
4958
4959struct mlx5_ifc_query_dct_out_bits {
4960 u8 status[0x8];
4961 u8 reserved_at_8[0x18];
4962
4963 u8 syndrome[0x20];
4964
4965 u8 reserved_at_40[0x40];
4966
4967 struct mlx5_ifc_dctc_bits dct_context_entry;
4968
4969 u8 reserved_at_280[0x180];
4970};
4971
4972struct mlx5_ifc_query_dct_in_bits {
4973 u8 opcode[0x10];
4974 u8 reserved_at_10[0x10];
4975
4976 u8 reserved_at_20[0x10];
4977 u8 op_mod[0x10];
4978
4979 u8 reserved_at_40[0x8];
4980 u8 dctn[0x18];
4981
4982 u8 reserved_at_60[0x20];
4983};
4984
4985struct mlx5_ifc_query_cq_out_bits {
4986 u8 status[0x8];
4987 u8 reserved_at_8[0x18];
4988
4989 u8 syndrome[0x20];
4990
4991 u8 reserved_at_40[0x40];
4992
4993 struct mlx5_ifc_cqc_bits cq_context;
4994
4995 u8 reserved_at_280[0x600];
4996
4997 u8 pas[0][0x40];
4998};
4999
5000struct mlx5_ifc_query_cq_in_bits {
5001 u8 opcode[0x10];
5002 u8 reserved_at_10[0x10];
5003
5004 u8 reserved_at_20[0x10];
5005 u8 op_mod[0x10];
5006
5007 u8 reserved_at_40[0x8];
5008 u8 cqn[0x18];
5009
5010 u8 reserved_at_60[0x20];
5011};
5012
5013struct mlx5_ifc_query_cong_status_out_bits {
5014 u8 status[0x8];
5015 u8 reserved_at_8[0x18];
5016
5017 u8 syndrome[0x20];
5018
5019 u8 reserved_at_40[0x20];
5020
5021 u8 enable[0x1];
5022 u8 tag_enable[0x1];
5023 u8 reserved_at_62[0x1e];
5024};
5025
5026struct mlx5_ifc_query_cong_status_in_bits {
5027 u8 opcode[0x10];
5028 u8 reserved_at_10[0x10];
5029
5030 u8 reserved_at_20[0x10];
5031 u8 op_mod[0x10];
5032
5033 u8 reserved_at_40[0x18];
5034 u8 priority[0x4];
5035 u8 cong_protocol[0x4];
5036
5037 u8 reserved_at_60[0x20];
5038};
5039
5040struct mlx5_ifc_query_cong_statistics_out_bits {
5041 u8 status[0x8];
5042 u8 reserved_at_8[0x18];
5043
5044 u8 syndrome[0x20];
5045
5046 u8 reserved_at_40[0x40];
5047
5048 u8 rp_cur_flows[0x20];
5049
5050 u8 sum_flows[0x20];
5051
5052 u8 rp_cnp_ignored_high[0x20];
5053
5054 u8 rp_cnp_ignored_low[0x20];
5055
5056 u8 rp_cnp_handled_high[0x20];
5057
5058 u8 rp_cnp_handled_low[0x20];
5059
5060 u8 reserved_at_140[0x100];
5061
5062 u8 time_stamp_high[0x20];
5063
5064 u8 time_stamp_low[0x20];
5065
5066 u8 accumulators_period[0x20];
5067
5068 u8 np_ecn_marked_roce_packets_high[0x20];
5069
5070 u8 np_ecn_marked_roce_packets_low[0x20];
5071
5072 u8 np_cnp_sent_high[0x20];
5073
5074 u8 np_cnp_sent_low[0x20];
5075
5076 u8 reserved_at_320[0x560];
5077};
5078
5079struct mlx5_ifc_query_cong_statistics_in_bits {
5080 u8 opcode[0x10];
5081 u8 reserved_at_10[0x10];
5082
5083 u8 reserved_at_20[0x10];
5084 u8 op_mod[0x10];
5085
5086 u8 clear[0x1];
5087 u8 reserved_at_41[0x1f];
5088
5089 u8 reserved_at_60[0x20];
5090};
5091
5092struct mlx5_ifc_query_cong_params_out_bits {
5093 u8 status[0x8];
5094 u8 reserved_at_8[0x18];
5095
5096 u8 syndrome[0x20];
5097
5098 u8 reserved_at_40[0x40];
5099
5100 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5101};
5102
5103struct mlx5_ifc_query_cong_params_in_bits {
5104 u8 opcode[0x10];
5105 u8 reserved_at_10[0x10];
5106
5107 u8 reserved_at_20[0x10];
5108 u8 op_mod[0x10];
5109
5110 u8 reserved_at_40[0x1c];
5111 u8 cong_protocol[0x4];
5112
5113 u8 reserved_at_60[0x20];
5114};
5115
5116struct mlx5_ifc_query_adapter_out_bits {
5117 u8 status[0x8];
5118 u8 reserved_at_8[0x18];
5119
5120 u8 syndrome[0x20];
5121
5122 u8 reserved_at_40[0x40];
5123
5124 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5125};
5126
5127struct mlx5_ifc_query_adapter_in_bits {
5128 u8 opcode[0x10];
5129 u8 reserved_at_10[0x10];
5130
5131 u8 reserved_at_20[0x10];
5132 u8 op_mod[0x10];
5133
5134 u8 reserved_at_40[0x40];
5135};
5136
5137struct mlx5_ifc_qp_2rst_out_bits {
5138 u8 status[0x8];
5139 u8 reserved_at_8[0x18];
5140
5141 u8 syndrome[0x20];
5142
5143 u8 reserved_at_40[0x40];
5144};
5145
5146struct mlx5_ifc_qp_2rst_in_bits {
5147 u8 opcode[0x10];
5148 u8 reserved_at_10[0x10];
5149
5150 u8 reserved_at_20[0x10];
5151 u8 op_mod[0x10];
5152
5153 u8 reserved_at_40[0x8];
5154 u8 qpn[0x18];
5155
5156 u8 reserved_at_60[0x20];
5157};
5158
5159struct mlx5_ifc_qp_2err_out_bits {
5160 u8 status[0x8];
5161 u8 reserved_at_8[0x18];
5162
5163 u8 syndrome[0x20];
5164
5165 u8 reserved_at_40[0x40];
5166};
5167
5168struct mlx5_ifc_qp_2err_in_bits {
5169 u8 opcode[0x10];
5170 u8 reserved_at_10[0x10];
5171
5172 u8 reserved_at_20[0x10];
5173 u8 op_mod[0x10];
5174
5175 u8 reserved_at_40[0x8];
5176 u8 qpn[0x18];
5177
5178 u8 reserved_at_60[0x20];
5179};
5180
5181struct mlx5_ifc_page_fault_resume_out_bits {
5182 u8 status[0x8];
5183 u8 reserved_at_8[0x18];
5184
5185 u8 syndrome[0x20];
5186
5187 u8 reserved_at_40[0x40];
5188};
5189
5190struct mlx5_ifc_page_fault_resume_in_bits {
5191 u8 opcode[0x10];
5192 u8 reserved_at_10[0x10];
5193
5194 u8 reserved_at_20[0x10];
5195 u8 op_mod[0x10];
5196
5197 u8 error[0x1];
5198 u8 reserved_at_41[0x4];
5199 u8 page_fault_type[0x3];
5200 u8 wq_number[0x18];
5201
5202 u8 reserved_at_60[0x8];
5203 u8 token[0x18];
5204};
5205
5206struct mlx5_ifc_nop_out_bits {
5207 u8 status[0x8];
5208 u8 reserved_at_8[0x18];
5209
5210 u8 syndrome[0x20];
5211
5212 u8 reserved_at_40[0x40];
5213};
5214
5215struct mlx5_ifc_nop_in_bits {
5216 u8 opcode[0x10];
5217 u8 reserved_at_10[0x10];
5218
5219 u8 reserved_at_20[0x10];
5220 u8 op_mod[0x10];
5221
5222 u8 reserved_at_40[0x40];
5223};
5224
5225struct mlx5_ifc_modify_vport_state_out_bits {
5226 u8 status[0x8];
5227 u8 reserved_at_8[0x18];
5228
5229 u8 syndrome[0x20];
5230
5231 u8 reserved_at_40[0x40];
5232};
5233
5234struct mlx5_ifc_modify_vport_state_in_bits {
5235 u8 opcode[0x10];
5236 u8 reserved_at_10[0x10];
5237
5238 u8 reserved_at_20[0x10];
5239 u8 op_mod[0x10];
5240
5241 u8 other_vport[0x1];
5242 u8 reserved_at_41[0xf];
5243 u8 vport_number[0x10];
5244
5245 u8 reserved_at_60[0x18];
5246 u8 admin_state[0x4];
5247 u8 reserved_at_7c[0x4];
5248};
5249
5250struct mlx5_ifc_modify_tis_out_bits {
5251 u8 status[0x8];
5252 u8 reserved_at_8[0x18];
5253
5254 u8 syndrome[0x20];
5255
5256 u8 reserved_at_40[0x40];
5257};
5258
5259struct mlx5_ifc_modify_tis_bitmask_bits {
5260 u8 reserved_at_0[0x20];
5261
5262 u8 reserved_at_20[0x1d];
5263 u8 lag_tx_port_affinity[0x1];
5264 u8 strict_lag_tx_port_affinity[0x1];
5265 u8 prio[0x1];
5266};
5267
5268struct mlx5_ifc_modify_tis_in_bits {
5269 u8 opcode[0x10];
5270 u8 reserved_at_10[0x10];
5271
5272 u8 reserved_at_20[0x10];
5273 u8 op_mod[0x10];
5274
5275 u8 reserved_at_40[0x8];
5276 u8 tisn[0x18];
5277
5278 u8 reserved_at_60[0x20];
5279
5280 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5281
5282 u8 reserved_at_c0[0x40];
5283
5284 struct mlx5_ifc_tisc_bits ctx;
5285};
5286
5287struct mlx5_ifc_modify_tir_bitmask_bits {
5288 u8 reserved_at_0[0x20];
5289
5290 u8 reserved_at_20[0x1b];
5291 u8 self_lb_en[0x1];
5292 u8 reserved_at_3c[0x1];
5293 u8 hash[0x1];
5294 u8 reserved_at_3e[0x1];
5295 u8 lro[0x1];
5296};
5297
5298struct mlx5_ifc_modify_tir_out_bits {
5299 u8 status[0x8];
5300 u8 reserved_at_8[0x18];
5301
5302 u8 syndrome[0x20];
5303
5304 u8 reserved_at_40[0x40];
5305};
5306
5307struct mlx5_ifc_modify_tir_in_bits {
5308 u8 opcode[0x10];
5309 u8 reserved_at_10[0x10];
5310
5311 u8 reserved_at_20[0x10];
5312 u8 op_mod[0x10];
5313
5314 u8 reserved_at_40[0x8];
5315 u8 tirn[0x18];
5316
5317 u8 reserved_at_60[0x20];
5318
5319 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5320
5321 u8 reserved_at_c0[0x40];
5322
5323 struct mlx5_ifc_tirc_bits ctx;
5324};
5325
5326struct mlx5_ifc_modify_sq_out_bits {
5327 u8 status[0x8];
5328 u8 reserved_at_8[0x18];
5329
5330 u8 syndrome[0x20];
5331
5332 u8 reserved_at_40[0x40];
5333};
5334
5335struct mlx5_ifc_modify_sq_in_bits {
5336 u8 opcode[0x10];
5337 u8 reserved_at_10[0x10];
5338
5339 u8 reserved_at_20[0x10];
5340 u8 op_mod[0x10];
5341
5342 u8 sq_state[0x4];
5343 u8 reserved_at_44[0x4];
5344 u8 sqn[0x18];
5345
5346 u8 reserved_at_60[0x20];
5347
5348 u8 modify_bitmask[0x40];
5349
5350 u8 reserved_at_c0[0x40];
5351
5352 struct mlx5_ifc_sqc_bits ctx;
5353};
5354
5355struct mlx5_ifc_modify_scheduling_element_out_bits {
5356 u8 status[0x8];
5357 u8 reserved_at_8[0x18];
5358
5359 u8 syndrome[0x20];
5360
5361 u8 reserved_at_40[0x1c0];
5362};
5363
5364enum {
5365 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5366 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5367};
5368
5369struct mlx5_ifc_modify_scheduling_element_in_bits {
5370 u8 opcode[0x10];
5371 u8 reserved_at_10[0x10];
5372
5373 u8 reserved_at_20[0x10];
5374 u8 op_mod[0x10];
5375
5376 u8 scheduling_hierarchy[0x8];
5377 u8 reserved_at_48[0x18];
5378
5379 u8 scheduling_element_id[0x20];
5380
5381 u8 reserved_at_80[0x20];
5382
5383 u8 modify_bitmask[0x20];
5384
5385 u8 reserved_at_c0[0x40];
5386
5387 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5388
5389 u8 reserved_at_300[0x100];
5390};
5391
5392struct mlx5_ifc_modify_rqt_out_bits {
5393 u8 status[0x8];
5394 u8 reserved_at_8[0x18];
5395
5396 u8 syndrome[0x20];
5397
5398 u8 reserved_at_40[0x40];
5399};
5400
5401struct mlx5_ifc_rqt_bitmask_bits {
5402 u8 reserved_at_0[0x20];
5403
5404 u8 reserved_at_20[0x1f];
5405 u8 rqn_list[0x1];
5406};
5407
5408struct mlx5_ifc_modify_rqt_in_bits {
5409 u8 opcode[0x10];
5410 u8 reserved_at_10[0x10];
5411
5412 u8 reserved_at_20[0x10];
5413 u8 op_mod[0x10];
5414
5415 u8 reserved_at_40[0x8];
5416 u8 rqtn[0x18];
5417
5418 u8 reserved_at_60[0x20];
5419
5420 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5421
5422 u8 reserved_at_c0[0x40];
5423
5424 struct mlx5_ifc_rqtc_bits ctx;
5425};
5426
5427struct mlx5_ifc_modify_rq_out_bits {
5428 u8 status[0x8];
5429 u8 reserved_at_8[0x18];
5430
5431 u8 syndrome[0x20];
5432
5433 u8 reserved_at_40[0x40];
5434};
5435
5436enum {
5437 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5438 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5439 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5440};
5441
5442struct mlx5_ifc_modify_rq_in_bits {
5443 u8 opcode[0x10];
5444 u8 reserved_at_10[0x10];
5445
5446 u8 reserved_at_20[0x10];
5447 u8 op_mod[0x10];
5448
5449 u8 rq_state[0x4];
5450 u8 reserved_at_44[0x4];
5451 u8 rqn[0x18];
5452
5453 u8 reserved_at_60[0x20];
5454
5455 u8 modify_bitmask[0x40];
5456
5457 u8 reserved_at_c0[0x40];
5458
5459 struct mlx5_ifc_rqc_bits ctx;
5460};
5461
5462struct mlx5_ifc_modify_rmp_out_bits {
5463 u8 status[0x8];
5464 u8 reserved_at_8[0x18];
5465
5466 u8 syndrome[0x20];
5467
5468 u8 reserved_at_40[0x40];
5469};
5470
5471struct mlx5_ifc_rmp_bitmask_bits {
5472 u8 reserved_at_0[0x20];
5473
5474 u8 reserved_at_20[0x1f];
5475 u8 lwm[0x1];
5476};
5477
5478struct mlx5_ifc_modify_rmp_in_bits {
5479 u8 opcode[0x10];
5480 u8 reserved_at_10[0x10];
5481
5482 u8 reserved_at_20[0x10];
5483 u8 op_mod[0x10];
5484
5485 u8 rmp_state[0x4];
5486 u8 reserved_at_44[0x4];
5487 u8 rmpn[0x18];
5488
5489 u8 reserved_at_60[0x20];
5490
5491 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5492
5493 u8 reserved_at_c0[0x40];
5494
5495 struct mlx5_ifc_rmpc_bits ctx;
5496};
5497
5498struct mlx5_ifc_modify_nic_vport_context_out_bits {
5499 u8 status[0x8];
5500 u8 reserved_at_8[0x18];
5501
5502 u8 syndrome[0x20];
5503
5504 u8 reserved_at_40[0x40];
5505};
5506
5507struct mlx5_ifc_modify_nic_vport_field_select_bits {
5508 u8 reserved_at_0[0x12];
5509 u8 affiliation[0x1];
5510 u8 reserved_at_e[0x1];
5511 u8 disable_uc_local_lb[0x1];
5512 u8 disable_mc_local_lb[0x1];
5513 u8 node_guid[0x1];
5514 u8 port_guid[0x1];
5515 u8 min_inline[0x1];
5516 u8 mtu[0x1];
5517 u8 change_event[0x1];
5518 u8 promisc[0x1];
5519 u8 permanent_address[0x1];
5520 u8 addresses_list[0x1];
5521 u8 roce_en[0x1];
5522 u8 reserved_at_1f[0x1];
5523};
5524
5525struct mlx5_ifc_modify_nic_vport_context_in_bits {
5526 u8 opcode[0x10];
5527 u8 reserved_at_10[0x10];
5528
5529 u8 reserved_at_20[0x10];
5530 u8 op_mod[0x10];
5531
5532 u8 other_vport[0x1];
5533 u8 reserved_at_41[0xf];
5534 u8 vport_number[0x10];
5535
5536 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5537
5538 u8 reserved_at_80[0x780];
5539
5540 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5541};
5542
5543struct mlx5_ifc_modify_hca_vport_context_out_bits {
5544 u8 status[0x8];
5545 u8 reserved_at_8[0x18];
5546
5547 u8 syndrome[0x20];
5548
5549 u8 reserved_at_40[0x40];
5550};
5551
5552struct mlx5_ifc_modify_hca_vport_context_in_bits {
5553 u8 opcode[0x10];
5554 u8 reserved_at_10[0x10];
5555
5556 u8 reserved_at_20[0x10];
5557 u8 op_mod[0x10];
5558
5559 u8 other_vport[0x1];
5560 u8 reserved_at_41[0xb];
5561 u8 port_num[0x4];
5562 u8 vport_number[0x10];
5563
5564 u8 reserved_at_60[0x20];
5565
5566 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5567};
5568
5569struct mlx5_ifc_modify_cq_out_bits {
5570 u8 status[0x8];
5571 u8 reserved_at_8[0x18];
5572
5573 u8 syndrome[0x20];
5574
5575 u8 reserved_at_40[0x40];
5576};
5577
5578enum {
5579 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5580 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5581};
5582
5583struct mlx5_ifc_modify_cq_in_bits {
5584 u8 opcode[0x10];
5585 u8 reserved_at_10[0x10];
5586
5587 u8 reserved_at_20[0x10];
5588 u8 op_mod[0x10];
5589
5590 u8 reserved_at_40[0x8];
5591 u8 cqn[0x18];
5592
5593 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5594
5595 struct mlx5_ifc_cqc_bits cq_context;
5596
5597 u8 reserved_at_280[0x600];
5598
5599 u8 pas[0][0x40];
5600};
5601
5602struct mlx5_ifc_modify_cong_status_out_bits {
5603 u8 status[0x8];
5604 u8 reserved_at_8[0x18];
5605
5606 u8 syndrome[0x20];
5607
5608 u8 reserved_at_40[0x40];
5609};
5610
5611struct mlx5_ifc_modify_cong_status_in_bits {
5612 u8 opcode[0x10];
5613 u8 reserved_at_10[0x10];
5614
5615 u8 reserved_at_20[0x10];
5616 u8 op_mod[0x10];
5617
5618 u8 reserved_at_40[0x18];
5619 u8 priority[0x4];
5620 u8 cong_protocol[0x4];
5621
5622 u8 enable[0x1];
5623 u8 tag_enable[0x1];
5624 u8 reserved_at_62[0x1e];
5625};
5626
5627struct mlx5_ifc_modify_cong_params_out_bits {
5628 u8 status[0x8];
5629 u8 reserved_at_8[0x18];
5630
5631 u8 syndrome[0x20];
5632
5633 u8 reserved_at_40[0x40];
5634};
5635
5636struct mlx5_ifc_modify_cong_params_in_bits {
5637 u8 opcode[0x10];
5638 u8 reserved_at_10[0x10];
5639
5640 u8 reserved_at_20[0x10];
5641 u8 op_mod[0x10];
5642
5643 u8 reserved_at_40[0x1c];
5644 u8 cong_protocol[0x4];
5645
5646 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5647
5648 u8 reserved_at_80[0x80];
5649
5650 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5651};
5652
5653struct mlx5_ifc_manage_pages_out_bits {
5654 u8 status[0x8];
5655 u8 reserved_at_8[0x18];
5656
5657 u8 syndrome[0x20];
5658
5659 u8 output_num_entries[0x20];
5660
5661 u8 reserved_at_60[0x20];
5662
5663 u8 pas[0][0x40];
5664};
5665
5666enum {
5667 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5668 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5669 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5670};
5671
5672struct mlx5_ifc_manage_pages_in_bits {
5673 u8 opcode[0x10];
5674 u8 reserved_at_10[0x10];
5675
5676 u8 reserved_at_20[0x10];
5677 u8 op_mod[0x10];
5678
5679 u8 reserved_at_40[0x10];
5680 u8 function_id[0x10];
5681
5682 u8 input_num_entries[0x20];
5683
5684 u8 pas[0][0x40];
5685};
5686
5687struct mlx5_ifc_mad_ifc_out_bits {
5688 u8 status[0x8];
5689 u8 reserved_at_8[0x18];
5690
5691 u8 syndrome[0x20];
5692
5693 u8 reserved_at_40[0x40];
5694
5695 u8 response_mad_packet[256][0x8];
5696};
5697
5698struct mlx5_ifc_mad_ifc_in_bits {
5699 u8 opcode[0x10];
5700 u8 reserved_at_10[0x10];
5701
5702 u8 reserved_at_20[0x10];
5703 u8 op_mod[0x10];
5704
5705 u8 remote_lid[0x10];
5706 u8 reserved_at_50[0x8];
5707 u8 port[0x8];
5708
5709 u8 reserved_at_60[0x20];
5710
5711 u8 mad[256][0x8];
5712};
5713
5714struct mlx5_ifc_init_hca_out_bits {
5715 u8 status[0x8];
5716 u8 reserved_at_8[0x18];
5717
5718 u8 syndrome[0x20];
5719
5720 u8 reserved_at_40[0x40];
5721};
5722
5723struct mlx5_ifc_init_hca_in_bits {
5724 u8 opcode[0x10];
5725 u8 reserved_at_10[0x10];
5726
5727 u8 reserved_at_20[0x10];
5728 u8 op_mod[0x10];
5729
5730 u8 reserved_at_40[0x40];
5731 u8 sw_owner_id[4][0x20];
5732};
5733
5734struct mlx5_ifc_init2rtr_qp_out_bits {
5735 u8 status[0x8];
5736 u8 reserved_at_8[0x18];
5737
5738 u8 syndrome[0x20];
5739
5740 u8 reserved_at_40[0x40];
5741};
5742
5743struct mlx5_ifc_init2rtr_qp_in_bits {
5744 u8 opcode[0x10];
5745 u8 reserved_at_10[0x10];
5746
5747 u8 reserved_at_20[0x10];
5748 u8 op_mod[0x10];
5749
5750 u8 reserved_at_40[0x8];
5751 u8 qpn[0x18];
5752
5753 u8 reserved_at_60[0x20];
5754
5755 u8 opt_param_mask[0x20];
5756
5757 u8 reserved_at_a0[0x20];
5758
5759 struct mlx5_ifc_qpc_bits qpc;
5760
5761 u8 reserved_at_800[0x80];
5762};
5763
5764struct mlx5_ifc_init2init_qp_out_bits {
5765 u8 status[0x8];
5766 u8 reserved_at_8[0x18];
5767
5768 u8 syndrome[0x20];
5769
5770 u8 reserved_at_40[0x40];
5771};
5772
5773struct mlx5_ifc_init2init_qp_in_bits {
5774 u8 opcode[0x10];
5775 u8 reserved_at_10[0x10];
5776
5777 u8 reserved_at_20[0x10];
5778 u8 op_mod[0x10];
5779
5780 u8 reserved_at_40[0x8];
5781 u8 qpn[0x18];
5782
5783 u8 reserved_at_60[0x20];
5784
5785 u8 opt_param_mask[0x20];
5786
5787 u8 reserved_at_a0[0x20];
5788
5789 struct mlx5_ifc_qpc_bits qpc;
5790
5791 u8 reserved_at_800[0x80];
5792};
5793
5794struct mlx5_ifc_get_dropped_packet_log_out_bits {
5795 u8 status[0x8];
5796 u8 reserved_at_8[0x18];
5797
5798 u8 syndrome[0x20];
5799
5800 u8 reserved_at_40[0x40];
5801
5802 u8 packet_headers_log[128][0x8];
5803
5804 u8 packet_syndrome[64][0x8];
5805};
5806
5807struct mlx5_ifc_get_dropped_packet_log_in_bits {
5808 u8 opcode[0x10];
5809 u8 reserved_at_10[0x10];
5810
5811 u8 reserved_at_20[0x10];
5812 u8 op_mod[0x10];
5813
5814 u8 reserved_at_40[0x40];
5815};
5816
5817struct mlx5_ifc_gen_eqe_in_bits {
5818 u8 opcode[0x10];
5819 u8 reserved_at_10[0x10];
5820
5821 u8 reserved_at_20[0x10];
5822 u8 op_mod[0x10];
5823
5824 u8 reserved_at_40[0x18];
5825 u8 eq_number[0x8];
5826
5827 u8 reserved_at_60[0x20];
5828
5829 u8 eqe[64][0x8];
5830};
5831
5832struct mlx5_ifc_gen_eq_out_bits {
5833 u8 status[0x8];
5834 u8 reserved_at_8[0x18];
5835
5836 u8 syndrome[0x20];
5837
5838 u8 reserved_at_40[0x40];
5839};
5840
5841struct mlx5_ifc_enable_hca_out_bits {
5842 u8 status[0x8];
5843 u8 reserved_at_8[0x18];
5844
5845 u8 syndrome[0x20];
5846
5847 u8 reserved_at_40[0x20];
5848};
5849
5850struct mlx5_ifc_enable_hca_in_bits {
5851 u8 opcode[0x10];
5852 u8 reserved_at_10[0x10];
5853
5854 u8 reserved_at_20[0x10];
5855 u8 op_mod[0x10];
5856
5857 u8 reserved_at_40[0x10];
5858 u8 function_id[0x10];
5859
5860 u8 reserved_at_60[0x20];
5861};
5862
5863struct mlx5_ifc_drain_dct_out_bits {
5864 u8 status[0x8];
5865 u8 reserved_at_8[0x18];
5866
5867 u8 syndrome[0x20];
5868
5869 u8 reserved_at_40[0x40];
5870};
5871
5872struct mlx5_ifc_drain_dct_in_bits {
5873 u8 opcode[0x10];
5874 u8 reserved_at_10[0x10];
5875
5876 u8 reserved_at_20[0x10];
5877 u8 op_mod[0x10];
5878
5879 u8 reserved_at_40[0x8];
5880 u8 dctn[0x18];
5881
5882 u8 reserved_at_60[0x20];
5883};
5884
5885struct mlx5_ifc_disable_hca_out_bits {
5886 u8 status[0x8];
5887 u8 reserved_at_8[0x18];
5888
5889 u8 syndrome[0x20];
5890
5891 u8 reserved_at_40[0x20];
5892};
5893
5894struct mlx5_ifc_disable_hca_in_bits {
5895 u8 opcode[0x10];
5896 u8 reserved_at_10[0x10];
5897
5898 u8 reserved_at_20[0x10];
5899 u8 op_mod[0x10];
5900
5901 u8 reserved_at_40[0x10];
5902 u8 function_id[0x10];
5903
5904 u8 reserved_at_60[0x20];
5905};
5906
5907struct mlx5_ifc_detach_from_mcg_out_bits {
5908 u8 status[0x8];
5909 u8 reserved_at_8[0x18];
5910
5911 u8 syndrome[0x20];
5912
5913 u8 reserved_at_40[0x40];
5914};
5915
5916struct mlx5_ifc_detach_from_mcg_in_bits {
5917 u8 opcode[0x10];
5918 u8 reserved_at_10[0x10];
5919
5920 u8 reserved_at_20[0x10];
5921 u8 op_mod[0x10];
5922
5923 u8 reserved_at_40[0x8];
5924 u8 qpn[0x18];
5925
5926 u8 reserved_at_60[0x20];
5927
5928 u8 multicast_gid[16][0x8];
5929};
5930
5931struct mlx5_ifc_destroy_xrq_out_bits {
5932 u8 status[0x8];
5933 u8 reserved_at_8[0x18];
5934
5935 u8 syndrome[0x20];
5936
5937 u8 reserved_at_40[0x40];
5938};
5939
5940struct mlx5_ifc_destroy_xrq_in_bits {
5941 u8 opcode[0x10];
5942 u8 reserved_at_10[0x10];
5943
5944 u8 reserved_at_20[0x10];
5945 u8 op_mod[0x10];
5946
5947 u8 reserved_at_40[0x8];
5948 u8 xrqn[0x18];
5949
5950 u8 reserved_at_60[0x20];
5951};
5952
5953struct mlx5_ifc_destroy_xrc_srq_out_bits {
5954 u8 status[0x8];
5955 u8 reserved_at_8[0x18];
5956
5957 u8 syndrome[0x20];
5958
5959 u8 reserved_at_40[0x40];
5960};
5961
5962struct mlx5_ifc_destroy_xrc_srq_in_bits {
5963 u8 opcode[0x10];
5964 u8 reserved_at_10[0x10];
5965
5966 u8 reserved_at_20[0x10];
5967 u8 op_mod[0x10];
5968
5969 u8 reserved_at_40[0x8];
5970 u8 xrc_srqn[0x18];
5971
5972 u8 reserved_at_60[0x20];
5973};
5974
5975struct mlx5_ifc_destroy_tis_out_bits {
5976 u8 status[0x8];
5977 u8 reserved_at_8[0x18];
5978
5979 u8 syndrome[0x20];
5980
5981 u8 reserved_at_40[0x40];
5982};
5983
5984struct mlx5_ifc_destroy_tis_in_bits {
5985 u8 opcode[0x10];
5986 u8 reserved_at_10[0x10];
5987
5988 u8 reserved_at_20[0x10];
5989 u8 op_mod[0x10];
5990
5991 u8 reserved_at_40[0x8];
5992 u8 tisn[0x18];
5993
5994 u8 reserved_at_60[0x20];
5995};
5996
5997struct mlx5_ifc_destroy_tir_out_bits {
5998 u8 status[0x8];
5999 u8 reserved_at_8[0x18];
6000
6001 u8 syndrome[0x20];
6002
6003 u8 reserved_at_40[0x40];
6004};
6005
6006struct mlx5_ifc_destroy_tir_in_bits {
6007 u8 opcode[0x10];
6008 u8 reserved_at_10[0x10];
6009
6010 u8 reserved_at_20[0x10];
6011 u8 op_mod[0x10];
6012
6013 u8 reserved_at_40[0x8];
6014 u8 tirn[0x18];
6015
6016 u8 reserved_at_60[0x20];
6017};
6018
6019struct mlx5_ifc_destroy_srq_out_bits {
6020 u8 status[0x8];
6021 u8 reserved_at_8[0x18];
6022
6023 u8 syndrome[0x20];
6024
6025 u8 reserved_at_40[0x40];
6026};
6027
6028struct mlx5_ifc_destroy_srq_in_bits {
6029 u8 opcode[0x10];
6030 u8 reserved_at_10[0x10];
6031
6032 u8 reserved_at_20[0x10];
6033 u8 op_mod[0x10];
6034
6035 u8 reserved_at_40[0x8];
6036 u8 srqn[0x18];
6037
6038 u8 reserved_at_60[0x20];
6039};
6040
6041struct mlx5_ifc_destroy_sq_out_bits {
6042 u8 status[0x8];
6043 u8 reserved_at_8[0x18];
6044
6045 u8 syndrome[0x20];
6046
6047 u8 reserved_at_40[0x40];
6048};
6049
6050struct mlx5_ifc_destroy_sq_in_bits {
6051 u8 opcode[0x10];
6052 u8 reserved_at_10[0x10];
6053
6054 u8 reserved_at_20[0x10];
6055 u8 op_mod[0x10];
6056
6057 u8 reserved_at_40[0x8];
6058 u8 sqn[0x18];
6059
6060 u8 reserved_at_60[0x20];
6061};
6062
6063struct mlx5_ifc_destroy_scheduling_element_out_bits {
6064 u8 status[0x8];
6065 u8 reserved_at_8[0x18];
6066
6067 u8 syndrome[0x20];
6068
6069 u8 reserved_at_40[0x1c0];
6070};
6071
6072struct mlx5_ifc_destroy_scheduling_element_in_bits {
6073 u8 opcode[0x10];
6074 u8 reserved_at_10[0x10];
6075
6076 u8 reserved_at_20[0x10];
6077 u8 op_mod[0x10];
6078
6079 u8 scheduling_hierarchy[0x8];
6080 u8 reserved_at_48[0x18];
6081
6082 u8 scheduling_element_id[0x20];
6083
6084 u8 reserved_at_80[0x180];
6085};
6086
6087struct mlx5_ifc_destroy_rqt_out_bits {
6088 u8 status[0x8];
6089 u8 reserved_at_8[0x18];
6090
6091 u8 syndrome[0x20];
6092
6093 u8 reserved_at_40[0x40];
6094};
6095
6096struct mlx5_ifc_destroy_rqt_in_bits {
6097 u8 opcode[0x10];
6098 u8 reserved_at_10[0x10];
6099
6100 u8 reserved_at_20[0x10];
6101 u8 op_mod[0x10];
6102
6103 u8 reserved_at_40[0x8];
6104 u8 rqtn[0x18];
6105
6106 u8 reserved_at_60[0x20];
6107};
6108
6109struct mlx5_ifc_destroy_rq_out_bits {
6110 u8 status[0x8];
6111 u8 reserved_at_8[0x18];
6112
6113 u8 syndrome[0x20];
6114
6115 u8 reserved_at_40[0x40];
6116};
6117
6118struct mlx5_ifc_destroy_rq_in_bits {
6119 u8 opcode[0x10];
6120 u8 reserved_at_10[0x10];
6121
6122 u8 reserved_at_20[0x10];
6123 u8 op_mod[0x10];
6124
6125 u8 reserved_at_40[0x8];
6126 u8 rqn[0x18];
6127
6128 u8 reserved_at_60[0x20];
6129};
6130
6131struct mlx5_ifc_set_delay_drop_params_in_bits {
6132 u8 opcode[0x10];
6133 u8 reserved_at_10[0x10];
6134
6135 u8 reserved_at_20[0x10];
6136 u8 op_mod[0x10];
6137
6138 u8 reserved_at_40[0x20];
6139
6140 u8 reserved_at_60[0x10];
6141 u8 delay_drop_timeout[0x10];
6142};
6143
6144struct mlx5_ifc_set_delay_drop_params_out_bits {
6145 u8 status[0x8];
6146 u8 reserved_at_8[0x18];
6147
6148 u8 syndrome[0x20];
6149
6150 u8 reserved_at_40[0x40];
6151};
6152
6153struct mlx5_ifc_destroy_rmp_out_bits {
6154 u8 status[0x8];
6155 u8 reserved_at_8[0x18];
6156
6157 u8 syndrome[0x20];
6158
6159 u8 reserved_at_40[0x40];
6160};
6161
6162struct mlx5_ifc_destroy_rmp_in_bits {
6163 u8 opcode[0x10];
6164 u8 reserved_at_10[0x10];
6165
6166 u8 reserved_at_20[0x10];
6167 u8 op_mod[0x10];
6168
6169 u8 reserved_at_40[0x8];
6170 u8 rmpn[0x18];
6171
6172 u8 reserved_at_60[0x20];
6173};
6174
6175struct mlx5_ifc_destroy_qp_out_bits {
6176 u8 status[0x8];
6177 u8 reserved_at_8[0x18];
6178
6179 u8 syndrome[0x20];
6180
6181 u8 reserved_at_40[0x40];
6182};
6183
6184struct mlx5_ifc_destroy_qp_in_bits {
6185 u8 opcode[0x10];
6186 u8 reserved_at_10[0x10];
6187
6188 u8 reserved_at_20[0x10];
6189 u8 op_mod[0x10];
6190
6191 u8 reserved_at_40[0x8];
6192 u8 qpn[0x18];
6193
6194 u8 reserved_at_60[0x20];
6195};
6196
6197struct mlx5_ifc_destroy_psv_out_bits {
6198 u8 status[0x8];
6199 u8 reserved_at_8[0x18];
6200
6201 u8 syndrome[0x20];
6202
6203 u8 reserved_at_40[0x40];
6204};
6205
6206struct mlx5_ifc_destroy_psv_in_bits {
6207 u8 opcode[0x10];
6208 u8 reserved_at_10[0x10];
6209
6210 u8 reserved_at_20[0x10];
6211 u8 op_mod[0x10];
6212
6213 u8 reserved_at_40[0x8];
6214 u8 psvn[0x18];
6215
6216 u8 reserved_at_60[0x20];
6217};
6218
6219struct mlx5_ifc_destroy_mkey_out_bits {
6220 u8 status[0x8];
6221 u8 reserved_at_8[0x18];
6222
6223 u8 syndrome[0x20];
6224
6225 u8 reserved_at_40[0x40];
6226};
6227
6228struct mlx5_ifc_destroy_mkey_in_bits {
6229 u8 opcode[0x10];
6230 u8 reserved_at_10[0x10];
6231
6232 u8 reserved_at_20[0x10];
6233 u8 op_mod[0x10];
6234
6235 u8 reserved_at_40[0x8];
6236 u8 mkey_index[0x18];
6237
6238 u8 reserved_at_60[0x20];
6239};
6240
6241struct mlx5_ifc_destroy_flow_table_out_bits {
6242 u8 status[0x8];
6243 u8 reserved_at_8[0x18];
6244
6245 u8 syndrome[0x20];
6246
6247 u8 reserved_at_40[0x40];
6248};
6249
6250struct mlx5_ifc_destroy_flow_table_in_bits {
6251 u8 opcode[0x10];
6252 u8 reserved_at_10[0x10];
6253
6254 u8 reserved_at_20[0x10];
6255 u8 op_mod[0x10];
6256
6257 u8 other_vport[0x1];
6258 u8 reserved_at_41[0xf];
6259 u8 vport_number[0x10];
6260
6261 u8 reserved_at_60[0x20];
6262
6263 u8 table_type[0x8];
6264 u8 reserved_at_88[0x18];
6265
6266 u8 reserved_at_a0[0x8];
6267 u8 table_id[0x18];
6268
6269 u8 reserved_at_c0[0x140];
6270};
6271
6272struct mlx5_ifc_destroy_flow_group_out_bits {
6273 u8 status[0x8];
6274 u8 reserved_at_8[0x18];
6275
6276 u8 syndrome[0x20];
6277
6278 u8 reserved_at_40[0x40];
6279};
6280
6281struct mlx5_ifc_destroy_flow_group_in_bits {
6282 u8 opcode[0x10];
6283 u8 reserved_at_10[0x10];
6284
6285 u8 reserved_at_20[0x10];
6286 u8 op_mod[0x10];
6287
6288 u8 other_vport[0x1];
6289 u8 reserved_at_41[0xf];
6290 u8 vport_number[0x10];
6291
6292 u8 reserved_at_60[0x20];
6293
6294 u8 table_type[0x8];
6295 u8 reserved_at_88[0x18];
6296
6297 u8 reserved_at_a0[0x8];
6298 u8 table_id[0x18];
6299
6300 u8 group_id[0x20];
6301
6302 u8 reserved_at_e0[0x120];
6303};
6304
6305struct mlx5_ifc_destroy_eq_out_bits {
6306 u8 status[0x8];
6307 u8 reserved_at_8[0x18];
6308
6309 u8 syndrome[0x20];
6310
6311 u8 reserved_at_40[0x40];
6312};
6313
6314struct mlx5_ifc_destroy_eq_in_bits {
6315 u8 opcode[0x10];
6316 u8 reserved_at_10[0x10];
6317
6318 u8 reserved_at_20[0x10];
6319 u8 op_mod[0x10];
6320
6321 u8 reserved_at_40[0x18];
6322 u8 eq_number[0x8];
6323
6324 u8 reserved_at_60[0x20];
6325};
6326
6327struct mlx5_ifc_destroy_dct_out_bits {
6328 u8 status[0x8];
6329 u8 reserved_at_8[0x18];
6330
6331 u8 syndrome[0x20];
6332
6333 u8 reserved_at_40[0x40];
6334};
6335
6336struct mlx5_ifc_destroy_dct_in_bits {
6337 u8 opcode[0x10];
6338 u8 reserved_at_10[0x10];
6339
6340 u8 reserved_at_20[0x10];
6341 u8 op_mod[0x10];
6342
6343 u8 reserved_at_40[0x8];
6344 u8 dctn[0x18];
6345
6346 u8 reserved_at_60[0x20];
6347};
6348
6349struct mlx5_ifc_destroy_cq_out_bits {
6350 u8 status[0x8];
6351 u8 reserved_at_8[0x18];
6352
6353 u8 syndrome[0x20];
6354
6355 u8 reserved_at_40[0x40];
6356};
6357
6358struct mlx5_ifc_destroy_cq_in_bits {
6359 u8 opcode[0x10];
6360 u8 reserved_at_10[0x10];
6361
6362 u8 reserved_at_20[0x10];
6363 u8 op_mod[0x10];
6364
6365 u8 reserved_at_40[0x8];
6366 u8 cqn[0x18];
6367
6368 u8 reserved_at_60[0x20];
6369};
6370
6371struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6372 u8 status[0x8];
6373 u8 reserved_at_8[0x18];
6374
6375 u8 syndrome[0x20];
6376
6377 u8 reserved_at_40[0x40];
6378};
6379
6380struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6381 u8 opcode[0x10];
6382 u8 reserved_at_10[0x10];
6383
6384 u8 reserved_at_20[0x10];
6385 u8 op_mod[0x10];
6386
6387 u8 reserved_at_40[0x20];
6388
6389 u8 reserved_at_60[0x10];
6390 u8 vxlan_udp_port[0x10];
6391};
6392
6393struct mlx5_ifc_delete_l2_table_entry_out_bits {
6394 u8 status[0x8];
6395 u8 reserved_at_8[0x18];
6396
6397 u8 syndrome[0x20];
6398
6399 u8 reserved_at_40[0x40];
6400};
6401
6402struct mlx5_ifc_delete_l2_table_entry_in_bits {
6403 u8 opcode[0x10];
6404 u8 reserved_at_10[0x10];
6405
6406 u8 reserved_at_20[0x10];
6407 u8 op_mod[0x10];
6408
6409 u8 reserved_at_40[0x60];
6410
6411 u8 reserved_at_a0[0x8];
6412 u8 table_index[0x18];
6413
6414 u8 reserved_at_c0[0x140];
6415};
6416
6417struct mlx5_ifc_delete_fte_out_bits {
6418 u8 status[0x8];
6419 u8 reserved_at_8[0x18];
6420
6421 u8 syndrome[0x20];
6422
6423 u8 reserved_at_40[0x40];
6424};
6425
6426struct mlx5_ifc_delete_fte_in_bits {
6427 u8 opcode[0x10];
6428 u8 reserved_at_10[0x10];
6429
6430 u8 reserved_at_20[0x10];
6431 u8 op_mod[0x10];
6432
6433 u8 other_vport[0x1];
6434 u8 reserved_at_41[0xf];
6435 u8 vport_number[0x10];
6436
6437 u8 reserved_at_60[0x20];
6438
6439 u8 table_type[0x8];
6440 u8 reserved_at_88[0x18];
6441
6442 u8 reserved_at_a0[0x8];
6443 u8 table_id[0x18];
6444
6445 u8 reserved_at_c0[0x40];
6446
6447 u8 flow_index[0x20];
6448
6449 u8 reserved_at_120[0xe0];
6450};
6451
6452struct mlx5_ifc_dealloc_xrcd_out_bits {
6453 u8 status[0x8];
6454 u8 reserved_at_8[0x18];
6455
6456 u8 syndrome[0x20];
6457
6458 u8 reserved_at_40[0x40];
6459};
6460
6461struct mlx5_ifc_dealloc_xrcd_in_bits {
6462 u8 opcode[0x10];
6463 u8 reserved_at_10[0x10];
6464
6465 u8 reserved_at_20[0x10];
6466 u8 op_mod[0x10];
6467
6468 u8 reserved_at_40[0x8];
6469 u8 xrcd[0x18];
6470
6471 u8 reserved_at_60[0x20];
6472};
6473
6474struct mlx5_ifc_dealloc_uar_out_bits {
6475 u8 status[0x8];
6476 u8 reserved_at_8[0x18];
6477
6478 u8 syndrome[0x20];
6479
6480 u8 reserved_at_40[0x40];
6481};
6482
6483struct mlx5_ifc_dealloc_uar_in_bits {
6484 u8 opcode[0x10];
6485 u8 reserved_at_10[0x10];
6486
6487 u8 reserved_at_20[0x10];
6488 u8 op_mod[0x10];
6489
6490 u8 reserved_at_40[0x8];
6491 u8 uar[0x18];
6492
6493 u8 reserved_at_60[0x20];
6494};
6495
6496struct mlx5_ifc_dealloc_transport_domain_out_bits {
6497 u8 status[0x8];
6498 u8 reserved_at_8[0x18];
6499
6500 u8 syndrome[0x20];
6501
6502 u8 reserved_at_40[0x40];
6503};
6504
6505struct mlx5_ifc_dealloc_transport_domain_in_bits {
6506 u8 opcode[0x10];
6507 u8 reserved_at_10[0x10];
6508
6509 u8 reserved_at_20[0x10];
6510 u8 op_mod[0x10];
6511
6512 u8 reserved_at_40[0x8];
6513 u8 transport_domain[0x18];
6514
6515 u8 reserved_at_60[0x20];
6516};
6517
6518struct mlx5_ifc_dealloc_q_counter_out_bits {
6519 u8 status[0x8];
6520 u8 reserved_at_8[0x18];
6521
6522 u8 syndrome[0x20];
6523
6524 u8 reserved_at_40[0x40];
6525};
6526
6527struct mlx5_ifc_dealloc_q_counter_in_bits {
6528 u8 opcode[0x10];
6529 u8 reserved_at_10[0x10];
6530
6531 u8 reserved_at_20[0x10];
6532 u8 op_mod[0x10];
6533
6534 u8 reserved_at_40[0x18];
6535 u8 counter_set_id[0x8];
6536
6537 u8 reserved_at_60[0x20];
6538};
6539
6540struct mlx5_ifc_dealloc_pd_out_bits {
6541 u8 status[0x8];
6542 u8 reserved_at_8[0x18];
6543
6544 u8 syndrome[0x20];
6545
6546 u8 reserved_at_40[0x40];
6547};
6548
6549struct mlx5_ifc_dealloc_pd_in_bits {
6550 u8 opcode[0x10];
6551 u8 reserved_at_10[0x10];
6552
6553 u8 reserved_at_20[0x10];
6554 u8 op_mod[0x10];
6555
6556 u8 reserved_at_40[0x8];
6557 u8 pd[0x18];
6558
6559 u8 reserved_at_60[0x20];
6560};
6561
6562struct mlx5_ifc_dealloc_flow_counter_out_bits {
6563 u8 status[0x8];
6564 u8 reserved_at_8[0x18];
6565
6566 u8 syndrome[0x20];
6567
6568 u8 reserved_at_40[0x40];
6569};
6570
6571struct mlx5_ifc_dealloc_flow_counter_in_bits {
6572 u8 opcode[0x10];
6573 u8 reserved_at_10[0x10];
6574
6575 u8 reserved_at_20[0x10];
6576 u8 op_mod[0x10];
6577
6578 u8 flow_counter_id[0x20];
6579
6580 u8 reserved_at_60[0x20];
6581};
6582
6583struct mlx5_ifc_create_xrq_out_bits {
6584 u8 status[0x8];
6585 u8 reserved_at_8[0x18];
6586
6587 u8 syndrome[0x20];
6588
6589 u8 reserved_at_40[0x8];
6590 u8 xrqn[0x18];
6591
6592 u8 reserved_at_60[0x20];
6593};
6594
6595struct mlx5_ifc_create_xrq_in_bits {
6596 u8 opcode[0x10];
6597 u8 reserved_at_10[0x10];
6598
6599 u8 reserved_at_20[0x10];
6600 u8 op_mod[0x10];
6601
6602 u8 reserved_at_40[0x40];
6603
6604 struct mlx5_ifc_xrqc_bits xrq_context;
6605};
6606
6607struct mlx5_ifc_create_xrc_srq_out_bits {
6608 u8 status[0x8];
6609 u8 reserved_at_8[0x18];
6610
6611 u8 syndrome[0x20];
6612
6613 u8 reserved_at_40[0x8];
6614 u8 xrc_srqn[0x18];
6615
6616 u8 reserved_at_60[0x20];
6617};
6618
6619struct mlx5_ifc_create_xrc_srq_in_bits {
6620 u8 opcode[0x10];
6621 u8 reserved_at_10[0x10];
6622
6623 u8 reserved_at_20[0x10];
6624 u8 op_mod[0x10];
6625
6626 u8 reserved_at_40[0x40];
6627
6628 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6629
6630 u8 reserved_at_280[0x600];
6631
6632 u8 pas[0][0x40];
6633};
6634
6635struct mlx5_ifc_create_tis_out_bits {
6636 u8 status[0x8];
6637 u8 reserved_at_8[0x18];
6638
6639 u8 syndrome[0x20];
6640
6641 u8 reserved_at_40[0x8];
6642 u8 tisn[0x18];
6643
6644 u8 reserved_at_60[0x20];
6645};
6646
6647struct mlx5_ifc_create_tis_in_bits {
6648 u8 opcode[0x10];
6649 u8 reserved_at_10[0x10];
6650
6651 u8 reserved_at_20[0x10];
6652 u8 op_mod[0x10];
6653
6654 u8 reserved_at_40[0xc0];
6655
6656 struct mlx5_ifc_tisc_bits ctx;
6657};
6658
6659struct mlx5_ifc_create_tir_out_bits {
6660 u8 status[0x8];
6661 u8 reserved_at_8[0x18];
6662
6663 u8 syndrome[0x20];
6664
6665 u8 reserved_at_40[0x8];
6666 u8 tirn[0x18];
6667
6668 u8 reserved_at_60[0x20];
6669};
6670
6671struct mlx5_ifc_create_tir_in_bits {
6672 u8 opcode[0x10];
6673 u8 reserved_at_10[0x10];
6674
6675 u8 reserved_at_20[0x10];
6676 u8 op_mod[0x10];
6677
6678 u8 reserved_at_40[0xc0];
6679
6680 struct mlx5_ifc_tirc_bits ctx;
6681};
6682
6683struct mlx5_ifc_create_srq_out_bits {
6684 u8 status[0x8];
6685 u8 reserved_at_8[0x18];
6686
6687 u8 syndrome[0x20];
6688
6689 u8 reserved_at_40[0x8];
6690 u8 srqn[0x18];
6691
6692 u8 reserved_at_60[0x20];
6693};
6694
6695struct mlx5_ifc_create_srq_in_bits {
6696 u8 opcode[0x10];
6697 u8 reserved_at_10[0x10];
6698
6699 u8 reserved_at_20[0x10];
6700 u8 op_mod[0x10];
6701
6702 u8 reserved_at_40[0x40];
6703
6704 struct mlx5_ifc_srqc_bits srq_context_entry;
6705
6706 u8 reserved_at_280[0x600];
6707
6708 u8 pas[0][0x40];
6709};
6710
6711struct mlx5_ifc_create_sq_out_bits {
6712 u8 status[0x8];
6713 u8 reserved_at_8[0x18];
6714
6715 u8 syndrome[0x20];
6716
6717 u8 reserved_at_40[0x8];
6718 u8 sqn[0x18];
6719
6720 u8 reserved_at_60[0x20];
6721};
6722
6723struct mlx5_ifc_create_sq_in_bits {
6724 u8 opcode[0x10];
6725 u8 reserved_at_10[0x10];
6726
6727 u8 reserved_at_20[0x10];
6728 u8 op_mod[0x10];
6729
6730 u8 reserved_at_40[0xc0];
6731
6732 struct mlx5_ifc_sqc_bits ctx;
6733};
6734
6735struct mlx5_ifc_create_scheduling_element_out_bits {
6736 u8 status[0x8];
6737 u8 reserved_at_8[0x18];
6738
6739 u8 syndrome[0x20];
6740
6741 u8 reserved_at_40[0x40];
6742
6743 u8 scheduling_element_id[0x20];
6744
6745 u8 reserved_at_a0[0x160];
6746};
6747
6748struct mlx5_ifc_create_scheduling_element_in_bits {
6749 u8 opcode[0x10];
6750 u8 reserved_at_10[0x10];
6751
6752 u8 reserved_at_20[0x10];
6753 u8 op_mod[0x10];
6754
6755 u8 scheduling_hierarchy[0x8];
6756 u8 reserved_at_48[0x18];
6757
6758 u8 reserved_at_60[0xa0];
6759
6760 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6761
6762 u8 reserved_at_300[0x100];
6763};
6764
6765struct mlx5_ifc_create_rqt_out_bits {
6766 u8 status[0x8];
6767 u8 reserved_at_8[0x18];
6768
6769 u8 syndrome[0x20];
6770
6771 u8 reserved_at_40[0x8];
6772 u8 rqtn[0x18];
6773
6774 u8 reserved_at_60[0x20];
6775};
6776
6777struct mlx5_ifc_create_rqt_in_bits {
6778 u8 opcode[0x10];
6779 u8 reserved_at_10[0x10];
6780
6781 u8 reserved_at_20[0x10];
6782 u8 op_mod[0x10];
6783
6784 u8 reserved_at_40[0xc0];
6785
6786 struct mlx5_ifc_rqtc_bits rqt_context;
6787};
6788
6789struct mlx5_ifc_create_rq_out_bits {
6790 u8 status[0x8];
6791 u8 reserved_at_8[0x18];
6792
6793 u8 syndrome[0x20];
6794
6795 u8 reserved_at_40[0x8];
6796 u8 rqn[0x18];
6797
6798 u8 reserved_at_60[0x20];
6799};
6800
6801struct mlx5_ifc_create_rq_in_bits {
6802 u8 opcode[0x10];
6803 u8 reserved_at_10[0x10];
6804
6805 u8 reserved_at_20[0x10];
6806 u8 op_mod[0x10];
6807
6808 u8 reserved_at_40[0xc0];
6809
6810 struct mlx5_ifc_rqc_bits ctx;
6811};
6812
6813struct mlx5_ifc_create_rmp_out_bits {
6814 u8 status[0x8];
6815 u8 reserved_at_8[0x18];
6816
6817 u8 syndrome[0x20];
6818
6819 u8 reserved_at_40[0x8];
6820 u8 rmpn[0x18];
6821
6822 u8 reserved_at_60[0x20];
6823};
6824
6825struct mlx5_ifc_create_rmp_in_bits {
6826 u8 opcode[0x10];
6827 u8 reserved_at_10[0x10];
6828
6829 u8 reserved_at_20[0x10];
6830 u8 op_mod[0x10];
6831
6832 u8 reserved_at_40[0xc0];
6833
6834 struct mlx5_ifc_rmpc_bits ctx;
6835};
6836
6837struct mlx5_ifc_create_qp_out_bits {
6838 u8 status[0x8];
6839 u8 reserved_at_8[0x18];
6840
6841 u8 syndrome[0x20];
6842
6843 u8 reserved_at_40[0x8];
6844 u8 qpn[0x18];
6845
6846 u8 reserved_at_60[0x20];
6847};
6848
6849struct mlx5_ifc_create_qp_in_bits {
6850 u8 opcode[0x10];
6851 u8 reserved_at_10[0x10];
6852
6853 u8 reserved_at_20[0x10];
6854 u8 op_mod[0x10];
6855
6856 u8 reserved_at_40[0x40];
6857
6858 u8 opt_param_mask[0x20];
6859
6860 u8 reserved_at_a0[0x20];
6861
6862 struct mlx5_ifc_qpc_bits qpc;
6863
6864 u8 reserved_at_800[0x80];
6865
6866 u8 pas[0][0x40];
6867};
6868
6869struct mlx5_ifc_create_psv_out_bits {
6870 u8 status[0x8];
6871 u8 reserved_at_8[0x18];
6872
6873 u8 syndrome[0x20];
6874
6875 u8 reserved_at_40[0x40];
6876
6877 u8 reserved_at_80[0x8];
6878 u8 psv0_index[0x18];
6879
6880 u8 reserved_at_a0[0x8];
6881 u8 psv1_index[0x18];
6882
6883 u8 reserved_at_c0[0x8];
6884 u8 psv2_index[0x18];
6885
6886 u8 reserved_at_e0[0x8];
6887 u8 psv3_index[0x18];
6888};
6889
6890struct mlx5_ifc_create_psv_in_bits {
6891 u8 opcode[0x10];
6892 u8 reserved_at_10[0x10];
6893
6894 u8 reserved_at_20[0x10];
6895 u8 op_mod[0x10];
6896
6897 u8 num_psv[0x4];
6898 u8 reserved_at_44[0x4];
6899 u8 pd[0x18];
6900
6901 u8 reserved_at_60[0x20];
6902};
6903
6904struct mlx5_ifc_create_mkey_out_bits {
6905 u8 status[0x8];
6906 u8 reserved_at_8[0x18];
6907
6908 u8 syndrome[0x20];
6909
6910 u8 reserved_at_40[0x8];
6911 u8 mkey_index[0x18];
6912
6913 u8 reserved_at_60[0x20];
6914};
6915
6916struct mlx5_ifc_create_mkey_in_bits {
6917 u8 opcode[0x10];
6918 u8 reserved_at_10[0x10];
6919
6920 u8 reserved_at_20[0x10];
6921 u8 op_mod[0x10];
6922
6923 u8 reserved_at_40[0x20];
6924
6925 u8 pg_access[0x1];
6926 u8 reserved_at_61[0x1f];
6927
6928 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6929
6930 u8 reserved_at_280[0x80];
6931
6932 u8 translations_octword_actual_size[0x20];
6933
6934 u8 reserved_at_320[0x560];
6935
6936 u8 klm_pas_mtt[0][0x20];
6937};
6938
6939struct mlx5_ifc_create_flow_table_out_bits {
6940 u8 status[0x8];
6941 u8 reserved_at_8[0x18];
6942
6943 u8 syndrome[0x20];
6944
6945 u8 reserved_at_40[0x8];
6946 u8 table_id[0x18];
6947
6948 u8 reserved_at_60[0x20];
6949};
6950
6951struct mlx5_ifc_flow_table_context_bits {
6952 u8 encap_en[0x1];
6953 u8 decap_en[0x1];
6954 u8 reserved_at_2[0x2];
6955 u8 table_miss_action[0x4];
6956 u8 level[0x8];
6957 u8 reserved_at_10[0x8];
6958 u8 log_size[0x8];
6959
6960 u8 reserved_at_20[0x8];
6961 u8 table_miss_id[0x18];
6962
6963 u8 reserved_at_40[0x8];
6964 u8 lag_master_next_table_id[0x18];
6965
6966 u8 reserved_at_60[0xe0];
6967};
6968
6969struct mlx5_ifc_create_flow_table_in_bits {
6970 u8 opcode[0x10];
6971 u8 reserved_at_10[0x10];
6972
6973 u8 reserved_at_20[0x10];
6974 u8 op_mod[0x10];
6975
6976 u8 other_vport[0x1];
6977 u8 reserved_at_41[0xf];
6978 u8 vport_number[0x10];
6979
6980 u8 reserved_at_60[0x20];
6981
6982 u8 table_type[0x8];
6983 u8 reserved_at_88[0x18];
6984
6985 u8 reserved_at_a0[0x20];
6986
6987 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6988};
6989
6990struct mlx5_ifc_create_flow_group_out_bits {
6991 u8 status[0x8];
6992 u8 reserved_at_8[0x18];
6993
6994 u8 syndrome[0x20];
6995
6996 u8 reserved_at_40[0x8];
6997 u8 group_id[0x18];
6998
6999 u8 reserved_at_60[0x20];
7000};
7001
7002enum {
7003 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7004 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7005 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7006 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7007};
7008
7009struct mlx5_ifc_create_flow_group_in_bits {
7010 u8 opcode[0x10];
7011 u8 reserved_at_10[0x10];
7012
7013 u8 reserved_at_20[0x10];
7014 u8 op_mod[0x10];
7015
7016 u8 other_vport[0x1];
7017 u8 reserved_at_41[0xf];
7018 u8 vport_number[0x10];
7019
7020 u8 reserved_at_60[0x20];
7021
7022 u8 table_type[0x8];
7023 u8 reserved_at_88[0x18];
7024
7025 u8 reserved_at_a0[0x8];
7026 u8 table_id[0x18];
7027
7028 u8 source_eswitch_owner_vhca_id_valid[0x1];
7029
7030 u8 reserved_at_c1[0x1f];
7031
7032 u8 start_flow_index[0x20];
7033
7034 u8 reserved_at_100[0x20];
7035
7036 u8 end_flow_index[0x20];
7037
7038 u8 reserved_at_140[0xa0];
7039
7040 u8 reserved_at_1e0[0x18];
7041 u8 match_criteria_enable[0x8];
7042
7043 struct mlx5_ifc_fte_match_param_bits match_criteria;
7044
7045 u8 reserved_at_1200[0xe00];
7046};
7047
7048struct mlx5_ifc_create_eq_out_bits {
7049 u8 status[0x8];
7050 u8 reserved_at_8[0x18];
7051
7052 u8 syndrome[0x20];
7053
7054 u8 reserved_at_40[0x18];
7055 u8 eq_number[0x8];
7056
7057 u8 reserved_at_60[0x20];
7058};
7059
7060struct mlx5_ifc_create_eq_in_bits {
7061 u8 opcode[0x10];
7062 u8 reserved_at_10[0x10];
7063
7064 u8 reserved_at_20[0x10];
7065 u8 op_mod[0x10];
7066
7067 u8 reserved_at_40[0x40];
7068
7069 struct mlx5_ifc_eqc_bits eq_context_entry;
7070
7071 u8 reserved_at_280[0x40];
7072
7073 u8 event_bitmask[0x40];
7074
7075 u8 reserved_at_300[0x580];
7076
7077 u8 pas[0][0x40];
7078};
7079
7080struct mlx5_ifc_create_dct_out_bits {
7081 u8 status[0x8];
7082 u8 reserved_at_8[0x18];
7083
7084 u8 syndrome[0x20];
7085
7086 u8 reserved_at_40[0x8];
7087 u8 dctn[0x18];
7088
7089 u8 reserved_at_60[0x20];
7090};
7091
7092struct mlx5_ifc_create_dct_in_bits {
7093 u8 opcode[0x10];
7094 u8 reserved_at_10[0x10];
7095
7096 u8 reserved_at_20[0x10];
7097 u8 op_mod[0x10];
7098
7099 u8 reserved_at_40[0x40];
7100
7101 struct mlx5_ifc_dctc_bits dct_context_entry;
7102
7103 u8 reserved_at_280[0x180];
7104};
7105
7106struct mlx5_ifc_create_cq_out_bits {
7107 u8 status[0x8];
7108 u8 reserved_at_8[0x18];
7109
7110 u8 syndrome[0x20];
7111
7112 u8 reserved_at_40[0x8];
7113 u8 cqn[0x18];
7114
7115 u8 reserved_at_60[0x20];
7116};
7117
7118struct mlx5_ifc_create_cq_in_bits {
7119 u8 opcode[0x10];
7120 u8 reserved_at_10[0x10];
7121
7122 u8 reserved_at_20[0x10];
7123 u8 op_mod[0x10];
7124
7125 u8 reserved_at_40[0x40];
7126
7127 struct mlx5_ifc_cqc_bits cq_context;
7128
7129 u8 reserved_at_280[0x600];
7130
7131 u8 pas[0][0x40];
7132};
7133
7134struct mlx5_ifc_config_int_moderation_out_bits {
7135 u8 status[0x8];
7136 u8 reserved_at_8[0x18];
7137
7138 u8 syndrome[0x20];
7139
7140 u8 reserved_at_40[0x4];
7141 u8 min_delay[0xc];
7142 u8 int_vector[0x10];
7143
7144 u8 reserved_at_60[0x20];
7145};
7146
7147enum {
7148 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7149 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7150};
7151
7152struct mlx5_ifc_config_int_moderation_in_bits {
7153 u8 opcode[0x10];
7154 u8 reserved_at_10[0x10];
7155
7156 u8 reserved_at_20[0x10];
7157 u8 op_mod[0x10];
7158
7159 u8 reserved_at_40[0x4];
7160 u8 min_delay[0xc];
7161 u8 int_vector[0x10];
7162
7163 u8 reserved_at_60[0x20];
7164};
7165
7166struct mlx5_ifc_attach_to_mcg_out_bits {
7167 u8 status[0x8];
7168 u8 reserved_at_8[0x18];
7169
7170 u8 syndrome[0x20];
7171
7172 u8 reserved_at_40[0x40];
7173};
7174
7175struct mlx5_ifc_attach_to_mcg_in_bits {
7176 u8 opcode[0x10];
7177 u8 reserved_at_10[0x10];
7178
7179 u8 reserved_at_20[0x10];
7180 u8 op_mod[0x10];
7181
7182 u8 reserved_at_40[0x8];
7183 u8 qpn[0x18];
7184
7185 u8 reserved_at_60[0x20];
7186
7187 u8 multicast_gid[16][0x8];
7188};
7189
7190struct mlx5_ifc_arm_xrq_out_bits {
7191 u8 status[0x8];
7192 u8 reserved_at_8[0x18];
7193
7194 u8 syndrome[0x20];
7195
7196 u8 reserved_at_40[0x40];
7197};
7198
7199struct mlx5_ifc_arm_xrq_in_bits {
7200 u8 opcode[0x10];
7201 u8 reserved_at_10[0x10];
7202
7203 u8 reserved_at_20[0x10];
7204 u8 op_mod[0x10];
7205
7206 u8 reserved_at_40[0x8];
7207 u8 xrqn[0x18];
7208
7209 u8 reserved_at_60[0x10];
7210 u8 lwm[0x10];
7211};
7212
7213struct mlx5_ifc_arm_xrc_srq_out_bits {
7214 u8 status[0x8];
7215 u8 reserved_at_8[0x18];
7216
7217 u8 syndrome[0x20];
7218
7219 u8 reserved_at_40[0x40];
7220};
7221
7222enum {
7223 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7224};
7225
7226struct mlx5_ifc_arm_xrc_srq_in_bits {
7227 u8 opcode[0x10];
7228 u8 reserved_at_10[0x10];
7229
7230 u8 reserved_at_20[0x10];
7231 u8 op_mod[0x10];
7232
7233 u8 reserved_at_40[0x8];
7234 u8 xrc_srqn[0x18];
7235
7236 u8 reserved_at_60[0x10];
7237 u8 lwm[0x10];
7238};
7239
7240struct mlx5_ifc_arm_rq_out_bits {
7241 u8 status[0x8];
7242 u8 reserved_at_8[0x18];
7243
7244 u8 syndrome[0x20];
7245
7246 u8 reserved_at_40[0x40];
7247};
7248
7249enum {
7250 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7251 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7252};
7253
7254struct mlx5_ifc_arm_rq_in_bits {
7255 u8 opcode[0x10];
7256 u8 reserved_at_10[0x10];
7257
7258 u8 reserved_at_20[0x10];
7259 u8 op_mod[0x10];
7260
7261 u8 reserved_at_40[0x8];
7262 u8 srq_number[0x18];
7263
7264 u8 reserved_at_60[0x10];
7265 u8 lwm[0x10];
7266};
7267
7268struct mlx5_ifc_arm_dct_out_bits {
7269 u8 status[0x8];
7270 u8 reserved_at_8[0x18];
7271
7272 u8 syndrome[0x20];
7273
7274 u8 reserved_at_40[0x40];
7275};
7276
7277struct mlx5_ifc_arm_dct_in_bits {
7278 u8 opcode[0x10];
7279 u8 reserved_at_10[0x10];
7280
7281 u8 reserved_at_20[0x10];
7282 u8 op_mod[0x10];
7283
7284 u8 reserved_at_40[0x8];
7285 u8 dct_number[0x18];
7286
7287 u8 reserved_at_60[0x20];
7288};
7289
7290struct mlx5_ifc_alloc_xrcd_out_bits {
7291 u8 status[0x8];
7292 u8 reserved_at_8[0x18];
7293
7294 u8 syndrome[0x20];
7295
7296 u8 reserved_at_40[0x8];
7297 u8 xrcd[0x18];
7298
7299 u8 reserved_at_60[0x20];
7300};
7301
7302struct mlx5_ifc_alloc_xrcd_in_bits {
7303 u8 opcode[0x10];
7304 u8 reserved_at_10[0x10];
7305
7306 u8 reserved_at_20[0x10];
7307 u8 op_mod[0x10];
7308
7309 u8 reserved_at_40[0x40];
7310};
7311
7312struct mlx5_ifc_alloc_uar_out_bits {
7313 u8 status[0x8];
7314 u8 reserved_at_8[0x18];
7315
7316 u8 syndrome[0x20];
7317
7318 u8 reserved_at_40[0x8];
7319 u8 uar[0x18];
7320
7321 u8 reserved_at_60[0x20];
7322};
7323
7324struct mlx5_ifc_alloc_uar_in_bits {
7325 u8 opcode[0x10];
7326 u8 reserved_at_10[0x10];
7327
7328 u8 reserved_at_20[0x10];
7329 u8 op_mod[0x10];
7330
7331 u8 reserved_at_40[0x40];
7332};
7333
7334struct mlx5_ifc_alloc_transport_domain_out_bits {
7335 u8 status[0x8];
7336 u8 reserved_at_8[0x18];
7337
7338 u8 syndrome[0x20];
7339
7340 u8 reserved_at_40[0x8];
7341 u8 transport_domain[0x18];
7342
7343 u8 reserved_at_60[0x20];
7344};
7345
7346struct mlx5_ifc_alloc_transport_domain_in_bits {
7347 u8 opcode[0x10];
7348 u8 reserved_at_10[0x10];
7349
7350 u8 reserved_at_20[0x10];
7351 u8 op_mod[0x10];
7352
7353 u8 reserved_at_40[0x40];
7354};
7355
7356struct mlx5_ifc_alloc_q_counter_out_bits {
7357 u8 status[0x8];
7358 u8 reserved_at_8[0x18];
7359
7360 u8 syndrome[0x20];
7361
7362 u8 reserved_at_40[0x18];
7363 u8 counter_set_id[0x8];
7364
7365 u8 reserved_at_60[0x20];
7366};
7367
7368struct mlx5_ifc_alloc_q_counter_in_bits {
7369 u8 opcode[0x10];
7370 u8 reserved_at_10[0x10];
7371
7372 u8 reserved_at_20[0x10];
7373 u8 op_mod[0x10];
7374
7375 u8 reserved_at_40[0x40];
7376};
7377
7378struct mlx5_ifc_alloc_pd_out_bits {
7379 u8 status[0x8];
7380 u8 reserved_at_8[0x18];
7381
7382 u8 syndrome[0x20];
7383
7384 u8 reserved_at_40[0x8];
7385 u8 pd[0x18];
7386
7387 u8 reserved_at_60[0x20];
7388};
7389
7390struct mlx5_ifc_alloc_pd_in_bits {
7391 u8 opcode[0x10];
7392 u8 reserved_at_10[0x10];
7393
7394 u8 reserved_at_20[0x10];
7395 u8 op_mod[0x10];
7396
7397 u8 reserved_at_40[0x40];
7398};
7399
7400struct mlx5_ifc_alloc_flow_counter_out_bits {
7401 u8 status[0x8];
7402 u8 reserved_at_8[0x18];
7403
7404 u8 syndrome[0x20];
7405
7406 u8 flow_counter_id[0x20];
7407
7408 u8 reserved_at_60[0x20];
7409};
7410
7411struct mlx5_ifc_alloc_flow_counter_in_bits {
7412 u8 opcode[0x10];
7413 u8 reserved_at_10[0x10];
7414
7415 u8 reserved_at_20[0x10];
7416 u8 op_mod[0x10];
7417
7418 u8 reserved_at_40[0x40];
7419};
7420
7421struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7422 u8 status[0x8];
7423 u8 reserved_at_8[0x18];
7424
7425 u8 syndrome[0x20];
7426
7427 u8 reserved_at_40[0x40];
7428};
7429
7430struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7431 u8 opcode[0x10];
7432 u8 reserved_at_10[0x10];
7433
7434 u8 reserved_at_20[0x10];
7435 u8 op_mod[0x10];
7436
7437 u8 reserved_at_40[0x20];
7438
7439 u8 reserved_at_60[0x10];
7440 u8 vxlan_udp_port[0x10];
7441};
7442
7443struct mlx5_ifc_set_pp_rate_limit_out_bits {
7444 u8 status[0x8];
7445 u8 reserved_at_8[0x18];
7446
7447 u8 syndrome[0x20];
7448
7449 u8 reserved_at_40[0x40];
7450};
7451
7452struct mlx5_ifc_set_pp_rate_limit_in_bits {
7453 u8 opcode[0x10];
7454 u8 reserved_at_10[0x10];
7455
7456 u8 reserved_at_20[0x10];
7457 u8 op_mod[0x10];
7458
7459 u8 reserved_at_40[0x10];
7460 u8 rate_limit_index[0x10];
7461
7462 u8 reserved_at_60[0x20];
7463
7464 u8 rate_limit[0x20];
7465
7466 u8 burst_upper_bound[0x20];
7467
7468 u8 reserved_at_c0[0x10];
7469 u8 typical_packet_size[0x10];
7470
7471 u8 reserved_at_e0[0x120];
7472};
7473
7474struct mlx5_ifc_access_register_out_bits {
7475 u8 status[0x8];
7476 u8 reserved_at_8[0x18];
7477
7478 u8 syndrome[0x20];
7479
7480 u8 reserved_at_40[0x40];
7481
7482 u8 register_data[0][0x20];
7483};
7484
7485enum {
7486 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7487 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7488};
7489
7490struct mlx5_ifc_access_register_in_bits {
7491 u8 opcode[0x10];
7492 u8 reserved_at_10[0x10];
7493
7494 u8 reserved_at_20[0x10];
7495 u8 op_mod[0x10];
7496
7497 u8 reserved_at_40[0x10];
7498 u8 register_id[0x10];
7499
7500 u8 argument[0x20];
7501
7502 u8 register_data[0][0x20];
7503};
7504
7505struct mlx5_ifc_sltp_reg_bits {
7506 u8 status[0x4];
7507 u8 version[0x4];
7508 u8 local_port[0x8];
7509 u8 pnat[0x2];
7510 u8 reserved_at_12[0x2];
7511 u8 lane[0x4];
7512 u8 reserved_at_18[0x8];
7513
7514 u8 reserved_at_20[0x20];
7515
7516 u8 reserved_at_40[0x7];
7517 u8 polarity[0x1];
7518 u8 ob_tap0[0x8];
7519 u8 ob_tap1[0x8];
7520 u8 ob_tap2[0x8];
7521
7522 u8 reserved_at_60[0xc];
7523 u8 ob_preemp_mode[0x4];
7524 u8 ob_reg[0x8];
7525 u8 ob_bias[0x8];
7526
7527 u8 reserved_at_80[0x20];
7528};
7529
7530struct mlx5_ifc_slrg_reg_bits {
7531 u8 status[0x4];
7532 u8 version[0x4];
7533 u8 local_port[0x8];
7534 u8 pnat[0x2];
7535 u8 reserved_at_12[0x2];
7536 u8 lane[0x4];
7537 u8 reserved_at_18[0x8];
7538
7539 u8 time_to_link_up[0x10];
7540 u8 reserved_at_30[0xc];
7541 u8 grade_lane_speed[0x4];
7542
7543 u8 grade_version[0x8];
7544 u8 grade[0x18];
7545
7546 u8 reserved_at_60[0x4];
7547 u8 height_grade_type[0x4];
7548 u8 height_grade[0x18];
7549
7550 u8 height_dz[0x10];
7551 u8 height_dv[0x10];
7552
7553 u8 reserved_at_a0[0x10];
7554 u8 height_sigma[0x10];
7555
7556 u8 reserved_at_c0[0x20];
7557
7558 u8 reserved_at_e0[0x4];
7559 u8 phase_grade_type[0x4];
7560 u8 phase_grade[0x18];
7561
7562 u8 reserved_at_100[0x8];
7563 u8 phase_eo_pos[0x8];
7564 u8 reserved_at_110[0x8];
7565 u8 phase_eo_neg[0x8];
7566
7567 u8 ffe_set_tested[0x10];
7568 u8 test_errors_per_lane[0x10];
7569};
7570
7571struct mlx5_ifc_pvlc_reg_bits {
7572 u8 reserved_at_0[0x8];
7573 u8 local_port[0x8];
7574 u8 reserved_at_10[0x10];
7575
7576 u8 reserved_at_20[0x1c];
7577 u8 vl_hw_cap[0x4];
7578
7579 u8 reserved_at_40[0x1c];
7580 u8 vl_admin[0x4];
7581
7582 u8 reserved_at_60[0x1c];
7583 u8 vl_operational[0x4];
7584};
7585
7586struct mlx5_ifc_pude_reg_bits {
7587 u8 swid[0x8];
7588 u8 local_port[0x8];
7589 u8 reserved_at_10[0x4];
7590 u8 admin_status[0x4];
7591 u8 reserved_at_18[0x4];
7592 u8 oper_status[0x4];
7593
7594 u8 reserved_at_20[0x60];
7595};
7596
7597struct mlx5_ifc_ptys_reg_bits {
7598 u8 reserved_at_0[0x1];
7599 u8 an_disable_admin[0x1];
7600 u8 an_disable_cap[0x1];
7601 u8 reserved_at_3[0x5];
7602 u8 local_port[0x8];
7603 u8 reserved_at_10[0xd];
7604 u8 proto_mask[0x3];
7605
7606 u8 an_status[0x4];
7607 u8 reserved_at_24[0x3c];
7608
7609 u8 eth_proto_capability[0x20];
7610
7611 u8 ib_link_width_capability[0x10];
7612 u8 ib_proto_capability[0x10];
7613
7614 u8 reserved_at_a0[0x20];
7615
7616 u8 eth_proto_admin[0x20];
7617
7618 u8 ib_link_width_admin[0x10];
7619 u8 ib_proto_admin[0x10];
7620
7621 u8 reserved_at_100[0x20];
7622
7623 u8 eth_proto_oper[0x20];
7624
7625 u8 ib_link_width_oper[0x10];
7626 u8 ib_proto_oper[0x10];
7627
7628 u8 reserved_at_160[0x1c];
7629 u8 connector_type[0x4];
7630
7631 u8 eth_proto_lp_advertise[0x20];
7632
7633 u8 reserved_at_1a0[0x60];
7634};
7635
7636struct mlx5_ifc_mlcr_reg_bits {
7637 u8 reserved_at_0[0x8];
7638 u8 local_port[0x8];
7639 u8 reserved_at_10[0x20];
7640
7641 u8 beacon_duration[0x10];
7642 u8 reserved_at_40[0x10];
7643
7644 u8 beacon_remain[0x10];
7645};
7646
7647struct mlx5_ifc_ptas_reg_bits {
7648 u8 reserved_at_0[0x20];
7649
7650 u8 algorithm_options[0x10];
7651 u8 reserved_at_30[0x4];
7652 u8 repetitions_mode[0x4];
7653 u8 num_of_repetitions[0x8];
7654
7655 u8 grade_version[0x8];
7656 u8 height_grade_type[0x4];
7657 u8 phase_grade_type[0x4];
7658 u8 height_grade_weight[0x8];
7659 u8 phase_grade_weight[0x8];
7660
7661 u8 gisim_measure_bits[0x10];
7662 u8 adaptive_tap_measure_bits[0x10];
7663
7664 u8 ber_bath_high_error_threshold[0x10];
7665 u8 ber_bath_mid_error_threshold[0x10];
7666
7667 u8 ber_bath_low_error_threshold[0x10];
7668 u8 one_ratio_high_threshold[0x10];
7669
7670 u8 one_ratio_high_mid_threshold[0x10];
7671 u8 one_ratio_low_mid_threshold[0x10];
7672
7673 u8 one_ratio_low_threshold[0x10];
7674 u8 ndeo_error_threshold[0x10];
7675
7676 u8 mixer_offset_step_size[0x10];
7677 u8 reserved_at_110[0x8];
7678 u8 mix90_phase_for_voltage_bath[0x8];
7679
7680 u8 mixer_offset_start[0x10];
7681 u8 mixer_offset_end[0x10];
7682
7683 u8 reserved_at_140[0x15];
7684 u8 ber_test_time[0xb];
7685};
7686
7687struct mlx5_ifc_pspa_reg_bits {
7688 u8 swid[0x8];
7689 u8 local_port[0x8];
7690 u8 sub_port[0x8];
7691 u8 reserved_at_18[0x8];
7692
7693 u8 reserved_at_20[0x20];
7694};
7695
7696struct mlx5_ifc_pqdr_reg_bits {
7697 u8 reserved_at_0[0x8];
7698 u8 local_port[0x8];
7699 u8 reserved_at_10[0x5];
7700 u8 prio[0x3];
7701 u8 reserved_at_18[0x6];
7702 u8 mode[0x2];
7703
7704 u8 reserved_at_20[0x20];
7705
7706 u8 reserved_at_40[0x10];
7707 u8 min_threshold[0x10];
7708
7709 u8 reserved_at_60[0x10];
7710 u8 max_threshold[0x10];
7711
7712 u8 reserved_at_80[0x10];
7713 u8 mark_probability_denominator[0x10];
7714
7715 u8 reserved_at_a0[0x60];
7716};
7717
7718struct mlx5_ifc_ppsc_reg_bits {
7719 u8 reserved_at_0[0x8];
7720 u8 local_port[0x8];
7721 u8 reserved_at_10[0x10];
7722
7723 u8 reserved_at_20[0x60];
7724
7725 u8 reserved_at_80[0x1c];
7726 u8 wrps_admin[0x4];
7727
7728 u8 reserved_at_a0[0x1c];
7729 u8 wrps_status[0x4];
7730
7731 u8 reserved_at_c0[0x8];
7732 u8 up_threshold[0x8];
7733 u8 reserved_at_d0[0x8];
7734 u8 down_threshold[0x8];
7735
7736 u8 reserved_at_e0[0x20];
7737
7738 u8 reserved_at_100[0x1c];
7739 u8 srps_admin[0x4];
7740
7741 u8 reserved_at_120[0x1c];
7742 u8 srps_status[0x4];
7743
7744 u8 reserved_at_140[0x40];
7745};
7746
7747struct mlx5_ifc_pplr_reg_bits {
7748 u8 reserved_at_0[0x8];
7749 u8 local_port[0x8];
7750 u8 reserved_at_10[0x10];
7751
7752 u8 reserved_at_20[0x8];
7753 u8 lb_cap[0x8];
7754 u8 reserved_at_30[0x8];
7755 u8 lb_en[0x8];
7756};
7757
7758struct mlx5_ifc_pplm_reg_bits {
7759 u8 reserved_at_0[0x8];
7760 u8 local_port[0x8];
7761 u8 reserved_at_10[0x10];
7762
7763 u8 reserved_at_20[0x20];
7764
7765 u8 port_profile_mode[0x8];
7766 u8 static_port_profile[0x8];
7767 u8 active_port_profile[0x8];
7768 u8 reserved_at_58[0x8];
7769
7770 u8 retransmission_active[0x8];
7771 u8 fec_mode_active[0x18];
7772
7773 u8 reserved_at_80[0x20];
7774};
7775
7776struct mlx5_ifc_ppcnt_reg_bits {
7777 u8 swid[0x8];
7778 u8 local_port[0x8];
7779 u8 pnat[0x2];
7780 u8 reserved_at_12[0x8];
7781 u8 grp[0x6];
7782
7783 u8 clr[0x1];
7784 u8 reserved_at_21[0x1c];
7785 u8 prio_tc[0x3];
7786
7787 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7788};
7789
7790struct mlx5_ifc_mpcnt_reg_bits {
7791 u8 reserved_at_0[0x8];
7792 u8 pcie_index[0x8];
7793 u8 reserved_at_10[0xa];
7794 u8 grp[0x6];
7795
7796 u8 clr[0x1];
7797 u8 reserved_at_21[0x1f];
7798
7799 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7800};
7801
7802struct mlx5_ifc_ppad_reg_bits {
7803 u8 reserved_at_0[0x3];
7804 u8 single_mac[0x1];
7805 u8 reserved_at_4[0x4];
7806 u8 local_port[0x8];
7807 u8 mac_47_32[0x10];
7808
7809 u8 mac_31_0[0x20];
7810
7811 u8 reserved_at_40[0x40];
7812};
7813
7814struct mlx5_ifc_pmtu_reg_bits {
7815 u8 reserved_at_0[0x8];
7816 u8 local_port[0x8];
7817 u8 reserved_at_10[0x10];
7818
7819 u8 max_mtu[0x10];
7820 u8 reserved_at_30[0x10];
7821
7822 u8 admin_mtu[0x10];
7823 u8 reserved_at_50[0x10];
7824
7825 u8 oper_mtu[0x10];
7826 u8 reserved_at_70[0x10];
7827};
7828
7829struct mlx5_ifc_pmpr_reg_bits {
7830 u8 reserved_at_0[0x8];
7831 u8 module[0x8];
7832 u8 reserved_at_10[0x10];
7833
7834 u8 reserved_at_20[0x18];
7835 u8 attenuation_5g[0x8];
7836
7837 u8 reserved_at_40[0x18];
7838 u8 attenuation_7g[0x8];
7839
7840 u8 reserved_at_60[0x18];
7841 u8 attenuation_12g[0x8];
7842};
7843
7844struct mlx5_ifc_pmpe_reg_bits {
7845 u8 reserved_at_0[0x8];
7846 u8 module[0x8];
7847 u8 reserved_at_10[0xc];
7848 u8 module_status[0x4];
7849
7850 u8 reserved_at_20[0x60];
7851};
7852
7853struct mlx5_ifc_pmpc_reg_bits {
7854 u8 module_state_updated[32][0x8];
7855};
7856
7857struct mlx5_ifc_pmlpn_reg_bits {
7858 u8 reserved_at_0[0x4];
7859 u8 mlpn_status[0x4];
7860 u8 local_port[0x8];
7861 u8 reserved_at_10[0x10];
7862
7863 u8 e[0x1];
7864 u8 reserved_at_21[0x1f];
7865};
7866
7867struct mlx5_ifc_pmlp_reg_bits {
7868 u8 rxtx[0x1];
7869 u8 reserved_at_1[0x7];
7870 u8 local_port[0x8];
7871 u8 reserved_at_10[0x8];
7872 u8 width[0x8];
7873
7874 u8 lane0_module_mapping[0x20];
7875
7876 u8 lane1_module_mapping[0x20];
7877
7878 u8 lane2_module_mapping[0x20];
7879
7880 u8 lane3_module_mapping[0x20];
7881
7882 u8 reserved_at_a0[0x160];
7883};
7884
7885struct mlx5_ifc_pmaos_reg_bits {
7886 u8 reserved_at_0[0x8];
7887 u8 module[0x8];
7888 u8 reserved_at_10[0x4];
7889 u8 admin_status[0x4];
7890 u8 reserved_at_18[0x4];
7891 u8 oper_status[0x4];
7892
7893 u8 ase[0x1];
7894 u8 ee[0x1];
7895 u8 reserved_at_22[0x1c];
7896 u8 e[0x2];
7897
7898 u8 reserved_at_40[0x40];
7899};
7900
7901struct mlx5_ifc_plpc_reg_bits {
7902 u8 reserved_at_0[0x4];
7903 u8 profile_id[0xc];
7904 u8 reserved_at_10[0x4];
7905 u8 proto_mask[0x4];
7906 u8 reserved_at_18[0x8];
7907
7908 u8 reserved_at_20[0x10];
7909 u8 lane_speed[0x10];
7910
7911 u8 reserved_at_40[0x17];
7912 u8 lpbf[0x1];
7913 u8 fec_mode_policy[0x8];
7914
7915 u8 retransmission_capability[0x8];
7916 u8 fec_mode_capability[0x18];
7917
7918 u8 retransmission_support_admin[0x8];
7919 u8 fec_mode_support_admin[0x18];
7920
7921 u8 retransmission_request_admin[0x8];
7922 u8 fec_mode_request_admin[0x18];
7923
7924 u8 reserved_at_c0[0x80];
7925};
7926
7927struct mlx5_ifc_plib_reg_bits {
7928 u8 reserved_at_0[0x8];
7929 u8 local_port[0x8];
7930 u8 reserved_at_10[0x8];
7931 u8 ib_port[0x8];
7932
7933 u8 reserved_at_20[0x60];
7934};
7935
7936struct mlx5_ifc_plbf_reg_bits {
7937 u8 reserved_at_0[0x8];
7938 u8 local_port[0x8];
7939 u8 reserved_at_10[0xd];
7940 u8 lbf_mode[0x3];
7941
7942 u8 reserved_at_20[0x20];
7943};
7944
7945struct mlx5_ifc_pipg_reg_bits {
7946 u8 reserved_at_0[0x8];
7947 u8 local_port[0x8];
7948 u8 reserved_at_10[0x10];
7949
7950 u8 dic[0x1];
7951 u8 reserved_at_21[0x19];
7952 u8 ipg[0x4];
7953 u8 reserved_at_3e[0x2];
7954};
7955
7956struct mlx5_ifc_pifr_reg_bits {
7957 u8 reserved_at_0[0x8];
7958 u8 local_port[0x8];
7959 u8 reserved_at_10[0x10];
7960
7961 u8 reserved_at_20[0xe0];
7962
7963 u8 port_filter[8][0x20];
7964
7965 u8 port_filter_update_en[8][0x20];
7966};
7967
7968struct mlx5_ifc_pfcc_reg_bits {
7969 u8 reserved_at_0[0x8];
7970 u8 local_port[0x8];
7971 u8 reserved_at_10[0xb];
7972 u8 ppan_mask_n[0x1];
7973 u8 minor_stall_mask[0x1];
7974 u8 critical_stall_mask[0x1];
7975 u8 reserved_at_1e[0x2];
7976
7977 u8 ppan[0x4];
7978 u8 reserved_at_24[0x4];
7979 u8 prio_mask_tx[0x8];
7980 u8 reserved_at_30[0x8];
7981 u8 prio_mask_rx[0x8];
7982
7983 u8 pptx[0x1];
7984 u8 aptx[0x1];
7985 u8 pptx_mask_n[0x1];
7986 u8 reserved_at_43[0x5];
7987 u8 pfctx[0x8];
7988 u8 reserved_at_50[0x10];
7989
7990 u8 pprx[0x1];
7991 u8 aprx[0x1];
7992 u8 pprx_mask_n[0x1];
7993 u8 reserved_at_63[0x5];
7994 u8 pfcrx[0x8];
7995 u8 reserved_at_70[0x10];
7996
7997 u8 device_stall_minor_watermark[0x10];
7998 u8 device_stall_critical_watermark[0x10];
7999
8000 u8 reserved_at_a0[0x60];
8001};
8002
8003struct mlx5_ifc_pelc_reg_bits {
8004 u8 op[0x4];
8005 u8 reserved_at_4[0x4];
8006 u8 local_port[0x8];
8007 u8 reserved_at_10[0x10];
8008
8009 u8 op_admin[0x8];
8010 u8 op_capability[0x8];
8011 u8 op_request[0x8];
8012 u8 op_active[0x8];
8013
8014 u8 admin[0x40];
8015
8016 u8 capability[0x40];
8017
8018 u8 request[0x40];
8019
8020 u8 active[0x40];
8021
8022 u8 reserved_at_140[0x80];
8023};
8024
8025struct mlx5_ifc_peir_reg_bits {
8026 u8 reserved_at_0[0x8];
8027 u8 local_port[0x8];
8028 u8 reserved_at_10[0x10];
8029
8030 u8 reserved_at_20[0xc];
8031 u8 error_count[0x4];
8032 u8 reserved_at_30[0x10];
8033
8034 u8 reserved_at_40[0xc];
8035 u8 lane[0x4];
8036 u8 reserved_at_50[0x8];
8037 u8 error_type[0x8];
8038};
8039
8040struct mlx5_ifc_pcam_enhanced_features_bits {
8041 u8 reserved_at_0[0x76];
8042
8043 u8 pfcc_mask[0x1];
8044 u8 reserved_at_77[0x4];
8045 u8 rx_buffer_fullness_counters[0x1];
8046 u8 ptys_connector_type[0x1];
8047 u8 reserved_at_7d[0x1];
8048 u8 ppcnt_discard_group[0x1];
8049 u8 ppcnt_statistical_group[0x1];
8050};
8051
8052struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8053 u8 port_access_reg_cap_mask_127_to_96[0x20];
8054 u8 port_access_reg_cap_mask_95_to_64[0x20];
8055 u8 port_access_reg_cap_mask_63_to_32[0x20];
8056
8057 u8 port_access_reg_cap_mask_31_to_13[0x13];
8058 u8 pbmc[0x1];
8059 u8 pptb[0x1];
8060 u8 port_access_reg_cap_mask_10_to_0[0xb];
8061};
8062
8063struct mlx5_ifc_pcam_reg_bits {
8064 u8 reserved_at_0[0x8];
8065 u8 feature_group[0x8];
8066 u8 reserved_at_10[0x8];
8067 u8 access_reg_group[0x8];
8068
8069 u8 reserved_at_20[0x20];
8070
8071 union {
8072 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8073 u8 reserved_at_0[0x80];
8074 } port_access_reg_cap_mask;
8075
8076 u8 reserved_at_c0[0x80];
8077
8078 union {
8079 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8080 u8 reserved_at_0[0x80];
8081 } feature_cap_mask;
8082
8083 u8 reserved_at_1c0[0xc0];
8084};
8085
8086struct mlx5_ifc_mcam_enhanced_features_bits {
8087 u8 reserved_at_0[0x7b];
8088 u8 pcie_outbound_stalled[0x1];
8089 u8 tx_overflow_buffer_pkt[0x1];
8090 u8 mtpps_enh_out_per_adj[0x1];
8091 u8 mtpps_fs[0x1];
8092 u8 pcie_performance_group[0x1];
8093};
8094
8095struct mlx5_ifc_mcam_access_reg_bits {
8096 u8 reserved_at_0[0x1c];
8097 u8 mcda[0x1];
8098 u8 mcc[0x1];
8099 u8 mcqi[0x1];
8100 u8 reserved_at_1f[0x1];
8101
8102 u8 regs_95_to_64[0x20];
8103 u8 regs_63_to_32[0x20];
8104 u8 regs_31_to_0[0x20];
8105};
8106
8107struct mlx5_ifc_mcam_reg_bits {
8108 u8 reserved_at_0[0x8];
8109 u8 feature_group[0x8];
8110 u8 reserved_at_10[0x8];
8111 u8 access_reg_group[0x8];
8112
8113 u8 reserved_at_20[0x20];
8114
8115 union {
8116 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8117 u8 reserved_at_0[0x80];
8118 } mng_access_reg_cap_mask;
8119
8120 u8 reserved_at_c0[0x80];
8121
8122 union {
8123 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8124 u8 reserved_at_0[0x80];
8125 } mng_feature_cap_mask;
8126
8127 u8 reserved_at_1c0[0x80];
8128};
8129
8130struct mlx5_ifc_qcam_access_reg_cap_mask {
8131 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8132 u8 qpdpm[0x1];
8133 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8134 u8 qdpm[0x1];
8135 u8 qpts[0x1];
8136 u8 qcap[0x1];
8137 u8 qcam_access_reg_cap_mask_0[0x1];
8138};
8139
8140struct mlx5_ifc_qcam_qos_feature_cap_mask {
8141 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8142 u8 qpts_trust_both[0x1];
8143};
8144
8145struct mlx5_ifc_qcam_reg_bits {
8146 u8 reserved_at_0[0x8];
8147 u8 feature_group[0x8];
8148 u8 reserved_at_10[0x8];
8149 u8 access_reg_group[0x8];
8150 u8 reserved_at_20[0x20];
8151
8152 union {
8153 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8154 u8 reserved_at_0[0x80];
8155 } qos_access_reg_cap_mask;
8156
8157 u8 reserved_at_c0[0x80];
8158
8159 union {
8160 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8161 u8 reserved_at_0[0x80];
8162 } qos_feature_cap_mask;
8163
8164 u8 reserved_at_1c0[0x80];
8165};
8166
8167struct mlx5_ifc_pcap_reg_bits {
8168 u8 reserved_at_0[0x8];
8169 u8 local_port[0x8];
8170 u8 reserved_at_10[0x10];
8171
8172 u8 port_capability_mask[4][0x20];
8173};
8174
8175struct mlx5_ifc_paos_reg_bits {
8176 u8 swid[0x8];
8177 u8 local_port[0x8];
8178 u8 reserved_at_10[0x4];
8179 u8 admin_status[0x4];
8180 u8 reserved_at_18[0x4];
8181 u8 oper_status[0x4];
8182
8183 u8 ase[0x1];
8184 u8 ee[0x1];
8185 u8 reserved_at_22[0x1c];
8186 u8 e[0x2];
8187
8188 u8 reserved_at_40[0x40];
8189};
8190
8191struct mlx5_ifc_pamp_reg_bits {
8192 u8 reserved_at_0[0x8];
8193 u8 opamp_group[0x8];
8194 u8 reserved_at_10[0xc];
8195 u8 opamp_group_type[0x4];
8196
8197 u8 start_index[0x10];
8198 u8 reserved_at_30[0x4];
8199 u8 num_of_indices[0xc];
8200
8201 u8 index_data[18][0x10];
8202};
8203
8204struct mlx5_ifc_pcmr_reg_bits {
8205 u8 reserved_at_0[0x8];
8206 u8 local_port[0x8];
8207 u8 reserved_at_10[0x2e];
8208 u8 fcs_cap[0x1];
8209 u8 reserved_at_3f[0x1f];
8210 u8 fcs_chk[0x1];
8211 u8 reserved_at_5f[0x1];
8212};
8213
8214struct mlx5_ifc_lane_2_module_mapping_bits {
8215 u8 reserved_at_0[0x6];
8216 u8 rx_lane[0x2];
8217 u8 reserved_at_8[0x6];
8218 u8 tx_lane[0x2];
8219 u8 reserved_at_10[0x8];
8220 u8 module[0x8];
8221};
8222
8223struct mlx5_ifc_bufferx_reg_bits {
8224 u8 reserved_at_0[0x6];
8225 u8 lossy[0x1];
8226 u8 epsb[0x1];
8227 u8 reserved_at_8[0xc];
8228 u8 size[0xc];
8229
8230 u8 xoff_threshold[0x10];
8231 u8 xon_threshold[0x10];
8232};
8233
8234struct mlx5_ifc_set_node_in_bits {
8235 u8 node_description[64][0x8];
8236};
8237
8238struct mlx5_ifc_register_power_settings_bits {
8239 u8 reserved_at_0[0x18];
8240 u8 power_settings_level[0x8];
8241
8242 u8 reserved_at_20[0x60];
8243};
8244
8245struct mlx5_ifc_register_host_endianness_bits {
8246 u8 he[0x1];
8247 u8 reserved_at_1[0x1f];
8248
8249 u8 reserved_at_20[0x60];
8250};
8251
8252struct mlx5_ifc_umr_pointer_desc_argument_bits {
8253 u8 reserved_at_0[0x20];
8254
8255 u8 mkey[0x20];
8256
8257 u8 addressh_63_32[0x20];
8258
8259 u8 addressl_31_0[0x20];
8260};
8261
8262struct mlx5_ifc_ud_adrs_vector_bits {
8263 u8 dc_key[0x40];
8264
8265 u8 ext[0x1];
8266 u8 reserved_at_41[0x7];
8267 u8 destination_qp_dct[0x18];
8268
8269 u8 static_rate[0x4];
8270 u8 sl_eth_prio[0x4];
8271 u8 fl[0x1];
8272 u8 mlid[0x7];
8273 u8 rlid_udp_sport[0x10];
8274
8275 u8 reserved_at_80[0x20];
8276
8277 u8 rmac_47_16[0x20];
8278
8279 u8 rmac_15_0[0x10];
8280 u8 tclass[0x8];
8281 u8 hop_limit[0x8];
8282
8283 u8 reserved_at_e0[0x1];
8284 u8 grh[0x1];
8285 u8 reserved_at_e2[0x2];
8286 u8 src_addr_index[0x8];
8287 u8 flow_label[0x14];
8288
8289 u8 rgid_rip[16][0x8];
8290};
8291
8292struct mlx5_ifc_pages_req_event_bits {
8293 u8 reserved_at_0[0x10];
8294 u8 function_id[0x10];
8295
8296 u8 num_pages[0x20];
8297
8298 u8 reserved_at_40[0xa0];
8299};
8300
8301struct mlx5_ifc_eqe_bits {
8302 u8 reserved_at_0[0x8];
8303 u8 event_type[0x8];
8304 u8 reserved_at_10[0x8];
8305 u8 event_sub_type[0x8];
8306
8307 u8 reserved_at_20[0xe0];
8308
8309 union mlx5_ifc_event_auto_bits event_data;
8310
8311 u8 reserved_at_1e0[0x10];
8312 u8 signature[0x8];
8313 u8 reserved_at_1f8[0x7];
8314 u8 owner[0x1];
8315};
8316
8317enum {
8318 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8319};
8320
8321struct mlx5_ifc_cmd_queue_entry_bits {
8322 u8 type[0x8];
8323 u8 reserved_at_8[0x18];
8324
8325 u8 input_length[0x20];
8326
8327 u8 input_mailbox_pointer_63_32[0x20];
8328
8329 u8 input_mailbox_pointer_31_9[0x17];
8330 u8 reserved_at_77[0x9];
8331
8332 u8 command_input_inline_data[16][0x8];
8333
8334 u8 command_output_inline_data[16][0x8];
8335
8336 u8 output_mailbox_pointer_63_32[0x20];
8337
8338 u8 output_mailbox_pointer_31_9[0x17];
8339 u8 reserved_at_1b7[0x9];
8340
8341 u8 output_length[0x20];
8342
8343 u8 token[0x8];
8344 u8 signature[0x8];
8345 u8 reserved_at_1f0[0x8];
8346 u8 status[0x7];
8347 u8 ownership[0x1];
8348};
8349
8350struct mlx5_ifc_cmd_out_bits {
8351 u8 status[0x8];
8352 u8 reserved_at_8[0x18];
8353
8354 u8 syndrome[0x20];
8355
8356 u8 command_output[0x20];
8357};
8358
8359struct mlx5_ifc_cmd_in_bits {
8360 u8 opcode[0x10];
8361 u8 reserved_at_10[0x10];
8362
8363 u8 reserved_at_20[0x10];
8364 u8 op_mod[0x10];
8365
8366 u8 command[0][0x20];
8367};
8368
8369struct mlx5_ifc_cmd_if_box_bits {
8370 u8 mailbox_data[512][0x8];
8371
8372 u8 reserved_at_1000[0x180];
8373
8374 u8 next_pointer_63_32[0x20];
8375
8376 u8 next_pointer_31_10[0x16];
8377 u8 reserved_at_11b6[0xa];
8378
8379 u8 block_number[0x20];
8380
8381 u8 reserved_at_11e0[0x8];
8382 u8 token[0x8];
8383 u8 ctrl_signature[0x8];
8384 u8 signature[0x8];
8385};
8386
8387struct mlx5_ifc_mtt_bits {
8388 u8 ptag_63_32[0x20];
8389
8390 u8 ptag_31_8[0x18];
8391 u8 reserved_at_38[0x6];
8392 u8 wr_en[0x1];
8393 u8 rd_en[0x1];
8394};
8395
8396struct mlx5_ifc_query_wol_rol_out_bits {
8397 u8 status[0x8];
8398 u8 reserved_at_8[0x18];
8399
8400 u8 syndrome[0x20];
8401
8402 u8 reserved_at_40[0x10];
8403 u8 rol_mode[0x8];
8404 u8 wol_mode[0x8];
8405
8406 u8 reserved_at_60[0x20];
8407};
8408
8409struct mlx5_ifc_query_wol_rol_in_bits {
8410 u8 opcode[0x10];
8411 u8 reserved_at_10[0x10];
8412
8413 u8 reserved_at_20[0x10];
8414 u8 op_mod[0x10];
8415
8416 u8 reserved_at_40[0x40];
8417};
8418
8419struct mlx5_ifc_set_wol_rol_out_bits {
8420 u8 status[0x8];
8421 u8 reserved_at_8[0x18];
8422
8423 u8 syndrome[0x20];
8424
8425 u8 reserved_at_40[0x40];
8426};
8427
8428struct mlx5_ifc_set_wol_rol_in_bits {
8429 u8 opcode[0x10];
8430 u8 reserved_at_10[0x10];
8431
8432 u8 reserved_at_20[0x10];
8433 u8 op_mod[0x10];
8434
8435 u8 rol_mode_valid[0x1];
8436 u8 wol_mode_valid[0x1];
8437 u8 reserved_at_42[0xe];
8438 u8 rol_mode[0x8];
8439 u8 wol_mode[0x8];
8440
8441 u8 reserved_at_60[0x20];
8442};
8443
8444enum {
8445 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8446 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8447 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8448};
8449
8450enum {
8451 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8452 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8453 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8454};
8455
8456enum {
8457 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8458 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8459 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8460 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8461 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8462 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8463 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8464 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8465 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8466 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8467 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8468};
8469
8470struct mlx5_ifc_initial_seg_bits {
8471 u8 fw_rev_minor[0x10];
8472 u8 fw_rev_major[0x10];
8473
8474 u8 cmd_interface_rev[0x10];
8475 u8 fw_rev_subminor[0x10];
8476
8477 u8 reserved_at_40[0x40];
8478
8479 u8 cmdq_phy_addr_63_32[0x20];
8480
8481 u8 cmdq_phy_addr_31_12[0x14];
8482 u8 reserved_at_b4[0x2];
8483 u8 nic_interface[0x2];
8484 u8 log_cmdq_size[0x4];
8485 u8 log_cmdq_stride[0x4];
8486
8487 u8 command_doorbell_vector[0x20];
8488
8489 u8 reserved_at_e0[0xf00];
8490
8491 u8 initializing[0x1];
8492 u8 reserved_at_fe1[0x4];
8493 u8 nic_interface_supported[0x3];
8494 u8 reserved_at_fe8[0x18];
8495
8496 struct mlx5_ifc_health_buffer_bits health_buffer;
8497
8498 u8 no_dram_nic_offset[0x20];
8499
8500 u8 reserved_at_1220[0x6e40];
8501
8502 u8 reserved_at_8060[0x1f];
8503 u8 clear_int[0x1];
8504
8505 u8 health_syndrome[0x8];
8506 u8 health_counter[0x18];
8507
8508 u8 reserved_at_80a0[0x17fc0];
8509};
8510
8511struct mlx5_ifc_mtpps_reg_bits {
8512 u8 reserved_at_0[0xc];
8513 u8 cap_number_of_pps_pins[0x4];
8514 u8 reserved_at_10[0x4];
8515 u8 cap_max_num_of_pps_in_pins[0x4];
8516 u8 reserved_at_18[0x4];
8517 u8 cap_max_num_of_pps_out_pins[0x4];
8518
8519 u8 reserved_at_20[0x24];
8520 u8 cap_pin_3_mode[0x4];
8521 u8 reserved_at_48[0x4];
8522 u8 cap_pin_2_mode[0x4];
8523 u8 reserved_at_50[0x4];
8524 u8 cap_pin_1_mode[0x4];
8525 u8 reserved_at_58[0x4];
8526 u8 cap_pin_0_mode[0x4];
8527
8528 u8 reserved_at_60[0x4];
8529 u8 cap_pin_7_mode[0x4];
8530 u8 reserved_at_68[0x4];
8531 u8 cap_pin_6_mode[0x4];
8532 u8 reserved_at_70[0x4];
8533 u8 cap_pin_5_mode[0x4];
8534 u8 reserved_at_78[0x4];
8535 u8 cap_pin_4_mode[0x4];
8536
8537 u8 field_select[0x20];
8538 u8 reserved_at_a0[0x60];
8539
8540 u8 enable[0x1];
8541 u8 reserved_at_101[0xb];
8542 u8 pattern[0x4];
8543 u8 reserved_at_110[0x4];
8544 u8 pin_mode[0x4];
8545 u8 pin[0x8];
8546
8547 u8 reserved_at_120[0x20];
8548
8549 u8 time_stamp[0x40];
8550
8551 u8 out_pulse_duration[0x10];
8552 u8 out_periodic_adjustment[0x10];
8553 u8 enhanced_out_periodic_adjustment[0x20];
8554
8555 u8 reserved_at_1c0[0x20];
8556};
8557
8558struct mlx5_ifc_mtppse_reg_bits {
8559 u8 reserved_at_0[0x18];
8560 u8 pin[0x8];
8561 u8 event_arm[0x1];
8562 u8 reserved_at_21[0x1b];
8563 u8 event_generation_mode[0x4];
8564 u8 reserved_at_40[0x40];
8565};
8566
8567struct mlx5_ifc_mcqi_cap_bits {
8568 u8 supported_info_bitmask[0x20];
8569
8570 u8 component_size[0x20];
8571
8572 u8 max_component_size[0x20];
8573
8574 u8 log_mcda_word_size[0x4];
8575 u8 reserved_at_64[0xc];
8576 u8 mcda_max_write_size[0x10];
8577
8578 u8 rd_en[0x1];
8579 u8 reserved_at_81[0x1];
8580 u8 match_chip_id[0x1];
8581 u8 match_psid[0x1];
8582 u8 check_user_timestamp[0x1];
8583 u8 match_base_guid_mac[0x1];
8584 u8 reserved_at_86[0x1a];
8585};
8586
8587struct mlx5_ifc_mcqi_reg_bits {
8588 u8 read_pending_component[0x1];
8589 u8 reserved_at_1[0xf];
8590 u8 component_index[0x10];
8591
8592 u8 reserved_at_20[0x20];
8593
8594 u8 reserved_at_40[0x1b];
8595 u8 info_type[0x5];
8596
8597 u8 info_size[0x20];
8598
8599 u8 offset[0x20];
8600
8601 u8 reserved_at_a0[0x10];
8602 u8 data_size[0x10];
8603
8604 u8 data[0][0x20];
8605};
8606
8607struct mlx5_ifc_mcc_reg_bits {
8608 u8 reserved_at_0[0x4];
8609 u8 time_elapsed_since_last_cmd[0xc];
8610 u8 reserved_at_10[0x8];
8611 u8 instruction[0x8];
8612
8613 u8 reserved_at_20[0x10];
8614 u8 component_index[0x10];
8615
8616 u8 reserved_at_40[0x8];
8617 u8 update_handle[0x18];
8618
8619 u8 handle_owner_type[0x4];
8620 u8 handle_owner_host_id[0x4];
8621 u8 reserved_at_68[0x1];
8622 u8 control_progress[0x7];
8623 u8 error_code[0x8];
8624 u8 reserved_at_78[0x4];
8625 u8 control_state[0x4];
8626
8627 u8 component_size[0x20];
8628
8629 u8 reserved_at_a0[0x60];
8630};
8631
8632struct mlx5_ifc_mcda_reg_bits {
8633 u8 reserved_at_0[0x8];
8634 u8 update_handle[0x18];
8635
8636 u8 offset[0x20];
8637
8638 u8 reserved_at_40[0x10];
8639 u8 size[0x10];
8640
8641 u8 reserved_at_60[0x20];
8642
8643 u8 data[0][0x20];
8644};
8645
8646union mlx5_ifc_ports_control_registers_document_bits {
8647 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8648 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8649 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8650 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8651 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8652 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8653 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8654 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8655 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8656 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8657 struct mlx5_ifc_paos_reg_bits paos_reg;
8658 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8659 struct mlx5_ifc_peir_reg_bits peir_reg;
8660 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8661 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8662 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8663 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8664 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8665 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8666 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8667 struct mlx5_ifc_plib_reg_bits plib_reg;
8668 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8669 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8670 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8671 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8672 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8673 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8674 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8675 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8676 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8677 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8678 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8679 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8680 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8681 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8682 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8683 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8684 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8685 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8686 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8687 struct mlx5_ifc_pude_reg_bits pude_reg;
8688 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8689 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8690 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8691 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8692 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8693 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8694 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8695 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8696 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8697 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8698 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8699 u8 reserved_at_0[0x60e0];
8700};
8701
8702union mlx5_ifc_debug_enhancements_document_bits {
8703 struct mlx5_ifc_health_buffer_bits health_buffer;
8704 u8 reserved_at_0[0x200];
8705};
8706
8707union mlx5_ifc_uplink_pci_interface_document_bits {
8708 struct mlx5_ifc_initial_seg_bits initial_seg;
8709 u8 reserved_at_0[0x20060];
8710};
8711
8712struct mlx5_ifc_set_flow_table_root_out_bits {
8713 u8 status[0x8];
8714 u8 reserved_at_8[0x18];
8715
8716 u8 syndrome[0x20];
8717
8718 u8 reserved_at_40[0x40];
8719};
8720
8721struct mlx5_ifc_set_flow_table_root_in_bits {
8722 u8 opcode[0x10];
8723 u8 reserved_at_10[0x10];
8724
8725 u8 reserved_at_20[0x10];
8726 u8 op_mod[0x10];
8727
8728 u8 other_vport[0x1];
8729 u8 reserved_at_41[0xf];
8730 u8 vport_number[0x10];
8731
8732 u8 reserved_at_60[0x20];
8733
8734 u8 table_type[0x8];
8735 u8 reserved_at_88[0x18];
8736
8737 u8 reserved_at_a0[0x8];
8738 u8 table_id[0x18];
8739
8740 u8 reserved_at_c0[0x8];
8741 u8 underlay_qpn[0x18];
8742 u8 reserved_at_e0[0x120];
8743};
8744
8745enum {
8746 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8747 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8748};
8749
8750struct mlx5_ifc_modify_flow_table_out_bits {
8751 u8 status[0x8];
8752 u8 reserved_at_8[0x18];
8753
8754 u8 syndrome[0x20];
8755
8756 u8 reserved_at_40[0x40];
8757};
8758
8759struct mlx5_ifc_modify_flow_table_in_bits {
8760 u8 opcode[0x10];
8761 u8 reserved_at_10[0x10];
8762
8763 u8 reserved_at_20[0x10];
8764 u8 op_mod[0x10];
8765
8766 u8 other_vport[0x1];
8767 u8 reserved_at_41[0xf];
8768 u8 vport_number[0x10];
8769
8770 u8 reserved_at_60[0x10];
8771 u8 modify_field_select[0x10];
8772
8773 u8 table_type[0x8];
8774 u8 reserved_at_88[0x18];
8775
8776 u8 reserved_at_a0[0x8];
8777 u8 table_id[0x18];
8778
8779 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8780};
8781
8782struct mlx5_ifc_ets_tcn_config_reg_bits {
8783 u8 g[0x1];
8784 u8 b[0x1];
8785 u8 r[0x1];
8786 u8 reserved_at_3[0x9];
8787 u8 group[0x4];
8788 u8 reserved_at_10[0x9];
8789 u8 bw_allocation[0x7];
8790
8791 u8 reserved_at_20[0xc];
8792 u8 max_bw_units[0x4];
8793 u8 reserved_at_30[0x8];
8794 u8 max_bw_value[0x8];
8795};
8796
8797struct mlx5_ifc_ets_global_config_reg_bits {
8798 u8 reserved_at_0[0x2];
8799 u8 r[0x1];
8800 u8 reserved_at_3[0x1d];
8801
8802 u8 reserved_at_20[0xc];
8803 u8 max_bw_units[0x4];
8804 u8 reserved_at_30[0x8];
8805 u8 max_bw_value[0x8];
8806};
8807
8808struct mlx5_ifc_qetc_reg_bits {
8809 u8 reserved_at_0[0x8];
8810 u8 port_number[0x8];
8811 u8 reserved_at_10[0x30];
8812
8813 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8814 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8815};
8816
8817struct mlx5_ifc_qpdpm_dscp_reg_bits {
8818 u8 e[0x1];
8819 u8 reserved_at_01[0x0b];
8820 u8 prio[0x04];
8821};
8822
8823struct mlx5_ifc_qpdpm_reg_bits {
8824 u8 reserved_at_0[0x8];
8825 u8 local_port[0x8];
8826 u8 reserved_at_10[0x10];
8827 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8828};
8829
8830struct mlx5_ifc_qpts_reg_bits {
8831 u8 reserved_at_0[0x8];
8832 u8 local_port[0x8];
8833 u8 reserved_at_10[0x2d];
8834 u8 trust_state[0x3];
8835};
8836
8837struct mlx5_ifc_pptb_reg_bits {
8838 u8 reserved_at_0[0x2];
8839 u8 mm[0x2];
8840 u8 reserved_at_4[0x4];
8841 u8 local_port[0x8];
8842 u8 reserved_at_10[0x6];
8843 u8 cm[0x1];
8844 u8 um[0x1];
8845 u8 pm[0x8];
8846
8847 u8 prio_x_buff[0x20];
8848
8849 u8 pm_msb[0x8];
8850 u8 reserved_at_48[0x10];
8851 u8 ctrl_buff[0x4];
8852 u8 untagged_buff[0x4];
8853};
8854
8855struct mlx5_ifc_pbmc_reg_bits {
8856 u8 reserved_at_0[0x8];
8857 u8 local_port[0x8];
8858 u8 reserved_at_10[0x10];
8859
8860 u8 xoff_timer_value[0x10];
8861 u8 xoff_refresh[0x10];
8862
8863 u8 reserved_at_40[0x9];
8864 u8 fullness_threshold[0x7];
8865 u8 port_buffer_size[0x10];
8866
8867 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8868
8869 u8 reserved_at_2e0[0x40];
8870};
8871
8872struct mlx5_ifc_qtct_reg_bits {
8873 u8 reserved_at_0[0x8];
8874 u8 port_number[0x8];
8875 u8 reserved_at_10[0xd];
8876 u8 prio[0x3];
8877
8878 u8 reserved_at_20[0x1d];
8879 u8 tclass[0x3];
8880};
8881
8882struct mlx5_ifc_mcia_reg_bits {
8883 u8 l[0x1];
8884 u8 reserved_at_1[0x7];
8885 u8 module[0x8];
8886 u8 reserved_at_10[0x8];
8887 u8 status[0x8];
8888
8889 u8 i2c_device_address[0x8];
8890 u8 page_number[0x8];
8891 u8 device_address[0x10];
8892
8893 u8 reserved_at_40[0x10];
8894 u8 size[0x10];
8895
8896 u8 reserved_at_60[0x20];
8897
8898 u8 dword_0[0x20];
8899 u8 dword_1[0x20];
8900 u8 dword_2[0x20];
8901 u8 dword_3[0x20];
8902 u8 dword_4[0x20];
8903 u8 dword_5[0x20];
8904 u8 dword_6[0x20];
8905 u8 dword_7[0x20];
8906 u8 dword_8[0x20];
8907 u8 dword_9[0x20];
8908 u8 dword_10[0x20];
8909 u8 dword_11[0x20];
8910};
8911
8912struct mlx5_ifc_dcbx_param_bits {
8913 u8 dcbx_cee_cap[0x1];
8914 u8 dcbx_ieee_cap[0x1];
8915 u8 dcbx_standby_cap[0x1];
8916 u8 reserved_at_0[0x5];
8917 u8 port_number[0x8];
8918 u8 reserved_at_10[0xa];
8919 u8 max_application_table_size[6];
8920 u8 reserved_at_20[0x15];
8921 u8 version_oper[0x3];
8922 u8 reserved_at_38[5];
8923 u8 version_admin[0x3];
8924 u8 willing_admin[0x1];
8925 u8 reserved_at_41[0x3];
8926 u8 pfc_cap_oper[0x4];
8927 u8 reserved_at_48[0x4];
8928 u8 pfc_cap_admin[0x4];
8929 u8 reserved_at_50[0x4];
8930 u8 num_of_tc_oper[0x4];
8931 u8 reserved_at_58[0x4];
8932 u8 num_of_tc_admin[0x4];
8933 u8 remote_willing[0x1];
8934 u8 reserved_at_61[3];
8935 u8 remote_pfc_cap[4];
8936 u8 reserved_at_68[0x14];
8937 u8 remote_num_of_tc[0x4];
8938 u8 reserved_at_80[0x18];
8939 u8 error[0x8];
8940 u8 reserved_at_a0[0x160];
8941};
8942
8943struct mlx5_ifc_lagc_bits {
8944 u8 reserved_at_0[0x1d];
8945 u8 lag_state[0x3];
8946
8947 u8 reserved_at_20[0x14];
8948 u8 tx_remap_affinity_2[0x4];
8949 u8 reserved_at_38[0x4];
8950 u8 tx_remap_affinity_1[0x4];
8951};
8952
8953struct mlx5_ifc_create_lag_out_bits {
8954 u8 status[0x8];
8955 u8 reserved_at_8[0x18];
8956
8957 u8 syndrome[0x20];
8958
8959 u8 reserved_at_40[0x40];
8960};
8961
8962struct mlx5_ifc_create_lag_in_bits {
8963 u8 opcode[0x10];
8964 u8 reserved_at_10[0x10];
8965
8966 u8 reserved_at_20[0x10];
8967 u8 op_mod[0x10];
8968
8969 struct mlx5_ifc_lagc_bits ctx;
8970};
8971
8972struct mlx5_ifc_modify_lag_out_bits {
8973 u8 status[0x8];
8974 u8 reserved_at_8[0x18];
8975
8976 u8 syndrome[0x20];
8977
8978 u8 reserved_at_40[0x40];
8979};
8980
8981struct mlx5_ifc_modify_lag_in_bits {
8982 u8 opcode[0x10];
8983 u8 reserved_at_10[0x10];
8984
8985 u8 reserved_at_20[0x10];
8986 u8 op_mod[0x10];
8987
8988 u8 reserved_at_40[0x20];
8989 u8 field_select[0x20];
8990
8991 struct mlx5_ifc_lagc_bits ctx;
8992};
8993
8994struct mlx5_ifc_query_lag_out_bits {
8995 u8 status[0x8];
8996 u8 reserved_at_8[0x18];
8997
8998 u8 syndrome[0x20];
8999
9000 u8 reserved_at_40[0x40];
9001
9002 struct mlx5_ifc_lagc_bits ctx;
9003};
9004
9005struct mlx5_ifc_query_lag_in_bits {
9006 u8 opcode[0x10];
9007 u8 reserved_at_10[0x10];
9008
9009 u8 reserved_at_20[0x10];
9010 u8 op_mod[0x10];
9011
9012 u8 reserved_at_40[0x40];
9013};
9014
9015struct mlx5_ifc_destroy_lag_out_bits {
9016 u8 status[0x8];
9017 u8 reserved_at_8[0x18];
9018
9019 u8 syndrome[0x20];
9020
9021 u8 reserved_at_40[0x40];
9022};
9023
9024struct mlx5_ifc_destroy_lag_in_bits {
9025 u8 opcode[0x10];
9026 u8 reserved_at_10[0x10];
9027
9028 u8 reserved_at_20[0x10];
9029 u8 op_mod[0x10];
9030
9031 u8 reserved_at_40[0x40];
9032};
9033
9034struct mlx5_ifc_create_vport_lag_out_bits {
9035 u8 status[0x8];
9036 u8 reserved_at_8[0x18];
9037
9038 u8 syndrome[0x20];
9039
9040 u8 reserved_at_40[0x40];
9041};
9042
9043struct mlx5_ifc_create_vport_lag_in_bits {
9044 u8 opcode[0x10];
9045 u8 reserved_at_10[0x10];
9046
9047 u8 reserved_at_20[0x10];
9048 u8 op_mod[0x10];
9049
9050 u8 reserved_at_40[0x40];
9051};
9052
9053struct mlx5_ifc_destroy_vport_lag_out_bits {
9054 u8 status[0x8];
9055 u8 reserved_at_8[0x18];
9056
9057 u8 syndrome[0x20];
9058
9059 u8 reserved_at_40[0x40];
9060};
9061
9062struct mlx5_ifc_destroy_vport_lag_in_bits {
9063 u8 opcode[0x10];
9064 u8 reserved_at_10[0x10];
9065
9066 u8 reserved_at_20[0x10];
9067 u8 op_mod[0x10];
9068
9069 u8 reserved_at_40[0x40];
9070};
9071
9072struct mlx5_ifc_alloc_memic_in_bits {
9073 u8 opcode[0x10];
9074 u8 reserved_at_10[0x10];
9075
9076 u8 reserved_at_20[0x10];
9077 u8 op_mod[0x10];
9078
9079 u8 reserved_at_30[0x20];
9080
9081 u8 reserved_at_40[0x18];
9082 u8 log_memic_addr_alignment[0x8];
9083
9084 u8 range_start_addr[0x40];
9085
9086 u8 range_size[0x20];
9087
9088 u8 memic_size[0x20];
9089};
9090
9091struct mlx5_ifc_alloc_memic_out_bits {
9092 u8 status[0x8];
9093 u8 reserved_at_8[0x18];
9094
9095 u8 syndrome[0x20];
9096
9097 u8 memic_start_addr[0x40];
9098};
9099
9100struct mlx5_ifc_dealloc_memic_in_bits {
9101 u8 opcode[0x10];
9102 u8 reserved_at_10[0x10];
9103
9104 u8 reserved_at_20[0x10];
9105 u8 op_mod[0x10];
9106
9107 u8 reserved_at_40[0x40];
9108
9109 u8 memic_start_addr[0x40];
9110
9111 u8 memic_size[0x20];
9112
9113 u8 reserved_at_e0[0x20];
9114};
9115
9116struct mlx5_ifc_dealloc_memic_out_bits {
9117 u8 status[0x8];
9118 u8 reserved_at_8[0x18];
9119
9120 u8 syndrome[0x20];
9121
9122 u8 reserved_at_40[0x40];
9123};
9124
9125#endif
9126
