LXR linux/include/linux/mmc/sh

   1/*
   2 * include/linux/mmc/sh_mmcif.h
   3 *
   4 * platform data for eMMC driver
   5 *
   6 * Copyright (C) 2010 Renesas Solutions Corp.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License.
  11 *
  12 */
  13
  14#ifndef LINUX_MMC_SH_MMCIF_H
  15#define LINUX_MMC_SH_MMCIF_H
  16
  17#include <linux/io.h>
  18#include <linux/platform_device.h>
  19
  20/*
  21 * MMCIF : CE_CLK_CTRL [19:16]
  22 * 1000 : Peripheral clock / 512
  23 * 0111 : Peripheral clock / 256
  24 * 0110 : Peripheral clock / 128
  25 * 0101 : Peripheral clock / 64
  26 * 0100 : Peripheral clock / 32
  27 * 0011 : Peripheral clock / 16
  28 * 0010 : Peripheral clock / 8
  29 * 0001 : Peripheral clock / 4
  30 * 0000 : Peripheral clock / 2
  31 * 1111 : Peripheral clock (sup_pclk set '1')
  32 */
  33
  34struct sh_mmcif_plat_data {
  35        unsigned int            slave_id_tx;    /* embedded slave_id_[tr]x */
  36        unsigned int            slave_id_rx;
  37        u8                      sup_pclk;       /* 1 :SH7757, 0: SH7724/SH7372 */
  38        unsigned long           caps;
  39        u32                     ocr;
  40};
  41
  42#define MMCIF_CE_CMD_SET        0x00000000
  43#define MMCIF_CE_ARG            0x00000008
  44#define MMCIF_CE_ARG_CMD12      0x0000000C
  45#define MMCIF_CE_CMD_CTRL       0x00000010
  46#define MMCIF_CE_BLOCK_SET      0x00000014
  47#define MMCIF_CE_CLK_CTRL       0x00000018
  48#define MMCIF_CE_BUF_ACC        0x0000001C
  49#define MMCIF_CE_RESP3          0x00000020
  50#define MMCIF_CE_RESP2          0x00000024
  51#define MMCIF_CE_RESP1          0x00000028
  52#define MMCIF_CE_RESP0          0x0000002C
  53#define MMCIF_CE_RESP_CMD12     0x00000030
  54#define MMCIF_CE_DATA           0x00000034
  55#define MMCIF_CE_INT            0x00000040
  56#define MMCIF_CE_INT_MASK       0x00000044
  57#define MMCIF_CE_HOST_STS1      0x00000048
  58#define MMCIF_CE_HOST_STS2      0x0000004C
  59#define MMCIF_CE_CLK_CTRL2      0x00000070
  60#define MMCIF_CE_VERSION        0x0000007C
  61
  62/* CE_BUF_ACC */
  63#define BUF_ACC_DMAWEN          (1 << 25)
  64#define BUF_ACC_DMAREN          (1 << 24)
  65#define BUF_ACC_BUSW_32         (0 << 17)
  66#define BUF_ACC_BUSW_16         (1 << 17)
  67#define BUF_ACC_ATYP            (1 << 16)
  68
  69/* CE_CLK_CTRL */
  70#define CLK_ENABLE              (1 << 24) /* 1: output mmc clock */
  71#define CLK_CLEAR               (0xf << 16)
  72#define CLK_SUP_PCLK            (0xf << 16)
  73#define CLKDIV_4                (1 << 16) /* mmc clock frequency.
  74                                           * n: bus clock/(2^(n+1)) */
  75#define CLKDIV_256              (7 << 16) /* mmc clock frequency. (see above) */
  76#define SRSPTO_256              (2 << 12) /* resp timeout */
  77#define SRBSYTO_29              (0xf << 8) /* resp busy timeout */
  78#define SRWDTO_29               (0xf << 4) /* read/write timeout */
  79#define SCCSTO_29               (0xf << 0) /* ccs timeout */
  80
  81/* CE_VERSION */
  82#define SOFT_RST_ON             (1 << 31)
  83#define SOFT_RST_OFF            0
  84
  85static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
  86{
  87        return __raw_readl(addr + reg);
  88}
  89
  90static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
  91{
  92        __raw_writel(val, addr + reg);
  93}
  94
  95#define SH_MMCIF_BBS 512 /* boot block size */
  96
  97static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
  98                                          unsigned long cmd, unsigned long arg)
  99{
 100        sh_mmcif_writel(base, MMCIF_CE_INT, 0);
 101        sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
 102        sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
 103}
 104
 105static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
 106{
 107        unsigned long tmp;
 108        int cnt;
 109
 110        for (cnt = 0; cnt < 1000000; cnt++) {
 111                tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
 112                if (tmp & mask) {
 113                        sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
 114                        return 0;
 115                }
 116        }
 117
 118        return -1;
 119}
 120
 121static inline int sh_mmcif_boot_cmd(void __iomem *base,
 122                                    unsigned long cmd, unsigned long arg)
 123{
 124        sh_mmcif_boot_cmd_send(base, cmd, arg);
 125        return sh_mmcif_boot_cmd_poll(base, 0x00010000);
 126}
 127
 128static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
 129                                               unsigned int block_nr,
 130                                               unsigned long *buf)
 131{
 132        int k;
 133
 134        /* CMD13 - Status */
 135        sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
 136
 137        if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
 138                return -1;
 139
 140        /* CMD17 - Read */
 141        sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
 142        if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
 143                return -1;
 144
 145        for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
 146                buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
 147
 148        return 0;
 149}
 150
 151static inline int sh_mmcif_boot_do_read(void __iomem *base,
 152                                        unsigned long first_block,
 153                                        unsigned long nr_blocks,
 154                                        void *buf)
 155{
 156        unsigned long k;
 157        int ret = 0;
 158
 159        /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
 160        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
 161                        CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
 162                        SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 163
 164        /* CMD9 - Get CSD */
 165        sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
 166
 167        /* CMD7 - Select the card */
 168        sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
 169
 170        /* CMD16 - Set the block size */
 171        sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
 172
 173        for (k = 0; !ret && k < nr_blocks; k++)
 174                ret = sh_mmcif_boot_do_read_single(base, first_block + k,
 175                                                   buf + (k * SH_MMCIF_BBS));
 176
 177        return ret;
 178}
 179
 180static inline void sh_mmcif_boot_init(void __iomem *base)
 181{
 182        /* reset */
 183        sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
 184        sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
 185
 186        /* byte swap */
 187        sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 188
 189        /* Set block size in MMCIF hardware */
 190        sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
 191
 192        /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
 193        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
 194                        CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
 195                        SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 196
 197        /* CMD0 */
 198        sh_mmcif_boot_cmd(base, 0x00000040, 0);
 199
 200        /* CMD1 - Get OCR */
 201        do {
 202                sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
 203        } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
 204                 != 0x80000000);
 205
 206        /* CMD2 - Get CID */
 207        sh_mmcif_boot_cmd(base, 0x02806040, 0);
 208
 209        /* CMD3 - Set card relative address */
 210        sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
 211}
 212
 213#endif /* LINUX_MMC_SH_MMCIF_H */
 214