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16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/sysdev.h>
19#include <linux/interrupt.h>
20#include <linux/sched.h>
21#include <linux/bitops.h>
22#include <linux/fb.h>
23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26
27#include <asm/types.h>
28#include <asm/setup.h>
29#include <asm/memory.h>
30#include <asm/mach-types.h>
31#include <asm/hardware.h>
32#include <asm/irq.h>
33#include <asm/sizes.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/flash.h>
39
40#include <asm/arch/pxa-regs.h>
41#include <asm/arch/mainstone.h>
42#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h>
44#include <asm/arch/mmc.h>
45#include <asm/arch/irda.h>
46#include <asm/arch/ohci.h>
47
48#include "generic.h"
49#include "devices.h"
50
51
52static unsigned long mainstone_irq_enabled;
53
54static void mainstone_mask_irq(unsigned int irq)
55{
56 int mainstone_irq = (irq - MAINSTONE_IRQ(0));
57 MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
58}
59
60static void mainstone_unmask_irq(unsigned int irq)
61{
62 int mainstone_irq = (irq - MAINSTONE_IRQ(0));
63
64 MST_INTSETCLR &= ~(1 << mainstone_irq);
65 MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
66}
67
68static struct irq_chip mainstone_irq_chip = {
69 .name = "FPGA",
70 .ack = mainstone_mask_irq,
71 .mask = mainstone_mask_irq,
72 .unmask = mainstone_unmask_irq,
73};
74
75static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
76{
77 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
78 do {
79 GEDR(0) = GPIO_bit(0);
80 if (likely(pending)) {
81 irq = MAINSTONE_IRQ(0) + __ffs(pending);
82 desc = irq_desc + irq;
83 desc_handle_irq(irq, desc);
84 }
85 pending = MST_INTSETCLR & mainstone_irq_enabled;
86 } while (pending);
87}
88
89static void __init mainstone_init_irq(void)
90{
91 int irq;
92
93 pxa27x_init_irq();
94
95
96 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
97 set_irq_chip(irq, &mainstone_irq_chip);
98 set_irq_handler(irq, handle_level_irq);
99 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
101 else
102 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
103 }
104 set_irq_flags(MAINSTONE_IRQ(8), 0);
105 set_irq_flags(MAINSTONE_IRQ(12), 0);
106
107 MST_INTMSKENA = 0;
108 MST_INTSETCLR = 0;
109
110 set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
111 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
112}
113
114#ifdef CONFIG_PM
115
116static int mainstone_irq_resume(struct sys_device *dev)
117{
118 MST_INTMSKENA = mainstone_irq_enabled;
119 return 0;
120}
121
122static struct sysdev_class mainstone_irq_sysclass = {
123 set_kset_name("cpld_irq"),
124 .resume = mainstone_irq_resume,
125};
126
127static struct sys_device mainstone_irq_device = {
128 .cls = &mainstone_irq_sysclass,
129};
130
131static int __init mainstone_irq_device_init(void)
132{
133 int ret = sysdev_class_register(&mainstone_irq_sysclass);
134 if (ret == 0)
135 ret = sysdev_register(&mainstone_irq_device);
136 return ret;
137}
138
139device_initcall(mainstone_irq_device_init);
140
141#endif
142
143
144static struct resource smc91x_resources[] = {
145 [0] = {
146 .start = (MST_ETH_PHYS + 0x300),
147 .end = (MST_ETH_PHYS + 0xfffff),
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = MAINSTONE_IRQ(3),
152 .end = MAINSTONE_IRQ(3),
153 .flags = IORESOURCE_IRQ,
154 }
155};
156
157static struct platform_device smc91x_device = {
158 .name = "smc91x",
159 .id = 0,
160 .num_resources = ARRAY_SIZE(smc91x_resources),
161 .resource = smc91x_resources,
162};
163
164static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
165{
166 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
167 MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
168 return 0;
169}
170
171static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
172{
173 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
174 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
175}
176
177static long mst_audio_suspend_mask;
178
179static void mst_audio_suspend(void *priv)
180{
181 mst_audio_suspend_mask = MST_MSCWR2;
182 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
183}
184
185static void mst_audio_resume(void *priv)
186{
187 MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
188}
189
190static pxa2xx_audio_ops_t mst_audio_ops = {
191 .startup = mst_audio_startup,
192 .shutdown = mst_audio_shutdown,
193 .suspend = mst_audio_suspend,
194 .resume = mst_audio_resume,
195};
196
197static struct platform_device mst_audio_device = {
198 .name = "pxa2xx-ac97",
199 .id = -1,
200 .dev = { .platform_data = &mst_audio_ops },
201};
202
203static struct resource flash_resources[] = {
204 [0] = {
205 .start = PXA_CS0_PHYS,
206 .end = PXA_CS0_PHYS + SZ_64M - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = PXA_CS1_PHYS,
211 .end = PXA_CS1_PHYS + SZ_64M - 1,
212 .flags = IORESOURCE_MEM,
213 },
214};
215
216static struct mtd_partition mainstoneflash0_partitions[] = {
217 {
218 .name = "Bootloader",
219 .size = 0x00040000,
220 .offset = 0,
221 .mask_flags = MTD_WRITEABLE
222 },{
223 .name = "Kernel",
224 .size = 0x00400000,
225 .offset = 0x00040000,
226 },{
227 .name = "Filesystem",
228 .size = MTDPART_SIZ_FULL,
229 .offset = 0x00440000
230 }
231};
232
233static struct flash_platform_data mst_flash_data[2] = {
234 {
235 .map_name = "cfi_probe",
236 .parts = mainstoneflash0_partitions,
237 .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
238 }, {
239 .map_name = "cfi_probe",
240 .parts = NULL,
241 .nr_parts = 0,
242 }
243};
244
245static struct platform_device mst_flash_device[2] = {
246 {
247 .name = "pxa2xx-flash",
248 .id = 0,
249 .dev = {
250 .platform_data = &mst_flash_data[0],
251 },
252 .resource = &flash_resources[0],
253 .num_resources = 1,
254 },
255 {
256 .name = "pxa2xx-flash",
257 .id = 1,
258 .dev = {
259 .platform_data = &mst_flash_data[1],
260 },
261 .resource = &flash_resources[1],
262 .num_resources = 1,
263 },
264};
265
266static void mainstone_backlight_power(int on)
267{
268 if (on) {
269 pxa_gpio_mode(GPIO16_PWM0_MD);
270 pxa_set_cken(CKEN_PWM0, 1);
271 PWM_CTRL0 = 0;
272 PWM_PWDUTY0 = 0x3ff;
273 PWM_PERVAL0 = 0x3ff;
274 } else {
275 PWM_CTRL0 = 0;
276 PWM_PWDUTY0 = 0x0;
277 PWM_PERVAL0 = 0x3FF;
278 pxa_set_cken(CKEN_PWM0, 0);
279 }
280}
281
282static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
283 .pixclock = 50000,
284 .xres = 640,
285 .yres = 480,
286 .bpp = 16,
287 .hsync_len = 1,
288 .left_margin = 0x9f,
289 .right_margin = 1,
290 .vsync_len = 44,
291 .upper_margin = 0,
292 .lower_margin = 0,
293 .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
294};
295
296static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
297 .pixclock = 110000,
298 .xres = 240,
299 .yres = 320,
300 .bpp = 16,
301 .hsync_len = 4,
302 .left_margin = 8,
303 .right_margin = 20,
304 .vsync_len = 3,
305 .upper_margin = 1,
306 .lower_margin = 10,
307 .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
308};
309
310static struct pxafb_mach_info mainstone_pxafb_info = {
311 .num_modes = 1,
312 .lccr0 = LCCR0_Act,
313 .lccr3 = LCCR3_PCP,
314 .pxafb_backlight_power = mainstone_backlight_power,
315};
316
317static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
318{
319 int err;
320
321
322
323
324 pxa_gpio_mode(GPIO32_MMCCLK_MD);
325 pxa_gpio_mode(GPIO112_MMCCMD_MD);
326 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
327 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
328 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
329 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
330
331
332
333
334 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
335
336 err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
337 "MMC card detect", data);
338 if (err) {
339 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
340 return -1;
341 }
342
343 return 0;
344}
345
346static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
347{
348 struct pxamci_platform_data* p_d = dev->platform_data;
349
350 if (( 1 << vdd) & p_d->ocr_mask) {
351 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
352 MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
353 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
354 } else {
355 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
356 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
357 }
358}
359
360static void mainstone_mci_exit(struct device *dev, void *data)
361{
362 free_irq(MAINSTONE_MMC_IRQ, data);
363}
364
365static struct pxamci_platform_data mainstone_mci_platform_data = {
366 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
367 .init = mainstone_mci_init,
368 .setpower = mainstone_mci_setpower,
369 .exit = mainstone_mci_exit,
370};
371
372static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
373{
374 unsigned long flags;
375
376 local_irq_save(flags);
377 if (mode & IR_SIRMODE) {
378 MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
379 } else if (mode & IR_FIRMODE) {
380 MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
381 }
382 if (mode & IR_OFF) {
383 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
384 } else {
385 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
386 }
387 local_irq_restore(flags);
388}
389
390static struct pxaficp_platform_data mainstone_ficp_platform_data = {
391 .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
392 .transceiver_mode = mainstone_irda_transceiver_mode,
393};
394
395static struct platform_device *platform_devices[] __initdata = {
396 &smc91x_device,
397 &mst_audio_device,
398 &mst_flash_device[0],
399 &mst_flash_device[1],
400};
401
402static int mainstone_ohci_init(struct device *dev)
403{
404
405 pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);
406 pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT);
407
408
409
410 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
411 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
412
413 return 0;
414}
415
416static struct pxaohci_platform_data mainstone_ohci_platform_data = {
417 .port_mode = PMM_PERPORT_MODE,
418 .init = mainstone_ohci_init,
419};
420
421static void __init mainstone_init(void)
422{
423 int SW7 = 0;
424
425 mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
426 mst_flash_data[1].width = 4;
427
428
429 mst_flash_data[SW7].name = "processor-flash";
430 mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
431
432 printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
433 mst_flash_data[0].name);
434
435
436
437
438
439 ARB_CNTRL = ARB_CORE_PARK | 0x234;
440
441
442
443
444
445 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
446
447 GPSR(GPIO48_nPOE) =
448 GPIO_bit(GPIO48_nPOE) |
449 GPIO_bit(GPIO49_nPWE) |
450 GPIO_bit(GPIO50_nPIOR) |
451 GPIO_bit(GPIO51_nPIOW) |
452 GPIO_bit(GPIO85_nPCE_1) |
453 GPIO_bit(GPIO54_nPCE_2);
454
455 pxa_gpio_mode(GPIO48_nPOE_MD);
456 pxa_gpio_mode(GPIO49_nPWE_MD);
457 pxa_gpio_mode(GPIO50_nPIOR_MD);
458 pxa_gpio_mode(GPIO51_nPIOW_MD);
459 pxa_gpio_mode(GPIO85_nPCE_1_MD);
460 pxa_gpio_mode(GPIO54_nPCE_2_MD);
461 pxa_gpio_mode(GPIO79_pSKTSEL_MD);
462 pxa_gpio_mode(GPIO55_nPREG_MD);
463 pxa_gpio_mode(GPIO56_nPWAIT_MD);
464 pxa_gpio_mode(GPIO57_nIOIS16_MD);
465
466 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
467
468
469
470 if (0)
471 mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
472 else
473 mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
474
475 set_pxa_fb_info(&mainstone_pxafb_info);
476
477 pxa_set_mci_info(&mainstone_mci_platform_data);
478 pxa_set_ficp_info(&mainstone_ficp_platform_data);
479 pxa_set_ohci_info(&mainstone_ohci_platform_data);
480}
481
482
483static struct map_desc mainstone_io_desc[] __initdata = {
484 {
485 .virtual = MST_FPGA_VIRT,
486 .pfn = __phys_to_pfn(MST_FPGA_PHYS),
487 .length = 0x00100000,
488 .type = MT_DEVICE
489 }
490};
491
492static void __init mainstone_map_io(void)
493{
494 pxa_map_io();
495 iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
496
497
498 PGSR0 = 0x00008800;
499 PGSR1 = 0x00000002;
500 PGSR2 = 0x0001FC00;
501 PGSR3 = 0x00001F81;
502 PWER = 0xC0000002;
503 PRER = 0x00000002;
504 PFER = 0x00000002;
505
506 PSLR |= 0xF04;
507 PCFR = 0x66;
508
509 KPC &=~KPC_ASACT;
510 KPC |=KPC_AS;
511 PKWR = 0x000FD000;
512
513 PKWR;
514}
515
516MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
517
518 .phys_io = 0x40000000,
519 .boot_params = 0xa0000100,
520 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
521 .map_io = mainstone_map_io,
522 .init_irq = mainstone_init_irq,
523 .timer = &pxa_timer,
524 .init_machine = mainstone_init,
525MACHINE_END
526
