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14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/suspend.h>
18#include <linux/platform_device.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/arch/irqs.h>
23#include <asm/arch/pxa-regs.h>
24#include <asm/arch/ohci.h>
25#include <asm/arch/pm.h>
26#include <asm/arch/dma.h>
27
28#include "generic.h"
29#include "devices.h"
30#include "clock.h"
31
32
33#define BASE_CLK 13000000
34
35
36
37
38
39
40unsigned int pxa27x_get_clk_frequency_khz(int info)
41{
42 unsigned long ccsr, clkcfg;
43 unsigned int l, L, m, M, n2, N, S;
44 int cccr_a, t, ht, b;
45
46 ccsr = CCSR;
47 cccr_a = CCCR & (1 << 25);
48
49
50 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
51 t = clkcfg & (1 << 0);
52 ht = clkcfg & (1 << 2);
53 b = clkcfg & (1 << 3);
54
55 l = ccsr & 0x1f;
56 n2 = (ccsr>>7) & 0xf;
57 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
58
59 L = l * BASE_CLK;
60 N = (L * n2) / 2;
61 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
62 S = (b) ? L : (L/2);
63
64 if (info) {
65 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
66 L / 1000000, (L % 1000000) / 10000, l );
67 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
68 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
69 (t) ? "" : "in" );
70 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
71 M / 1000000, (M % 1000000) / 10000, m );
72 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
73 S / 1000000, (S % 1000000) / 10000 );
74 }
75
76 return (t) ? (N/1000) : (L/1000);
77}
78
79
80
81
82
83unsigned int pxa27x_get_memclk_frequency_10khz(void)
84{
85 unsigned long ccsr, clkcfg;
86 unsigned int l, L, m, M;
87 int cccr_a, b;
88
89 ccsr = CCSR;
90 cccr_a = CCCR & (1 << 25);
91
92
93 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
94 b = clkcfg & (1 << 3);
95
96 l = ccsr & 0x1f;
97 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
98
99 L = l * BASE_CLK;
100 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
101
102 return (M / 10000);
103}
104
105
106
107
108static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
109{
110 unsigned long ccsr;
111 unsigned int l, L, k, K;
112
113 ccsr = CCSR;
114
115 l = ccsr & 0x1f;
116 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
117
118 L = l * BASE_CLK;
119 K = L / k;
120
121 return (K / 10000);
122}
123
124static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
125{
126 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
127}
128
129static const struct clkops clk_pxa27x_lcd_ops = {
130 .enable = clk_cken_enable,
131 .disable = clk_cken_disable,
132 .getrate = clk_pxa27x_lcd_getrate,
133};
134
135static struct clk pxa27x_clks[] = {
136 INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
137 INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
138
139 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
140 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
141 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
142
143 INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
144 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
145 INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
146 INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
147 INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
148
149 INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
150 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
151 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
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163
164};
165
166#ifdef CONFIG_PM
167
168#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
169#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
170
171#define RESTORE_GPLEVEL(n) do { \
172 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
173 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
174} while (0)
175
176
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178
179
180
181enum { SLEEP_SAVE_START = 0,
182
183 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
184 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
185 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
186 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
187 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
188
189 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
190 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
191 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
192 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
193
194 SLEEP_SAVE_PSTR,
195
196 SLEEP_SAVE_ICMR,
197 SLEEP_SAVE_CKEN,
198
199 SLEEP_SAVE_MDREFR,
200 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
201 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
202
203 SLEEP_SAVE_SIZE
204};
205
206void pxa27x_cpu_pm_save(unsigned long *sleep_save)
207{
208 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
209 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
210 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
211 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
212 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
213
214 SAVE(GAFR0_L); SAVE(GAFR0_U);
215 SAVE(GAFR1_L); SAVE(GAFR1_U);
216 SAVE(GAFR2_L); SAVE(GAFR2_U);
217 SAVE(GAFR3_L); SAVE(GAFR3_U);
218
219 SAVE(MDREFR);
220 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
221 SAVE(PFER); SAVE(PKWR);
222
223 SAVE(ICMR); ICMR = 0;
224 SAVE(CKEN);
225 SAVE(PSTR);
226
227
228 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
229}
230
231void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
232{
233
234 PSPR = 0;
235
236
237 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
238 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
239 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
240 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
241 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
242 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
243 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
244 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
245 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
246 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
247
248 RESTORE(MDREFR);
249 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
250 RESTORE(PFER); RESTORE(PKWR);
251
252 PSSR = PSSR_RDH | PSSR_PH;
253
254 RESTORE(CKEN);
255
256 ICLR = 0;
257 ICCR = 1;
258 RESTORE(ICMR);
259 RESTORE(PSTR);
260}
261
262void pxa27x_cpu_pm_enter(suspend_state_t state)
263{
264 extern void pxa_cpu_standby(void);
265
266 if (state == PM_SUSPEND_STANDBY)
267 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
268 (1 << CKEN_LCD) | (1 << CKEN_PWM0);
269 else
270 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
271
272
273 PCFR &= ~PCFR_FVC;
274
275
276 PEDR = 0xDF12FE1B;
277
278 switch (state) {
279 case PM_SUSPEND_STANDBY:
280 pxa_cpu_standby();
281 break;
282 case PM_SUSPEND_MEM:
283
284 PSPR = virt_to_phys(pxa_cpu_resume);
285 pxa27x_cpu_suspend(PWRMODE_SLEEP);
286 break;
287 }
288}
289
290static int pxa27x_cpu_pm_valid(suspend_state_t state)
291{
292 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
293}
294
295static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
296 .save_size = SLEEP_SAVE_SIZE,
297 .save = pxa27x_cpu_pm_save,
298 .restore = pxa27x_cpu_pm_restore,
299 .valid = pxa27x_cpu_pm_valid,
300 .enter = pxa27x_cpu_pm_enter,
301};
302
303static void __init pxa27x_init_pm(void)
304{
305 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
306}
307#endif
308
309
310
311
312#define PXA27x_GPIO_NOWAKE_MASK \
313 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
314#define WAKEMASK(gpio) \
315 (((gpio) <= 15) \
316 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
317 : ((gpio == 35) ? (1 << 24) : 0))
318
319static int pxa27x_set_wake(unsigned int irq, unsigned int on)
320{
321 int gpio = IRQ_TO_GPIO(irq);
322 uint32_t mask;
323
324 if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
325 if (WAKEMASK(gpio) == 0)
326 return -EINVAL;
327
328 mask = WAKEMASK(gpio);
329
330 if (on) {
331 if (GRER(gpio) | GPIO_bit(gpio))
332 PRER |= mask;
333 else
334 PRER &= ~mask;
335
336 if (GFER(gpio) | GPIO_bit(gpio))
337 PFER |= mask;
338 else
339 PFER &= ~mask;
340 }
341 goto set_pwer;
342 }
343
344 switch (irq) {
345 case IRQ_RTCAlrm:
346 mask = PWER_RTC;
347 break;
348 case IRQ_USB:
349 mask = 1u << 26;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355set_pwer:
356 if (on)
357 PWER |= mask;
358 else
359 PWER &=~mask;
360
361 return 0;
362}
363
364void __init pxa27x_init_irq(void)
365{
366 pxa_init_irq_low();
367 pxa_init_irq_high();
368 pxa_init_irq_gpio(128);
369 pxa_init_irq_set_wake(pxa27x_set_wake);
370}
371
372
373
374
375
376static u64 pxa27x_dmamask = 0xffffffffUL;
377
378static struct resource pxa27x_ohci_resources[] = {
379 [0] = {
380 .start = 0x4C000000,
381 .end = 0x4C00ff6f,
382 .flags = IORESOURCE_MEM,
383 },
384 [1] = {
385 .start = IRQ_USBH1,
386 .end = IRQ_USBH1,
387 .flags = IORESOURCE_IRQ,
388 },
389};
390
391struct platform_device pxa27x_device_ohci = {
392 .name = "pxa27x-ohci",
393 .id = -1,
394 .dev = {
395 .dma_mask = &pxa27x_dmamask,
396 .coherent_dma_mask = 0xffffffff,
397 },
398 .num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
399 .resource = pxa27x_ohci_resources,
400};
401
402void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
403{
404 pxa27x_device_ohci.dev.platform_data = info;
405}
406
407static struct resource i2c_power_resources[] = {
408 {
409 .start = 0x40f00180,
410 .end = 0x40f001a3,
411 .flags = IORESOURCE_MEM,
412 }, {
413 .start = IRQ_PWRI2C,
414 .end = IRQ_PWRI2C,
415 .flags = IORESOURCE_IRQ,
416 },
417};
418
419struct platform_device pxa27x_device_i2c_power = {
420 .name = "pxa2xx-i2c",
421 .id = 1,
422 .resource = i2c_power_resources,
423 .num_resources = ARRAY_SIZE(i2c_power_resources),
424};
425
426static struct platform_device *devices[] __initdata = {
427 &pxa_device_mci,
428 &pxa_device_udc,
429 &pxa_device_fb,
430 &pxa_device_ffuart,
431 &pxa_device_btuart,
432 &pxa_device_stuart,
433 &pxa_device_i2c,
434 &pxa_device_i2s,
435 &pxa_device_ficp,
436 &pxa_device_rtc,
437 &pxa27x_device_i2c_power,
438 &pxa27x_device_ohci,
439};
440
441static int __init pxa27x_init(void)
442{
443 int ret = 0;
444 if (cpu_is_pxa27x()) {
445 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
446
447 if ((ret = pxa_init_dma(32)))
448 return ret;
449#ifdef CONFIG_PM
450 pxa27x_init_pm();
451#endif
452 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
453 }
454 return ret;
455}
456
457subsys_initcall(pxa27x_init);
458
