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36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67unsigned long irq_flags = 0x1f;
68
69
70atomic_t num_spurious;
71
72struct ivgx {
73
74 unsigned int irqno;
75
76 unsigned int isrflag;
77} ivg_table[NR_PERI_INTS];
78
79struct ivg_slice {
80
81 struct ivgx *ifirst;
82 struct ivgx *istop;
83} ivg7_13[IVG13 - IVG7 + 1];
84
85static void search_IAR(void);
86
87
88
89
90
91static void __init search_IAR(void)
92{
93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
95 int irqn;
96
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
98
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100 int iar_shift = (irqn & 7) * 4;
101 if (ivg ==
102 (0xf &
103#ifndef CONFIG_BF52x
104 bfin_read32((unsigned long *)SIC_IAR0 +
105 (irqn >> 3)) >> iar_shift)) {
106#else
107 bfin_read32((unsigned long *)SIC_IAR0 +
108 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
109#endif
110 ivg_table[irq_pos].irqno = IVG7 + irqn;
111 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
112 ivg7_13[ivg].istop++;
113 irq_pos++;
114 }
115 }
116 }
117}
118
119
120
121
122
123static void ack_noop(unsigned int irq)
124{
125
126}
127
128static void bfin_core_mask_irq(unsigned int irq)
129{
130 irq_flags &= ~(1 << irq);
131 if (!irqs_disabled())
132 local_irq_enable();
133}
134
135static void bfin_core_unmask_irq(unsigned int irq)
136{
137 irq_flags |= 1 << irq;
138
139
140
141
142
143
144
145
146
147 if (!irqs_disabled())
148 local_irq_enable();
149 return;
150}
151
152static void bfin_internal_mask_irq(unsigned int irq)
153{
154#ifdef CONFIG_BF53x
155 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
156 ~(1 << (irq - (IRQ_CORETMR + 1))));
157#else
158 unsigned mask_bank, mask_bit;
159 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
160 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
161 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
162 ~(1 << mask_bit));
163#endif
164 SSYNC();
165}
166
167static void bfin_internal_unmask_irq(unsigned int irq)
168{
169#ifdef CONFIG_BF53x
170 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
171 (1 << (irq - (IRQ_CORETMR + 1))));
172#else
173 unsigned mask_bank, mask_bit;
174 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
175 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
176 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
177 (1 << mask_bit));
178#endif
179 SSYNC();
180}
181
182static struct irq_chip bfin_core_irqchip = {
183 .ack = ack_noop,
184 .mask = bfin_core_mask_irq,
185 .unmask = bfin_core_unmask_irq,
186};
187
188static struct irq_chip bfin_internal_irqchip = {
189 .ack = ack_noop,
190 .mask = bfin_internal_mask_irq,
191 .unmask = bfin_internal_unmask_irq,
192};
193
194#ifdef BF537_GENERIC_ERROR_INT_DEMUX
195static int error_int_mask;
196
197static void bfin_generic_error_ack_irq(unsigned int irq)
198{
199
200}
201
202static void bfin_generic_error_mask_irq(unsigned int irq)
203{
204 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
205
206 if (!error_int_mask) {
207 local_irq_disable();
208 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
209 ~(1 <<
210 (IRQ_GENERIC_ERROR -
211 (IRQ_CORETMR + 1))));
212 SSYNC();
213 local_irq_enable();
214 }
215}
216
217static void bfin_generic_error_unmask_irq(unsigned int irq)
218{
219 local_irq_disable();
220 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
221 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
222 SSYNC();
223 local_irq_enable();
224
225 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
226}
227
228static struct irq_chip bfin_generic_error_irqchip = {
229 .ack = bfin_generic_error_ack_irq,
230 .mask = bfin_generic_error_mask_irq,
231 .unmask = bfin_generic_error_unmask_irq,
232};
233
234static void bfin_demux_error_irq(unsigned int int_err_irq,
235 struct irq_desc *intb_desc)
236{
237 int irq = 0;
238
239 SSYNC();
240
241#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
242 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
243 irq = IRQ_MAC_ERROR;
244 else
245#endif
246 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
247 irq = IRQ_SPORT0_ERROR;
248 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
249 irq = IRQ_SPORT1_ERROR;
250 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
251 irq = IRQ_PPI_ERROR;
252 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
253 irq = IRQ_CAN_ERROR;
254 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
255 irq = IRQ_SPI_ERROR;
256 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
257 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
258 irq = IRQ_UART0_ERROR;
259 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
260 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
261 irq = IRQ_UART1_ERROR;
262
263 if (irq) {
264 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
265 struct irq_desc *desc = irq_desc + irq;
266 desc->handle_irq(irq, desc);
267 } else {
268
269 switch (irq) {
270 case IRQ_PPI_ERROR:
271 bfin_write_PPI_STATUS(PPI_ERR_MASK);
272 break;
273#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
274 case IRQ_MAC_ERROR:
275 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
276 break;
277#endif
278 case IRQ_SPORT0_ERROR:
279 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
280 break;
281
282 case IRQ_SPORT1_ERROR:
283 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
284 break;
285
286 case IRQ_CAN_ERROR:
287 bfin_write_CAN_GIS(CAN_ERR_MASK);
288 break;
289
290 case IRQ_SPI_ERROR:
291 bfin_write_SPI_STAT(SPI_ERR_MASK);
292 break;
293
294 default:
295 break;
296 }
297
298 pr_debug("IRQ %d:"
299 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
300 irq);
301 }
302 } else
303 printk(KERN_ERR
304 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
305 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
306 __FUNCTION__, __FILE__, __LINE__);
307
308}
309#endif
310
311#if !defined(CONFIG_BF54x)
312
313static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
314static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
315
316static void bfin_gpio_ack_irq(unsigned int irq)
317{
318 u16 gpionr = irq - IRQ_PF0;
319
320 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
321 set_gpio_data(gpionr, 0);
322 SSYNC();
323 }
324}
325
326static void bfin_gpio_mask_ack_irq(unsigned int irq)
327{
328 u16 gpionr = irq - IRQ_PF0;
329
330 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
331 set_gpio_data(gpionr, 0);
332 SSYNC();
333 }
334
335 set_gpio_maska(gpionr, 0);
336 SSYNC();
337}
338
339static void bfin_gpio_mask_irq(unsigned int irq)
340{
341 set_gpio_maska(irq - IRQ_PF0, 0);
342 SSYNC();
343}
344
345static void bfin_gpio_unmask_irq(unsigned int irq)
346{
347 set_gpio_maska(irq - IRQ_PF0, 1);
348 SSYNC();
349}
350
351static unsigned int bfin_gpio_irq_startup(unsigned int irq)
352{
353 unsigned int ret;
354 u16 gpionr = irq - IRQ_PF0;
355
356 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
357 ret = gpio_request(gpionr, "IRQ");
358 if (ret)
359 return ret;
360 }
361
362 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
363 bfin_gpio_unmask_irq(irq);
364
365 return ret;
366}
367
368static void bfin_gpio_irq_shutdown(unsigned int irq)
369{
370 bfin_gpio_mask_irq(irq);
371 gpio_free(irq - IRQ_PF0);
372 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
373}
374
375static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
376{
377
378 unsigned int ret;
379 u16 gpionr = irq - IRQ_PF0;
380
381 if (type == IRQ_TYPE_PROBE) {
382
383 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
384 return 0;
385 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
386 }
387
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
389 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
390 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
391 ret = gpio_request(gpionr, "IRQ");
392 if (ret)
393 return ret;
394 }
395
396 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
397 } else {
398 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
399 return 0;
400 }
401
402 set_gpio_dir(gpionr, 0);
403 set_gpio_inen(gpionr, 1);
404
405 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
406 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
407 set_gpio_edge(gpionr, 1);
408 } else {
409 set_gpio_edge(gpionr, 0);
410 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
411 }
412
413 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
414 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
415 set_gpio_both(gpionr, 1);
416 else
417 set_gpio_both(gpionr, 0);
418
419 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
420 set_gpio_polar(gpionr, 1);
421 else
422 set_gpio_polar(gpionr, 0);
423
424 SSYNC();
425
426 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
427 set_irq_handler(irq, handle_edge_irq);
428 else
429 set_irq_handler(irq, handle_level_irq);
430
431 return 0;
432}
433
434static struct irq_chip bfin_gpio_irqchip = {
435 .ack = bfin_gpio_ack_irq,
436 .mask = bfin_gpio_mask_irq,
437 .mask_ack = bfin_gpio_mask_ack_irq,
438 .unmask = bfin_gpio_unmask_irq,
439 .set_type = bfin_gpio_irq_type,
440 .startup = bfin_gpio_irq_startup,
441 .shutdown = bfin_gpio_irq_shutdown
442};
443
444static void bfin_demux_gpio_irq(unsigned int intb_irq,
445 struct irq_desc *intb_desc)
446{
447 u16 i;
448 struct irq_desc *desc;
449
450 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
451 int irq = IRQ_PF0 + i;
452 int flag_d = get_gpiop_data(i);
453 int mask =
454 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
455
456 while (mask) {
457 if (mask & 1) {
458 desc = irq_desc + irq;
459 desc->handle_irq(irq, desc);
460 }
461 irq++;
462 mask >>= 1;
463 }
464 }
465}
466
467#else
468
469#define NR_PINT_SYS_IRQS 4
470#define NR_PINT_BITS 32
471#define NR_PINTS 160
472#define IRQ_NOT_AVAIL 0xFF
473
474#define PINT_2_BANK(x) ((x) >> 5)
475#define PINT_2_BIT(x) ((x) & 0x1F)
476#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
477
478static unsigned char irq2pint_lut[NR_PINTS];
479static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
480
481struct pin_int_t {
482 unsigned int mask_set;
483 unsigned int mask_clear;
484 unsigned int request;
485 unsigned int assign;
486 unsigned int edge_set;
487 unsigned int edge_clear;
488 unsigned int invert_set;
489 unsigned int invert_clear;
490 unsigned int pinstate;
491 unsigned int latch;
492};
493
494static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
495 (struct pin_int_t *)PINT0_MASK_SET,
496 (struct pin_int_t *)PINT1_MASK_SET,
497 (struct pin_int_t *)PINT2_MASK_SET,
498 (struct pin_int_t *)PINT3_MASK_SET,
499};
500
501unsigned short get_irq_base(u8 bank, u8 bmap)
502{
503
504 u16 irq_base;
505
506 if (bank < 2) {
507 irq_base = IRQ_PA0 + bmap * 16;
508 } else {
509 irq_base = IRQ_PC0 + bmap * 16;
510 }
511
512 return irq_base;
513
514}
515
516
517void init_pint_lut(void)
518{
519 u16 bank, bit, irq_base, bit_pos;
520 u32 pint_assign;
521 u8 bmap;
522
523 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
524
525 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
526
527 pint_assign = pint[bank]->assign;
528
529 for (bit = 0; bit < NR_PINT_BITS; bit++) {
530
531 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
532
533 irq_base = get_irq_base(bank, bmap);
534
535 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
536 bit_pos = bit + bank * NR_PINT_BITS;
537
538 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
539 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
540
541 }
542
543 }
544
545}
546
547static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
548
549static void bfin_gpio_ack_irq(unsigned int irq)
550{
551 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
552
553 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
554 SSYNC();
555}
556
557static void bfin_gpio_mask_ack_irq(unsigned int irq)
558{
559 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
560 u32 pintbit = PINT_BIT(pint_val);
561 u8 bank = PINT_2_BANK(pint_val);
562
563 pint[bank]->request = pintbit;
564 pint[bank]->mask_clear = pintbit;
565 SSYNC();
566}
567
568static void bfin_gpio_mask_irq(unsigned int irq)
569{
570 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
571
572 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
573 SSYNC();
574}
575
576static void bfin_gpio_unmask_irq(unsigned int irq)
577{
578 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
579 u32 pintbit = PINT_BIT(pint_val);
580 u8 bank = PINT_2_BANK(pint_val);
581
582 pint[bank]->request = pintbit;
583 pint[bank]->mask_set = pintbit;
584 SSYNC();
585}
586
587static unsigned int bfin_gpio_irq_startup(unsigned int irq)
588{
589 unsigned int ret;
590 u16 gpionr = irq - IRQ_PA0;
591 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
592
593 if (pint_val == IRQ_NOT_AVAIL) {
594 printk(KERN_ERR
595 "GPIO IRQ %d :Not in PINT Assign table "
596 "Reconfigure Interrupt to Port Assignemt\n", irq);
597 return -ENODEV;
598 }
599
600 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
601 ret = gpio_request(gpionr, "IRQ");
602 if (ret)
603 return ret;
604 }
605
606 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
607 bfin_gpio_unmask_irq(irq);
608
609 return ret;
610}
611
612static void bfin_gpio_irq_shutdown(unsigned int irq)
613{
614 bfin_gpio_mask_irq(irq);
615 gpio_free(irq - IRQ_PA0);
616 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
617}
618
619static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
620{
621
622 unsigned int ret;
623 u16 gpionr = irq - IRQ_PA0;
624 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
625 u32 pintbit = PINT_BIT(pint_val);
626 u8 bank = PINT_2_BANK(pint_val);
627
628 if (pint_val == IRQ_NOT_AVAIL)
629 return -ENODEV;
630
631 if (type == IRQ_TYPE_PROBE) {
632
633 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
634 return 0;
635 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
636 }
637
638 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
639 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
640 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
641 ret = gpio_request(gpionr, "IRQ");
642 if (ret)
643 return ret;
644 }
645
646 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
647 } else {
648 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
649 return 0;
650 }
651
652 gpio_direction_input(gpionr);
653
654 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
655 pint[bank]->edge_set = pintbit;
656 } else {
657 pint[bank]->edge_clear = pintbit;
658 }
659
660 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
661 pint[bank]->invert_set = pintbit;
662 else
663 pint[bank]->invert_set = pintbit;
664
665 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
666 pint[bank]->invert_set = pintbit;
667 else
668 pint[bank]->invert_set = pintbit;
669
670 SSYNC();
671
672 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
673 set_irq_handler(irq, handle_edge_irq);
674 else
675 set_irq_handler(irq, handle_level_irq);
676
677 return 0;
678}
679
680static struct irq_chip bfin_gpio_irqchip = {
681 .ack = bfin_gpio_ack_irq,
682 .mask = bfin_gpio_mask_irq,
683 .mask_ack = bfin_gpio_mask_ack_irq,
684 .unmask = bfin_gpio_unmask_irq,
685 .set_type = bfin_gpio_irq_type,
686 .startup = bfin_gpio_irq_startup,
687 .shutdown = bfin_gpio_irq_shutdown
688};
689
690static void bfin_demux_gpio_irq(unsigned int intb_irq,
691 struct irq_desc *intb_desc)
692{
693 u8 bank, pint_val;
694 u32 request, irq;
695 struct irq_desc *desc;
696
697 switch (intb_irq) {
698 case IRQ_PINT0:
699 bank = 0;
700 break;
701 case IRQ_PINT2:
702 bank = 2;
703 break;
704 case IRQ_PINT3:
705 bank = 3;
706 break;
707 case IRQ_PINT1:
708 bank = 1;
709 break;
710 default:
711 return;
712 }
713
714 pint_val = bank * NR_PINT_BITS;
715
716 request = pint[bank]->request;
717
718 while (request) {
719 if (request & 1) {
720 irq = pint2irq_lut[pint_val] + SYS_IRQS;
721 desc = irq_desc + irq;
722 desc->handle_irq(irq, desc);
723 }
724 pint_val++;
725 request >>= 1;
726 }
727
728}
729#endif
730
731void __init init_exception_vectors(void)
732{
733 SSYNC();
734
735
736
737
738
739 bfin_write_EVT2(evt_nmi);
740 bfin_write_EVT3(trap);
741 bfin_write_EVT5(evt_ivhw);
742 bfin_write_EVT6(evt_timer);
743 bfin_write_EVT7(evt_evt7);
744 bfin_write_EVT8(evt_evt8);
745 bfin_write_EVT9(evt_evt9);
746 bfin_write_EVT10(evt_evt10);
747 bfin_write_EVT11(evt_evt11);
748 bfin_write_EVT12(evt_evt12);
749 bfin_write_EVT13(evt_evt13);
750 bfin_write_EVT14(evt14_softirq);
751 bfin_write_EVT15(evt_system_call);
752 CSYNC();
753}
754
755
756
757
758
759int __init init_arch_irq(void)
760{
761 int irq;
762 unsigned long ilat = 0;
763
764#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
765 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
766 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
767 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
768 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
769# ifdef CONFIG_BF54x
770 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
771 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
772# endif
773#else
774 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
775 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
776#endif
777 SSYNC();
778
779 local_irq_disable();
780
781#ifdef CONFIG_BF54x
782# ifdef CONFIG_PINTx_REASSIGN
783 pint[0]->assign = CONFIG_PINT0_ASSIGN;
784 pint[1]->assign = CONFIG_PINT1_ASSIGN;
785 pint[2]->assign = CONFIG_PINT2_ASSIGN;
786 pint[3]->assign = CONFIG_PINT3_ASSIGN;
787# endif
788
789 init_pint_lut();
790#endif
791
792 for (irq = 0; irq <= SYS_IRQS; irq++) {
793 if (irq <= IRQ_CORETMR)
794 set_irq_chip(irq, &bfin_core_irqchip);
795 else
796 set_irq_chip(irq, &bfin_internal_irqchip);
797#ifdef BF537_GENERIC_ERROR_INT_DEMUX
798 if (irq != IRQ_GENERIC_ERROR) {
799#endif
800
801 switch (irq) {
802#if defined(CONFIG_BF53x)
803 case IRQ_PROG_INTA:
804 set_irq_chained_handler(irq,
805 bfin_demux_gpio_irq);
806 break;
807# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
808 case IRQ_MAC_RX:
809 set_irq_chained_handler(irq,
810 bfin_demux_gpio_irq);
811 break;
812# endif
813#elif defined(CONFIG_BF54x)
814 case IRQ_PINT0:
815 set_irq_chained_handler(irq,
816 bfin_demux_gpio_irq);
817 break;
818 case IRQ_PINT1:
819 set_irq_chained_handler(irq,
820 bfin_demux_gpio_irq);
821 break;
822 case IRQ_PINT2:
823 set_irq_chained_handler(irq,
824 bfin_demux_gpio_irq);
825 break;
826 case IRQ_PINT3:
827 set_irq_chained_handler(irq,
828 bfin_demux_gpio_irq);
829 break;
830#elif defined(CONFIG_BF52x)
831 case IRQ_PORTF_INTA:
832 set_irq_chained_handler(irq,
833 bfin_demux_gpio_irq);
834 break;
835 case IRQ_PORTG_INTA:
836 set_irq_chained_handler(irq,
837 bfin_demux_gpio_irq);
838 break;
839 case IRQ_PORTH_INTA:
840 set_irq_chained_handler(irq,
841 bfin_demux_gpio_irq);
842 break;
843#endif
844 default:
845 set_irq_handler(irq, handle_simple_irq);
846 break;
847 }
848
849#ifdef BF537_GENERIC_ERROR_INT_DEMUX
850 } else {
851 set_irq_handler(irq, bfin_demux_error_irq);
852 }
853#endif
854 }
855#ifdef BF537_GENERIC_ERROR_INT_DEMUX
856 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
857 set_irq_chip(irq, &bfin_generic_error_irqchip);
858 set_irq_handler(irq, handle_level_irq);
859 }
860#endif
861
862#ifndef CONFIG_BF54x
863 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
864#else
865 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
866#endif
867 set_irq_chip(irq, &bfin_gpio_irqchip);
868
869 set_irq_handler(irq, handle_level_irq);
870 }
871
872 bfin_write_IMASK(0);
873 CSYNC();
874 ilat = bfin_read_ILAT();
875 CSYNC();
876 bfin_write_ILAT(ilat);
877 CSYNC();
878
879 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
880
881
882
883 program_IAR();
884
885 search_IAR();
886
887
888 irq_flags = irq_flags | IMASK_IVG15 |
889 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
890 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
891
892 return 0;
893}
894
895#ifdef CONFIG_DO_IRQ_L1
896__attribute__((l1_text))
897#endif
898void do_irq(int vec, struct pt_regs *fp)
899{
900 if (vec == EVT_IVTMR_P) {
901 vec = IRQ_CORETMR;
902 } else {
903 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
904 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
905#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
906 unsigned long sic_status[3];
907
908 SSYNC();
909 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
910 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
911#ifdef CONFIG_BF54x
912 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
913#endif
914 for (;; ivg++) {
915 if (ivg >= ivg_stop) {
916 atomic_inc(&num_spurious);
917 return;
918 }
919 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
920 break;
921 }
922#else
923 unsigned long sic_status;
924 SSYNC();
925 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
926
927 for (;; ivg++) {
928 if (ivg >= ivg_stop) {
929 atomic_inc(&num_spurious);
930 return;
931 } else if (sic_status & ivg->isrflag)
932 break;
933 }
934#endif
935 vec = ivg->irqno;
936 }
937 asm_do_IRQ(vec, fp);
938
939#ifdef CONFIG_KGDB
940 kgdb_process_breakpoint();
941#endif
942}
943
