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9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <asm/sn/sn_sal.h>
13#include <asm/sn/addrs.h>
14#include <asm/sn/io.h>
15#include <asm/sn/pcidev.h>
16#include <asm/sn/pcibus_provider_defs.h>
17#include <asm/sn/tioce_provider.h>
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53
54static void inline
55tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr)
56{
57 u64 mmr_base;
58 u64 mmr_offset;
59
60 if (kern->ce_common->ce_rev != TIOCE_REV_A)
61 return;
62
63 mmr_base = kern->ce_common->ce_pcibus.bs_base;
64 mmr_offset = (unsigned long)mmr_addr - mmr_base;
65
66 if (mmr_offset < 0x45000) {
67 u64 mmr_war_offset;
68
69 if (mmr_offset == 0 || mmr_offset == 0x80)
70 mmr_war_offset = 0xc0;
71 else if (mmr_offset == 0x148 || mmr_offset == 0x200)
72 mmr_war_offset = 0x28;
73 else
74 mmr_war_offset = 0x158;
75
76 readq_relaxed((void __iomem *)(mmr_base + mmr_war_offset));
77 }
78}
79
80static void inline
81tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr)
82{
83 u64 mmr_base;
84 u64 mmr_offset;
85
86 if (kern->ce_common->ce_rev != TIOCE_REV_A)
87 return;
88
89 mmr_base = kern->ce_common->ce_pcibus.bs_base;
90 mmr_offset = (unsigned long)mmr_addr - mmr_base;
91
92 if (mmr_offset < 0x45000) {
93 if (mmr_offset == 0x100)
94 readq_relaxed((void __iomem *)(mmr_base + 0x38));
95 readq_relaxed((void __iomem *)(mmr_base + 0xb050));
96 }
97}
98
99
100#define tioce_mmr_load(kern, mmrp, varp) do {\
101 tioce_mmr_war_pre(kern, mmrp); \
102 *(varp) = readq_relaxed(mmrp); \
103 tioce_mmr_war_post(kern, mmrp); \
104} while (0)
105
106
107#define tioce_mmr_store(kern, mmrp, varp) do {\
108 tioce_mmr_war_pre(kern, mmrp); \
109 writeq(*varp, mmrp); \
110 tioce_mmr_war_post(kern, mmrp); \
111} while (0)
112
113
114#define tioce_mmr_storei(kern, mmrp, val) do {\
115 tioce_mmr_war_pre(kern, mmrp); \
116 writeq(val, mmrp); \
117 tioce_mmr_war_post(kern, mmrp); \
118} while (0)
119
120
121#define tioce_mmr_seti(kern, mmrp, bits) do {\
122 u64 tmp; \
123 tioce_mmr_load(kern, mmrp, &tmp); \
124 tmp |= (bits); \
125 tioce_mmr_store(kern, mmrp, &tmp); \
126} while (0)
127
128
129#define tioce_mmr_clri(kern, mmrp, bits) do { \
130 u64 tmp; \
131 tioce_mmr_load(kern, mmrp, &tmp); \
132 tmp &= ~(bits); \
133 tioce_mmr_store(kern, mmrp, &tmp); \
134} while (0)
135
136
137
138
139
140#define TIOCE_D64_MIN 0x8000000000000000UL
141#define TIOCE_D64_MAX 0xffffffffffffffffUL
142#define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN)
143
144#define TIOCE_D32_MIN 0x0000000080000000UL
145#define TIOCE_D32_MAX 0x00000000ffffffffUL
146#define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
147
148#define TIOCE_M32_MIN 0x0000000000000000UL
149#define TIOCE_M32_MAX 0x000000007fffffffUL
150#define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
151
152#define TIOCE_M40_MIN 0x0000004000000000UL
153#define TIOCE_M40_MAX 0x0000007fffffffffUL
154#define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
155
156#define TIOCE_M40S_MIN 0x0000008000000000UL
157#define TIOCE_M40S_MAX 0x000000ffffffffffUL
158#define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
159
160
161
162
163
164#define ATE_PAGESHIFT(ps) (__ffs(ps))
165#define ATE_PAGEMASK(ps) ((ps)-1)
166
167#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
168#define ATE_NPAGES(start, len, pagesize) \
169 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
170
171#define ATE_VALID(ate) ((ate) & (1UL << 63))
172#define ATE_MAKE(addr, ps, msi) \
173 (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0))
174
175
176
177
178
179#define TIOCE_ATE_M32 1
180#define TIOCE_ATE_M40 2
181#define TIOCE_ATE_M40S 3
182
183#define KB(x) ((u64)(x) << 10)
184#define MB(x) ((u64)(x) << 20)
185#define GB(x) ((u64)(x) << 30)
186
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200
201
202static u64
203tioce_dma_d64(unsigned long ct_addr, int dma_flags)
204{
205 u64 bus_addr;
206
207 bus_addr = ct_addr | (1UL << 63);
208 if (dma_flags & SN_DMA_MSI)
209 bus_addr |= (1UL << 61);
210
211 return bus_addr;
212}
213
214
215
216
217
218
219
220
221
222
223
224static inline void
225pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
226 struct tioce_kernel **kernel, int *port)
227{
228 struct pcidev_info *pcidev_info;
229 struct tioce_common *ce_common;
230 struct tioce_kernel *ce_kernel;
231
232 pcidev_info = SN_PCIDEV_INFO(pdev);
233 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
234 ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
235
236 if (base)
237 *base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
238 if (kernel)
239 *kernel = ce_kernel;
240
241
242
243
244
245 if (port)
246 *port =
247 (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1;
248}
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264static u64
265tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
266 u64 ct_addr, int len, int dma_flags)
267{
268 int i;
269 int j;
270 int first;
271 int last;
272 int entries;
273 int nates;
274 u64 pagesize;
275 int msi_capable, msi_wanted;
276 u64 *ate_shadow;
277 u64 __iomem *ate_reg;
278 u64 addr;
279 struct tioce __iomem *ce_mmr;
280 u64 bus_base;
281 struct tioce_dmamap *map;
282
283 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
284
285 switch (type) {
286 case TIOCE_ATE_M32:
287
288
289
290
291 first = 64;
292 entries = TIOCE_NUM_M3240_ATES - 64;
293 ate_shadow = ce_kern->ce_ate3240_shadow;
294 ate_reg = ce_mmr->ce_ure_ate3240;
295 pagesize = ce_kern->ce_ate3240_pagesize;
296 bus_base = TIOCE_M32_MIN;
297 msi_capable = 1;
298 break;
299 case TIOCE_ATE_M40:
300 first = 0;
301 entries = TIOCE_NUM_M40_ATES;
302 ate_shadow = ce_kern->ce_ate40_shadow;
303 ate_reg = ce_mmr->ce_ure_ate40;
304 pagesize = MB(64);
305 bus_base = TIOCE_M40_MIN;
306 msi_capable = 0;
307 break;
308 case TIOCE_ATE_M40S:
309
310
311
312
313 first = port * 32;
314 entries = 32;
315 ate_shadow = ce_kern->ce_ate3240_shadow;
316 ate_reg = ce_mmr->ce_ure_ate3240;
317 pagesize = GB(16);
318 bus_base = TIOCE_M40S_MIN;
319 msi_capable = 0;
320 break;
321 default:
322 return 0;
323 }
324
325 msi_wanted = dma_flags & SN_DMA_MSI;
326 if (msi_wanted && !msi_capable)
327 return 0;
328
329 nates = ATE_NPAGES(ct_addr, len, pagesize);
330 if (nates > entries)
331 return 0;
332
333 last = first + entries - nates;
334 for (i = first; i <= last; i++) {
335 if (ATE_VALID(ate_shadow[i]))
336 continue;
337
338 for (j = i; j < i + nates; j++)
339 if (ATE_VALID(ate_shadow[j]))
340 break;
341
342 if (j >= i + nates)
343 break;
344 }
345
346 if (i > last)
347 return 0;
348
349 map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC);
350 if (!map)
351 return 0;
352
353 addr = ct_addr;
354 for (j = 0; j < nates; j++) {
355 u64 ate;
356
357 ate = ATE_MAKE(addr, pagesize, msi_wanted);
358 ate_shadow[i + j] = ate;
359 tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate);
360 addr += pagesize;
361 }
362
363 map->refcnt = 1;
364 map->nbytes = nates * pagesize;
365 map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize);
366 map->pci_start = bus_base + (i * pagesize);
367 map->ate_hw = &ate_reg[i];
368 map->ate_shadow = &ate_shadow[i];
369 map->ate_count = nates;
370
371 list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list);
372
373 return (map->pci_start + (ct_addr - map->ct_start));
374}
375
376
377
378
379
380
381
382
383static u64
384tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags)
385{
386 int dma_ok;
387 int port;
388 struct tioce __iomem *ce_mmr;
389 struct tioce_kernel *ce_kern;
390 u64 ct_upper;
391 u64 ct_lower;
392 dma_addr_t bus_addr;
393
394 if (dma_flags & SN_DMA_MSI)
395 return 0;
396
397 ct_upper = ct_addr & ~0x3fffffffUL;
398 ct_lower = ct_addr & 0x3fffffffUL;
399
400 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
401
402 if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
403 u64 tmp;
404
405 ce_kern->ce_port[port].dirmap_shadow = ct_upper;
406 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
407 ct_upper);
408 tmp = ce_mmr->ce_ure_dir_map[port];
409 dma_ok = 1;
410 } else
411 dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper);
412
413 if (dma_ok) {
414 ce_kern->ce_port[port].dirmap_refcnt++;
415 bus_addr = TIOCE_D32_MIN + ct_lower;
416 } else
417 bus_addr = 0;
418
419 return bus_addr;
420}
421
422
423
424
425
426
427
428
429
430static u64
431tioce_dma_barrier(u64 bus_addr, int on)
432{
433 u64 barrier_bit;
434
435
436 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
437 return bus_addr;
438
439 if (TIOCE_D64_ADDR(bus_addr))
440 barrier_bit = (1UL << 62);
441 else
442 barrier_bit = (1UL << 30);
443
444 return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit);
445}
446
447
448
449
450
451
452
453
454
455
456
457void
458tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
459{
460 int i;
461 int port;
462 struct tioce_kernel *ce_kern;
463 struct tioce __iomem *ce_mmr;
464 unsigned long flags;
465
466 bus_addr = tioce_dma_barrier(bus_addr, 0);
467 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
468
469
470
471 if (TIOCE_D64_ADDR(bus_addr))
472 return;
473
474 spin_lock_irqsave(&ce_kern->ce_lock, flags);
475
476 if (TIOCE_D32_ADDR(bus_addr)) {
477 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
478 ce_kern->ce_port[port].dirmap_shadow = 0;
479 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
480 0);
481 }
482 } else {
483 struct tioce_dmamap *map;
484
485 list_for_each_entry(map, &ce_kern->ce_dmamap_list,
486 ce_dmamap_list) {
487 u64 last;
488
489 last = map->pci_start + map->nbytes - 1;
490 if (bus_addr >= map->pci_start && bus_addr <= last)
491 break;
492 }
493
494 if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) {
495 printk(KERN_WARNING
496 "%s: %s - no map found for bus_addr 0x%lx\n",
497 __FUNCTION__, pci_name(pdev), bus_addr);
498 } else if (--map->refcnt == 0) {
499 for (i = 0; i < map->ate_count; i++) {
500 map->ate_shadow[i] = 0;
501 tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0);
502 }
503
504 list_del(&map->ce_dmamap_list);
505 kfree(map);
506 }
507 }
508
509 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
510}
511
512
513
514
515
516
517
518
519
520
521static u64
522tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
523 int barrier, int dma_flags)
524{
525 unsigned long flags;
526 u64 ct_addr;
527 u64 mapaddr = 0;
528 struct tioce_kernel *ce_kern;
529 struct tioce_dmamap *map;
530 int port;
531 u64 dma_mask;
532
533 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
534
535
536 if (dma_mask < 0x7fffffffUL)
537 return 0;
538
539 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
540 ct_addr = PHYS_TO_TIODMA(paddr);
541 else
542 ct_addr = paddr;
543
544
545
546
547 if (dma_mask == ~0UL) {
548 mapaddr = tioce_dma_d64(ct_addr, dma_flags);
549 if (mapaddr)
550 goto dma_map_done;
551 }
552
553 pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
554
555 spin_lock_irqsave(&ce_kern->ce_lock, flags);
556
557
558
559
560
561
562
563 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
564 u64 last;
565
566 last = map->ct_start + map->nbytes - 1;
567 if (ct_addr >= map->ct_start &&
568 ct_addr + byte_count - 1 <= last &&
569 map->pci_start <= dma_mask) {
570 map->refcnt++;
571 mapaddr = map->pci_start + (ct_addr - map->ct_start);
572 break;
573 }
574 }
575
576
577
578
579
580
581
582 if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
583
584
585
586
587
588
589
590
591 if (byte_count > MB(64)) {
592 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
593 port, ct_addr, byte_count,
594 dma_flags);
595 if (!mapaddr)
596 mapaddr =
597 tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
598 ct_addr, byte_count,
599 dma_flags);
600 } else {
601 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
602 ct_addr, byte_count,
603 dma_flags);
604 if (!mapaddr)
605 mapaddr =
606 tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
607 port, ct_addr, byte_count,
608 dma_flags);
609 }
610 }
611
612
613
614
615 if (!mapaddr && dma_mask >= 0xffffffffUL)
616 mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags);
617
618
619
620
621 if (!mapaddr)
622 mapaddr =
623 tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
624 byte_count, dma_flags);
625
626 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
627
628dma_map_done:
629 if (mapaddr && barrier)
630 mapaddr = tioce_dma_barrier(mapaddr, 1);
631
632 return mapaddr;
633}
634
635
636
637
638
639
640
641
642
643
644static u64
645tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
646{
647 return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags);
648}
649
650
651
652
653
654
655
656
657
658 static u64
659tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
660{
661 return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags);
662}
663
664
665
666
667
668
669
670
671 static irqreturn_t
672tioce_error_intr_handler(int irq, void *arg)
673{
674 struct tioce_common *soft = arg;
675 struct ia64_sal_retval ret_stuff;
676 ret_stuff.status = 0;
677 ret_stuff.v0 = 0;
678
679 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
680 soft->ce_pcibus.bs_persist_segment,
681 soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
682
683 if (ret_stuff.v0)
684 panic("tioce_error_intr_handler: Fatal TIOCE error");
685
686 return IRQ_HANDLED;
687}
688
689
690
691
692
693
694
695
696
697
698static void
699tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
700{
701 int ate_index, last_ate, ps;
702 struct tioce __iomem *ce_mmr;
703
704 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
705 ps = ce_kern->ce_ate3240_pagesize;
706 ate_index = ATE_PAGE(base, ps);
707 last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
708
709 if (ate_index < 64)
710 ate_index = 64;
711
712 if (last_ate >= TIOCE_NUM_M3240_ATES)
713 last_ate = TIOCE_NUM_M3240_ATES - 1;
714
715 while (ate_index <= last_ate) {
716 u64 ate;
717
718 ate = ATE_MAKE(0xdeadbeef, ps, 0);
719 ce_kern->ce_ate3240_shadow[ate_index] = ate;
720 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index],
721 ate);
722 ate_index++;
723 }
724}
725
726
727
728
729
730static struct tioce_kernel *
731tioce_kern_init(struct tioce_common *tioce_common)
732{
733 int i;
734 int ps;
735 int dev;
736 u32 tmp;
737 unsigned int seg, bus;
738 struct tioce __iomem *tioce_mmr;
739 struct tioce_kernel *tioce_kern;
740
741 tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
742 if (!tioce_kern) {
743 return NULL;
744 }
745
746 tioce_kern->ce_common = tioce_common;
747 spin_lock_init(&tioce_kern->ce_lock);
748 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
749 tioce_common->ce_kernel_private = (u64) tioce_kern;
750
751
752
753
754
755
756
757
758 seg = tioce_common->ce_pcibus.bs_persist_segment;
759 bus = tioce_common->ce_pcibus.bs_persist_busnum;
760
761 raw_pci_ops->read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
762 tioce_kern->ce_port1_secondary = (u8) tmp;
763
764
765
766
767
768
769 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
770 tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
771 CE_URE_PAGESIZE_MASK);
772 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
773 CE_URE_256K_PAGESIZE);
774 ps = tioce_kern->ce_ate3240_pagesize = KB(256);
775
776 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
777 tioce_kern->ce_ate40_shadow[i] = 0;
778 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0);
779 }
780
781 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
782 tioce_kern->ce_ate3240_shadow[i] = 0;
783 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0);
784 }
785
786
787
788
789
790
791
792
793
794
795
796
797 for (dev = 1; dev <= 2; dev++) {
798 u64 base, limit;
799
800
801
802 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
803 PCI_MEMORY_BASE, 2, &tmp);
804 base = (u64)tmp << 16;
805
806 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
807 PCI_MEMORY_LIMIT, 2, &tmp);
808 limit = (u64)tmp << 16;
809 limit |= 0xfffffUL;
810
811 if (base < limit)
812 tioce_reserve_m32(tioce_kern, base, limit);
813
814
815
816
817
818
819
820 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
821 PCI_PREF_MEMORY_BASE, 2, &tmp);
822 base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
823
824 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
825 PCI_PREF_BASE_UPPER32, 4, &tmp);
826 base |= (u64)tmp << 32;
827
828 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
829 PCI_PREF_MEMORY_LIMIT, 2, &tmp);
830
831 limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
832 limit |= 0xfffffUL;
833
834 raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
835 PCI_PREF_LIMIT_UPPER32, 4, &tmp);
836 limit |= (u64)tmp << 32;
837
838 if ((base < limit) && TIOCE_M32_ADDR(base))
839 tioce_reserve_m32(tioce_kern, base, limit);
840 }
841
842 return tioce_kern;
843}
844
845
846
847
848
849
850
851
852
853
854static void
855tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
856{
857 struct pcidev_info *pcidev_info;
858 struct tioce_common *ce_common;
859 struct tioce_kernel *ce_kern;
860 struct tioce __iomem *ce_mmr;
861 u64 force_int_val;
862
863 if (!sn_irq_info->irq_bridge)
864 return;
865
866 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE)
867 return;
868
869 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
870 if (!pcidev_info)
871 return;
872
873 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
874 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
875 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
876
877
878
879
880
881 if (ce_common->ce_rev == TIOCE_REV_A) {
882 u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit);
883 u64 status;
884
885 tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status);
886 if (status & int_bit_mask) {
887 u64 force_irq = (1 << 8) | sn_irq_info->irq_irq;
888 u64 ctalk = sn_irq_info->irq_xtalkaddr;
889 u64 nasid, offset;
890
891 nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT;
892 offset = (ctalk & CTALK_NODE_OFFSET);
893 HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq);
894 }
895
896 return;
897 }
898
899
900
901
902
903
904
905
906
907 switch (sn_irq_info->irq_int_bit) {
908 case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT:
909 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT;
910 break;
911 case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT:
912 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT;
913 break;
914 case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT:
915 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT;
916 break;
917 case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT:
918 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT;
919 break;
920 case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT:
921 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT;
922 break;
923 case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT:
924 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT;
925 break;
926 case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT:
927 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT;
928 break;
929 case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT:
930 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT;
931 break;
932 default:
933 return;
934 }
935 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val);
936}
937
938
939
940
941
942
943
944
945
946
947
948
949static void
950tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
951{
952 struct pcidev_info *pcidev_info;
953 struct tioce_common *ce_common;
954 struct tioce_kernel *ce_kern;
955 struct tioce __iomem *ce_mmr;
956 int bit;
957 u64 vector;
958
959 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
960 if (!pcidev_info)
961 return;
962
963 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
964 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
965 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
966
967 bit = sn_irq_info->irq_int_bit;
968
969 tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
970 vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
971 vector |= sn_irq_info->irq_xtalkaddr;
972 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector);
973 tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
974
975 tioce_force_interrupt(sn_irq_info);
976}
977
978
979
980
981
982
983
984
985
986
987
988
989static void *
990tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
991{
992 struct tioce_common *tioce_common;
993 struct tioce_kernel *tioce_kern;
994 struct tioce __iomem *tioce_mmr;
995
996
997
998
999
1000 tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL);
1001 if (!tioce_common)
1002 return NULL;
1003
1004 memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
1005 tioce_common->ce_pcibus.bs_base = (unsigned long)
1006 ioremap(REGION_OFFSET(tioce_common->ce_pcibus.bs_base),
1007 sizeof(struct tioce_common));
1008
1009 tioce_kern = tioce_kern_init(tioce_common);
1010 if (tioce_kern == NULL) {
1011 kfree(tioce_common);
1012 return NULL;
1013 }
1014
1015
1016
1017
1018
1019
1020 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
1021 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
1022 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
1023 ~0ULL);
1024 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, 0ULL);
1025
1026 if (request_irq(SGI_PCIASIC_ERROR,
1027 tioce_error_intr_handler,
1028 IRQF_SHARED, "TIOCE error", (void *)tioce_common))
1029 printk(KERN_WARNING
1030 "%s: Unable to get irq %d. "
1031 "Error interrupts won't be routed for "
1032 "TIOCE bus %04x:%02x\n",
1033 __FUNCTION__, SGI_PCIASIC_ERROR,
1034 tioce_common->ce_pcibus.bs_persist_segment,
1035 tioce_common->ce_pcibus.bs_persist_busnum);
1036
1037 sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
1038 return tioce_common;
1039}
1040
1041static struct sn_pcibus_provider tioce_pci_interfaces = {
1042 .dma_map = tioce_dma,
1043 .dma_map_consistent = tioce_dma_consistent,
1044 .dma_unmap = tioce_dma_unmap,
1045 .bus_fixup = tioce_bus_fixup,
1046 .force_interrupt = tioce_force_interrupt,
1047 .target_interrupt = tioce_target_interrupt
1048};
1049
1050
1051
1052
1053int
1054tioce_init_provider(void)
1055{
1056 sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces;
1057 return 0;
1058}
1059