1/*****************************************************************************/ 2 3/* 4 * head.S -- common startup code for ColdFire CPUs. 5 * 6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. 7 */ 8 9/*****************************************************************************/ 10 11#include <linux/sys.h> 12#include <linux/linkage.h> 13#include <asm/asm-offsets.h> 14#include <asm/coldfire.h> 15#include <asm/mcfcache.h> 16#include <asm/mcfsim.h> 17 18/*****************************************************************************/ 19 20/* 21 * If we don't have a fixed memory size, then lets build in code 22 * to auto detect the DRAM size. Obviously this is the prefered 23 * method, and should work for most boards. It won't work for those 24 * that do not have their RAM starting at address 0, and it only 25 * works on SDRAM (not boards fitted with SRAM). 26 */ 27#if CONFIG_RAMSIZE != 0 28.macro GET_MEM_SIZE 29 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ 30.endm 31 32#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 33 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ 34 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ 35 defined(CONFIG_M5407) 36/* 37 * Not all these devices have exactly the same DRAM controller, 38 * but the DCMR register is virtually identical - give or take 39 * a couple of bits. The only exception is the 5272 devices, their 40 * DRAM controller is quite different. 41 */ 42.macro GET_MEM_SIZE 43 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */ 44 btst #0,%d0 /* check if region enabled */ 45 beq 1f 46 andl #0xfffc0000,%d0 47 beq 1f 48 addl #0x00040000,%d0 /* convert mask to size */ 491: 50 movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ 51 btst #0,%d1 /* check if region enabled */ 52 beq 2f 53 andl #0xfffc0000, %d1 54 beq 2f 55 addl #0x00040000,%d1 56 addl %d1,%d0 /* total mem size in d0 */ 572: 58.endm 59 60#elif defined(CONFIG_M5272) 61.macro GET_MEM_SIZE 62 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 63 andil #0xfffff000,%d0 /* mask out chip select options */ 64 negl %d0 /* negate bits */ 65.endm 66 67#elif defined(CONFIG_M520x) 68.macro GET_MEM_SIZE 69 clrl %d0 70 movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ 71 andl #0x1f, %d2 /* Get only the chip select size */ 72 beq 3f /* Check if it is enabled */ 73 addql #1, %d2 /* Form exponent */ 74 moveql #1, %d0 75 lsll %d2, %d0 /* 2 ^ exponent */ 763: 77 movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ 78 andl #0x1f, %d2 /* Get only the chip select size */ 79 beq 4f /* Check if it is enabled */ 80 addql #1, %d2 /* Form exponent */ 81 moveql #1, %d1 82 lsll %d2, %d1 /* 2 ^ exponent */ 83 addl %d1, %d0 /* Total size of SDRAM in d0 */ 844: 85.endm 86 87#else 88#error "ERROR: I don't know how to probe your boards memory size?" 89#endif 90 91/*****************************************************************************/ 92 93/* 94 * Boards and platforms can do specific early hardware setup if 95 * they need to. Most don't need this, define away if not required. 96 */ 97#ifndef PLATFORM_SETUP 98#define PLATFORM_SETUP 99#endif 100 101/*****************************************************************************/ 102 103.global _start 104.global _rambase 105.global _ramvec 106.global _ramstart 107.global _ramend 108 109/*****************************************************************************/ 110 111.data 112 113/* 114 * During startup we store away the RAM setup. These are not in the 115 * bss, since their values are determined and written before the bss 116 * has been cleared. 117 */ 118_rambase: 119.long 0 120_ramvec: 121.long 0 122_ramstart: 123.long 0 124_ramend: 125.long 0 126 127/*****************************************************************************/ 128 129.text 130 131/* 132 * This is the codes first entry point. This is where it all 133 * begins... 134 */ 135 136_start: 137 nop /* filler */ 138 movew #0x2700, %sr /* no interrupts */ 139 140 /* 141 * Do any platform or board specific setup now. Most boards 142 * don't need anything. Those exceptions are define this in 143 * their board specific includes. 144 */ 145 PLATFORM_SETUP 146 147 /* 148 * Create basic memory configuration. Set VBR accordingly, 149 * and size memory. 150 */ 151 movel #CONFIG_VECTORBASE,%a7 152 movec %a7,%VBR /* set vectors addr */ 153 movel %a7,_ramvec 154 155 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ 156 movel %a7,_rambase 157 158 GET_MEM_SIZE /* macro code determines size */ 159 addl %a7,%d0 160 movel %d0,_ramend /* set end ram addr */ 161 162 /* 163 * Now that we know what the memory is, lets enable cache 164 * and get things moving. This is Coldfire CPU specific. 165 */ 166 CACHE_ENABLE /* enable CPU cache */ 167 168 169#ifdef CONFIG_ROMFS_FS 170 /* 171 * Move ROM filesystem above bss :-) 172 */ 173 lea _sbss,%a0 /* get start of bss */ 174 lea _ebss,%a1 /* set up destination */ 175 movel %a0,%a2 /* copy of bss start */ 176 177 movel 8(%a0),%d0 /* get size of ROMFS */ 178 addql #8,%d0 /* allow for rounding */ 179 andl #0xfffffffc, %d0 /* whole words */ 180 181 addl %d0,%a0 /* copy from end */ 182 addl %d0,%a1 /* copy from end */ 183 movel %a1,_ramstart /* set start of ram */ 184 185_copy_romfs: 186 movel -(%a0),%d0 /* copy dword */ 187 movel %d0,-(%a1) 188 cmpl %a0,%a2 /* check if at end */ 189 bne _copy_romfs 190 191#else /* CONFIG_ROMFS_FS */ 192 lea _ebss,%a1 193 movel %a1,_ramstart 194#endif /* CONFIG_ROMFS_FS */ 195 196 197 /* 198 * Zero out the bss region. 199 */ 200 lea _sbss,%a0 /* get start of bss */ 201 lea _ebss,%a1 /* get end of bss */ 202 clrl %d0 /* set value */ 203_clear_bss: 204 movel %d0,(%a0)+ /* clear each word */ 205 cmpl %a0,%a1 /* check if at end */ 206 bne _clear_bss 207 208 /* 209 * Load the current task pointer and stack. 210 */ 211 lea init_thread_union,%a0 212 lea THREAD_SIZE(%a0),%sp 213 214 /* 215 * Assember start up done, start code proper. 216 */ 217 jsr start_kernel /* start Linux kernel */ 218 219_exit: 220 jmp _exit /* should never get here */ 221 222/*****************************************************************************/ 223