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14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/ioport.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/console.h>
20#include <linux/pci.h>
21#include <linux/pm.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24
25#include <asm/wbflush.h>
26#include <asm/reboot.h>
27#include <asm/irq.h>
28#include <asm/time.h>
29#include <asm/txx9tmr.h>
30#include <asm/uaccess.h>
31#include <asm/io.h>
32#include <asm/bootinfo.h>
33#include <asm/tx4938/rbtx4938.h>
34#ifdef CONFIG_SERIAL_TXX9
35#include <linux/tty.h>
36#include <linux/serial.h>
37#include <linux/serial_core.h>
38#endif
39#include <linux/spi/spi.h>
40#include <asm/tx4938/spi.h>
41#include <asm/gpio.h>
42
43extern char * __init prom_getcmdline(void);
44static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
45
46
47extern void rbtx4938_machine_restart(char *command);
48extern void rbtx4938_machine_halt(void);
49extern void rbtx4938_machine_power_off(void);
50
51
52unsigned int txx9_master_clock;
53unsigned int txx9_cpu_clock;
54unsigned int txx9_gbus_clock;
55
56unsigned long rbtx4938_ce_base[8];
57unsigned long rbtx4938_ce_size[8];
58int txboard_pci66_mode;
59static int tx4938_pcic_trdyto;
60static int tx4938_pcic_retryto;
61static int tx4938_ccfg_toeon = 1;
62
63struct tx4938_pcic_reg *pcicptrs[4] = {
64 tx4938_pcicptr
65};
66
67static struct {
68 unsigned long base;
69 unsigned long size;
70} phys_regions[16] __initdata;
71static int num_phys_regions __initdata;
72
73#define PHYS_REGION_MINSIZE 0x10000
74
75void rbtx4938_machine_halt(void)
76{
77 printk(KERN_NOTICE "System Halted\n");
78 local_irq_disable();
79
80 while (1)
81 __asm__(".set\tmips3\n\t"
82 "wait\n\t"
83 ".set\tmips0");
84}
85
86void rbtx4938_machine_power_off(void)
87{
88 rbtx4938_machine_halt();
89
90}
91
92void rbtx4938_machine_restart(char *command)
93{
94 local_irq_disable();
95
96 printk("Rebooting...");
97 *rbtx4938_softresetlock_ptr = 1;
98 *rbtx4938_sfvol_ptr = 1;
99 *rbtx4938_softreset_ptr = 1;
100 wbflush();
101
102 while(1);
103}
104
105void __init
106txboard_add_phys_region(unsigned long base, unsigned long size)
107{
108 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
109 printk("phys_region overflow\n");
110 return;
111 }
112 phys_regions[num_phys_regions].base = base;
113 phys_regions[num_phys_regions].size = size;
114 num_phys_regions++;
115}
116unsigned long __init
117txboard_find_free_phys_region(unsigned long begin, unsigned long end,
118 unsigned long size)
119{
120 unsigned long base;
121 int i;
122
123 for (base = begin / size * size; base < end; base += size) {
124 for (i = 0; i < num_phys_regions; i++) {
125 if (phys_regions[i].size &&
126 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
127 base + (size - 1) >= phys_regions[i].base)
128 break;
129 }
130 if (i == num_phys_regions)
131 return base;
132 }
133 return 0;
134}
135unsigned long __init
136txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
137 unsigned long *size)
138{
139 unsigned long sz, base;
140 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
141 base = txboard_find_free_phys_region(begin, end, sz);
142 if (base) {
143 *size = sz;
144 return base;
145 }
146 }
147 return 0;
148}
149unsigned long __init
150txboard_request_phys_region_range(unsigned long begin, unsigned long end,
151 unsigned long size)
152{
153 unsigned long base;
154 base = txboard_find_free_phys_region(begin, end, size);
155 if (base)
156 txboard_add_phys_region(base, size);
157 return base;
158}
159unsigned long __init
160txboard_request_phys_region(unsigned long size)
161{
162 unsigned long base;
163 unsigned long begin = 0, end = 0x20000000;
164 base = txboard_find_free_phys_region(begin, end, size);
165 if (base)
166 txboard_add_phys_region(base, size);
167 return base;
168}
169unsigned long __init
170txboard_request_phys_region_shrink(unsigned long *size)
171{
172 unsigned long base;
173 unsigned long begin = 0, end = 0x20000000;
174 base = txboard_find_free_phys_region_shrink(begin, end, size);
175 if (base)
176 txboard_add_phys_region(base, *size);
177 return base;
178}
179
180#ifdef CONFIG_PCI
181void __init
182tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
183 struct pci_controller *channel,
184 unsigned long pci_io_base,
185 int extarb)
186{
187 int i;
188
189
190 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
191 TX4938_PCIC_PCICCFG_G2PMEN(1)|
192 TX4938_PCIC_PCICCFG_G2PMEN(2)|
193 TX4938_PCIC_PCICCFG_G2PIOEN);
194
195
196 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
197 pcicptr->g2piogbase = pci_io_base |
198#ifdef __BIG_ENDIAN
199 TX4938_PCIC_G2PIOGBASE_ECHG
200#else
201 TX4938_PCIC_G2PIOGBASE_BSDIS
202#endif
203 ;
204 pcicptr->g2piopbase = 0;
205 for (i = 0; i < 3; i++) {
206 pcicptr->g2pmmask[i] = 0;
207 pcicptr->g2pmgbase[i] = 0;
208 pcicptr->g2pmpbase[i] = 0;
209 }
210 if (channel->mem_resource->end) {
211 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
212 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
213#ifdef __BIG_ENDIAN
214 TX4938_PCIC_G2PMnGBASE_ECHG
215#else
216 TX4938_PCIC_G2PMnGBASE_BSDIS
217#endif
218 ;
219 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
220 }
221
222 pcicptr->p2giopbase = 0;
223 pcicptr->p2giogbase = 0;
224
225 pcicptr->p2gm0plbase = 0;
226 pcicptr->p2gm0pubase = 0;
227 pcicptr->p2gmgbase[0] = 0 |
228 TX4938_PCIC_P2GMnGBASE_TMEMEN |
229#ifdef __BIG_ENDIAN
230 TX4938_PCIC_P2GMnGBASE_TECHG
231#else
232 TX4938_PCIC_P2GMnGBASE_TBSDIS
233#endif
234 ;
235
236 pcicptr->p2gm1plbase = 0xffffffff;
237 pcicptr->p2gm1pubase = 0xffffffff;
238 pcicptr->p2gmgbase[1] = 0;
239
240 pcicptr->p2gm2pbase = 0xffffffff;
241 pcicptr->p2gmgbase[2] = 0;
242
243 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
244
245 if (channel->mem_resource->end)
246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
247
248 if (channel->io_resource->end)
249 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
250
251 pcicptr->pciccfg |=
252 TX4938_PCIC_PCICCFG_ICAEN |
253 TX4938_PCIC_PCICCFG_TCAR;
254
255
256 pcicptr->pcicfg1 = 0;
257
258 pcicptr->g2ptocnt &= ~0xffff;
259
260 if (tx4938_pcic_trdyto >= 0) {
261 pcicptr->g2ptocnt &= ~0xff;
262 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
263 }
264
265 if (tx4938_pcic_retryto >= 0) {
266 pcicptr->g2ptocnt &= ~0xff00;
267 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
268 }
269
270
271 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
272
273 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
274
275 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
276
277 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
278
279 pcicptr->pcistatus =
280 (pcicptr->pcistatus & 0x0000ffff) |
281 (TX4938_PCIC_PCISTATUS_ALL << 16);
282
283 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
284
285 if (!extarb) {
286
287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
288 pcicptr->pbabm = 0;
289
290 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
291 }
292
293
294 pcicptr->pcicfg2 =
295 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
296
297 pcicptr->pcistatus = PCI_COMMAND_MASTER |
298 PCI_COMMAND_MEMORY |
299 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
300}
301
302int __init
303tx4938_report_pciclk(void)
304{
305 unsigned long pcode = TX4938_REV_PCODE();
306 int pciclk = 0;
307 printk("TX%lx PCIC --%s PCICLK:",
308 pcode,
309 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
310 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
311
312 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
313 case TX4938_CCFG_PCIDIVMODE_4:
314 pciclk = txx9_cpu_clock / 4; break;
315 case TX4938_CCFG_PCIDIVMODE_4_5:
316 pciclk = txx9_cpu_clock * 2 / 9; break;
317 case TX4938_CCFG_PCIDIVMODE_5:
318 pciclk = txx9_cpu_clock / 5; break;
319 case TX4938_CCFG_PCIDIVMODE_5_5:
320 pciclk = txx9_cpu_clock * 2 / 11; break;
321 case TX4938_CCFG_PCIDIVMODE_8:
322 pciclk = txx9_cpu_clock / 8; break;
323 case TX4938_CCFG_PCIDIVMODE_9:
324 pciclk = txx9_cpu_clock / 9; break;
325 case TX4938_CCFG_PCIDIVMODE_10:
326 pciclk = txx9_cpu_clock / 10; break;
327 case TX4938_CCFG_PCIDIVMODE_11:
328 pciclk = txx9_cpu_clock / 11; break;
329 }
330 printk("Internal(%dMHz)", pciclk / 1000000);
331 } else {
332 printk("External");
333 pciclk = -1;
334 }
335 printk("\n");
336 return pciclk;
337}
338
339void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
340{
341 pcicptrs[ch] = pcicptr;
342}
343
344struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
345{
346 return pcicptrs[ch];
347}
348
349static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
350 int top_bus, int busnr, int devfn)
351{
352 static struct pci_dev dev;
353 static struct pci_bus bus;
354
355 dev.sysdata = bus.sysdata = hose;
356 dev.devfn = devfn;
357 bus.number = busnr;
358 bus.ops = hose->pci_ops;
359 bus.parent = NULL;
360 dev.bus = &bus;
361
362 return &dev;
363}
364
365#define EARLY_PCI_OP(rw, size, type) \
366static int early_##rw##_config_##size(struct pci_controller *hose, \
367 int top_bus, int bus, int devfn, int offset, type value) \
368{ \
369 return pci_##rw##_config_##size( \
370 fake_pci_dev(hose, top_bus, bus, devfn), \
371 offset, value); \
372}
373
374EARLY_PCI_OP(read, word, u16 *)
375
376int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
377{
378 u32 pci_devfn;
379 unsigned short vid;
380 int devfn_start = 0;
381 int devfn_stop = 0xff;
382 int cap66 = -1;
383 u16 stat;
384
385 printk("PCI: Checking 66MHz capabilities...\n");
386
387 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
388 if (early_read_config_word(hose, top_bus, current_bus,
389 pci_devfn, PCI_VENDOR_ID,
390 &vid) != PCIBIOS_SUCCESSFUL)
391 continue;
392
393 if (vid == 0xffff) continue;
394
395
396 if (cap66 < 0)
397 cap66 = 1;
398 if (cap66) {
399 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
400 PCI_STATUS, &stat);
401 if (!(stat & PCI_STATUS_66MHZ)) {
402 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
403 current_bus, pci_devfn);
404 cap66 = 0;
405 break;
406 }
407 }
408 }
409 return cap66 > 0;
410}
411
412int __init
413tx4938_pciclk66_setup(void)
414{
415 int pciclk;
416
417
418 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
419
420 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
421 unsigned int pcidivmode =
422 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
423 switch (pcidivmode) {
424 case TX4938_CCFG_PCIDIVMODE_8:
425 case TX4938_CCFG_PCIDIVMODE_4:
426 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
427 pciclk = txx9_cpu_clock / 4;
428 break;
429 case TX4938_CCFG_PCIDIVMODE_9:
430 case TX4938_CCFG_PCIDIVMODE_4_5:
431 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
432 pciclk = txx9_cpu_clock * 2 / 9;
433 break;
434 case TX4938_CCFG_PCIDIVMODE_10:
435 case TX4938_CCFG_PCIDIVMODE_5:
436 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
437 pciclk = txx9_cpu_clock / 5;
438 break;
439 case TX4938_CCFG_PCIDIVMODE_11:
440 case TX4938_CCFG_PCIDIVMODE_5_5:
441 default:
442 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
443 pciclk = txx9_cpu_clock * 2 / 11;
444 break;
445 }
446 tx4938_ccfgptr->ccfg =
447 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
448 | pcidivmode;
449 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
450 (unsigned long)tx4938_ccfgptr->ccfg);
451 } else {
452 pciclk = -1;
453 }
454 return pciclk;
455}
456
457extern struct pci_controller tx4938_pci_controller[];
458static int __init tx4938_pcibios_init(void)
459{
460 unsigned long mem_base[2];
461 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1};
462 unsigned long io_base[2];
463 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1};
464
465 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
466
467 PCIBIOS_MIN_IO = 0x00001000UL;
468
469 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
470 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
471
472 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
473 (unsigned short)(tx4938_pcicptr->pciid >> 16),
474 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
475 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
476 extarb ? "External" : "Internal");
477
478
479 tx4938_pci_controller[0].io_resource->start = io_base[0];
480 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
481 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
482 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
483
484 set_tx4938_pcicptr(0, tx4938_pcicptr);
485
486 register_pci_controller(&tx4938_pci_controller[0]);
487
488 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
489 printk("TX4938_CCFG_PCI66 already configured\n");
490 txboard_pci66_mode = -1;
491 }
492
493
494 *rbtx4938_pcireset_ptr = 0;
495
496 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
497 if (txboard_pci66_mode > 0)
498 tx4938_pciclk66_setup();
499 mdelay(10);
500
501 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
502 *rbtx4938_pcireset_ptr = 1;
503 wbflush();
504 tx4938_report_pcic_status1(tx4938_pcicptr);
505
506 tx4938_report_pciclk();
507 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
508 if (txboard_pci66_mode == 0 &&
509 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
510
511 *rbtx4938_pcireset_ptr = 0;
512
513 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
514 tx4938_pciclk66_setup();
515 mdelay(10);
516
517 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
518 *rbtx4938_pcireset_ptr = 1;
519 wbflush();
520
521 tx4938_report_pciclk();
522 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
523 }
524
525 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
526 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
527
528 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
529
530 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
531 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
532 else
533 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
534 mdelay(10);
535
536 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
537 tx4938_report_pcic_status1(tx4938_pcic1ptr);
538
539 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
540 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
541 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
542 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
543 printk("%s PCICLK:%dMHz\n",
544 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
545 txx9_gbus_clock /
546 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
547 1000000);
548
549
550 tx4938_pci_controller[1].io_resource->start =
551 io_base[1] - io_base[0];
552 tx4938_pci_controller[1].io_resource->end =
553 io_base[1] - io_base[0] + io_size[1] - 1;
554 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
555 tx4938_pci_controller[1].mem_resource->end =
556 mem_base[1] + mem_size[1] - 1;
557 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
558
559 register_pci_controller(&tx4938_pci_controller[1]);
560
561 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
562
563
564 set_io_port_base(KSEG1 + io_base[0]);
565
566 return 0;
567}
568
569arch_initcall(tx4938_pcibios_init);
570
571#endif
572
573
574
575
576#define SEEPROM1_CS 7
577#define SEEPROM2_CS 0
578#define SEEPROM3_CS 1
579#define SRTC_CS 2
580
581#ifdef CONFIG_PCI
582static int __init rbtx4938_ethaddr_init(void)
583{
584 unsigned char dat[17];
585 unsigned char sum;
586 int i;
587
588
589 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
590 printk(KERN_ERR "seeprom: read error.\n");
591 return -ENODEV;
592 } else {
593 if (strcmp(dat, "MAC") != 0)
594 printk(KERN_WARNING "seeprom: bad signature.\n");
595 for (i = 0, sum = 0; i < sizeof(dat); i++)
596 sum += dat[i];
597 if (sum)
598 printk(KERN_WARNING "seeprom: bad checksum.\n");
599 }
600 for (i = 0; i < 2; i++) {
601 unsigned int id =
602 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
603 struct platform_device *pdev;
604 if (!(tx4938_ccfgptr->pcfg &
605 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
606 continue;
607 pdev = platform_device_alloc("tc35815-mac", id);
608 if (!pdev ||
609 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
610 platform_device_add(pdev))
611 platform_device_put(pdev);
612 }
613 return 0;
614}
615device_initcall(rbtx4938_ethaddr_init);
616#endif
617
618static void __init rbtx4938_spi_setup(void)
619{
620
621 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
622
623 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
624 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
625}
626
627static struct resource rbtx4938_fpga_resource;
628
629static char pcode_str[8];
630static struct resource tx4938_reg_resource = {
631 .start = TX4938_REG_BASE,
632 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
633 .name = pcode_str,
634 .flags = IORESOURCE_MEM
635};
636
637void __init tx4938_board_setup(void)
638{
639 int i;
640 unsigned long divmode;
641 int cpuclk = 0;
642 unsigned long pcode = TX4938_REV_PCODE();
643
644 ioport_resource.start = 0x1000;
645 ioport_resource.end = 0xffffffff;
646 iomem_resource.start = 0x1000;
647 iomem_resource.end = 0xffffffff;
648
649 sprintf(pcode_str, "TX%lx", pcode);
650
651 for (i = 0; i < 8; i++) {
652 if (!(tx4938_ebuscptr->cr[i] & 0x8))
653 continue;
654 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
655 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
656 }
657
658
659 if (txx9_master_clock) {
660
661 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
662 switch (divmode) {
663 case TX4938_CCFG_DIVMODE_8:
664 case TX4938_CCFG_DIVMODE_10:
665 case TX4938_CCFG_DIVMODE_12:
666 case TX4938_CCFG_DIVMODE_16:
667 case TX4938_CCFG_DIVMODE_18:
668 txx9_gbus_clock = txx9_master_clock * 4; break;
669 default:
670 txx9_gbus_clock = txx9_master_clock;
671 }
672 switch (divmode) {
673 case TX4938_CCFG_DIVMODE_2:
674 case TX4938_CCFG_DIVMODE_8:
675 cpuclk = txx9_gbus_clock * 2; break;
676 case TX4938_CCFG_DIVMODE_2_5:
677 case TX4938_CCFG_DIVMODE_10:
678 cpuclk = txx9_gbus_clock * 5 / 2; break;
679 case TX4938_CCFG_DIVMODE_3:
680 case TX4938_CCFG_DIVMODE_12:
681 cpuclk = txx9_gbus_clock * 3; break;
682 case TX4938_CCFG_DIVMODE_4:
683 case TX4938_CCFG_DIVMODE_16:
684 cpuclk = txx9_gbus_clock * 4; break;
685 case TX4938_CCFG_DIVMODE_4_5:
686 case TX4938_CCFG_DIVMODE_18:
687 cpuclk = txx9_gbus_clock * 9 / 2; break;
688 }
689 txx9_cpu_clock = cpuclk;
690 } else {
691 if (txx9_cpu_clock == 0) {
692 txx9_cpu_clock = 300000000;
693 }
694
695 cpuclk = txx9_cpu_clock;
696 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
697 switch (divmode) {
698 case TX4938_CCFG_DIVMODE_2:
699 case TX4938_CCFG_DIVMODE_8:
700 txx9_gbus_clock = cpuclk / 2; break;
701 case TX4938_CCFG_DIVMODE_2_5:
702 case TX4938_CCFG_DIVMODE_10:
703 txx9_gbus_clock = cpuclk * 2 / 5; break;
704 case TX4938_CCFG_DIVMODE_3:
705 case TX4938_CCFG_DIVMODE_12:
706 txx9_gbus_clock = cpuclk / 3; break;
707 case TX4938_CCFG_DIVMODE_4:
708 case TX4938_CCFG_DIVMODE_16:
709 txx9_gbus_clock = cpuclk / 4; break;
710 case TX4938_CCFG_DIVMODE_4_5:
711 case TX4938_CCFG_DIVMODE_18:
712 txx9_gbus_clock = cpuclk * 2 / 9; break;
713 }
714 switch (divmode) {
715 case TX4938_CCFG_DIVMODE_8:
716 case TX4938_CCFG_DIVMODE_10:
717 case TX4938_CCFG_DIVMODE_12:
718 case TX4938_CCFG_DIVMODE_16:
719 case TX4938_CCFG_DIVMODE_18:
720 txx9_master_clock = txx9_gbus_clock / 4; break;
721 default:
722 txx9_master_clock = txx9_gbus_clock;
723 }
724 }
725
726 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
727
728
729
730 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
731
732 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
733 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
734
735
736 if (tx4938_ccfg_toeon)
737 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
738
739
740 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
741
742
743 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
744 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
745
746 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
747 pcode_str,
748 cpuclk / 1000000, txx9_master_clock / 1000000,
749 (unsigned long)tx4938_ccfgptr->crir,
750 tx4938_ccfgptr->ccfg,
751 tx4938_ccfgptr->pcfg);
752
753 printk("%s SDRAMC --", pcode_str);
754 for (i = 0; i < 4; i++) {
755 unsigned long long cr = tx4938_sdramcptr->cr[i];
756 unsigned long ram_base, ram_size;
757 if (!((unsigned long)cr & 0x00000400))
758 continue;
759 ram_base = (unsigned long)(cr >> 49) << 21;
760 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
761 if (ram_base >= 0x20000000)
762 continue;
763 printk(" CR%d:%016Lx", i, cr);
764 txboard_add_phys_region(ram_base, ram_size);
765 }
766 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
767
768
769 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
770 unsigned int size = 0x800;
771 unsigned long base =
772 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
773 txboard_add_phys_region(base, size);
774 }
775
776
777 for (i = 0; i < TX4938_NR_TMR; i++)
778 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
779
780
781 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
782 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
783
784
785 tx4938_pioptr->maskcpu = 0;
786 tx4938_pioptr->maskext = 0;
787
788
789 if (request_resource(&iomem_resource, &tx4938_reg_resource))
790 printk("request resource for internal registers failed\n");
791}
792
793#ifdef CONFIG_PCI
794static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
795{
796 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
797 unsigned long g2pstatus = pcicptr->g2pstatus;
798 unsigned long pcicstatus = pcicptr->pcicstatus;
799 static struct {
800 unsigned long flag;
801 const char *str;
802 } pcistat_tbl[] = {
803 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
804 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
805 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
806 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
807 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
808 { PCI_STATUS_PARITY, "MasterParityError" },
809 }, g2pstat_tbl[] = {
810 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
811 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
812 }, pcicstat_tbl[] = {
813 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
814 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
815 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
816 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
817 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
818 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
819 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
820 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
821 };
822 int i;
823
824 printk("pcistat:%04x(", pcistatus);
825 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
826 if (pcistatus & pcistat_tbl[i].flag)
827 printk("%s ", pcistat_tbl[i].str);
828 printk("), g2pstatus:%08lx(", g2pstatus);
829 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
830 if (g2pstatus & g2pstat_tbl[i].flag)
831 printk("%s ", g2pstat_tbl[i].str);
832 printk("), pcicstatus:%08lx(", pcicstatus);
833 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
834 if (pcicstatus & pcicstat_tbl[i].flag)
835 printk("%s ", pcicstat_tbl[i].str);
836 printk(")\n");
837}
838
839void tx4938_report_pcic_status(void)
840{
841 int i;
842 struct tx4938_pcic_reg *pcicptr;
843 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
844 tx4938_report_pcic_status1(pcicptr);
845}
846
847#endif
848
849void __init plat_time_init(void)
850{
851 mips_hpt_frequency = txx9_cpu_clock / 2;
852 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
853 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
854 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
855 txx9_gbus_clock / 2);
856}
857
858void __init toshiba_rbtx4938_setup(void)
859{
860 unsigned long long pcfg;
861 char *argptr;
862
863 iomem_resource.end = 0xffffffff;
864
865 if (txx9_master_clock == 0)
866 txx9_master_clock = 25000000;
867 tx4938_board_setup();
868
869 TX4938_WR(0xff1ff314, 0x00000000);
870 TX4938_WR(0xff1ff414, 0x00000000);
871
872#ifndef CONFIG_PCI
873 set_io_port_base(RBTX4938_ETHER_BASE);
874#endif
875
876#ifdef CONFIG_SERIAL_TXX9
877 {
878 extern int early_serial_txx9_setup(struct uart_port *port);
879 int i;
880 struct uart_port req;
881 for(i = 0; i < 2; i++) {
882 memset(&req, 0, sizeof(req));
883 req.line = i;
884 req.iotype = UPIO_MEM;
885 req.membase = (char *)(0xff1ff300 + i * 0x100);
886 req.mapbase = 0xff1ff300 + i * 0x100;
887 req.irq = RBTX4938_IRQ_IRC_SIO(i);
888 req.flags |= UPF_BUGGY_UART ;
889 req.uartclk = 50000000;
890 early_serial_txx9_setup(&req);
891 }
892 }
893#ifdef CONFIG_SERIAL_TXX9_CONSOLE
894 argptr = prom_getcmdline();
895 if (strstr(argptr, "console=") == NULL) {
896 strcat(argptr, " console=ttyS0,38400");
897 }
898#endif
899#endif
900
901#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
902 printk("PIOSEL: disabling both ata and nand selection\n");
903 local_irq_disable();
904 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
905#endif
906
907#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
908 printk("PIOSEL: enabling nand selection\n");
909 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
910 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
911#endif
912
913#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
914 printk("PIOSEL: enabling ata selection\n");
915 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
916 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
917#endif
918
919#ifdef CONFIG_IP_PNP
920 argptr = prom_getcmdline();
921 if (strstr(argptr, "ip=") == NULL) {
922 strcat(argptr, " ip=any");
923 }
924#endif
925
926
927#ifdef CONFIG_FB
928 {
929 conswitchp = &dummy_con;
930 }
931#endif
932
933 rbtx4938_spi_setup();
934 pcfg = tx4938_ccfgptr->pcfg;
935
936 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
937 TX4938_PCFG_ATA_SEL) {
938 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
939 }
940 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
941 TX4938_PCFG_NDF_SEL) {
942 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
943 }
944 else {
945 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
946 }
947
948 rbtx4938_fpga_resource.name = "FPGA Registers";
949 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
950 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
951 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
952 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
953 printk("request resource for fpga failed\n");
954
955
956 *rbtx4938_imask_ptr = 0;
957
958 _machine_restart = rbtx4938_machine_restart;
959 _machine_halt = rbtx4938_machine_halt;
960 pm_power_off = rbtx4938_machine_power_off;
961
962 *rbtx4938_led_ptr = 0xff;
963 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
964 printk(" DIPSW:%02x,%02x\n",
965 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
966}
967
968static int __init rbtx4938_ne_init(void)
969{
970 struct resource res[] = {
971 {
972 .start = RBTX4938_RTL_8019_BASE,
973 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
974 .flags = IORESOURCE_IO,
975 }, {
976 .start = RBTX4938_RTL_8019_IRQ,
977 .flags = IORESOURCE_IRQ,
978 }
979 };
980 struct platform_device *dev =
981 platform_device_register_simple("ne", -1,
982 res, ARRAY_SIZE(res));
983 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
984}
985device_initcall(rbtx4938_ne_init);
986
987
988
989static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
990
991static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
992{
993 u8 val;
994 unsigned long flags;
995 gpio -= 16;
996 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
997 val = *rbtx4938_spics_ptr;
998 if (value)
999 val |= 1 << gpio;
1000 else
1001 val &= ~(1 << gpio);
1002 *rbtx4938_spics_ptr = val;
1003 mmiowb();
1004 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1005}
1006
1007static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1008{
1009 rbtx4938_spi_gpio_set(gpio, value);
1010 return 0;
1011}
1012
1013static DEFINE_SPINLOCK(tx4938_gpio_lock);
1014
1015static int tx4938_gpio_get(unsigned gpio)
1016{
1017 return tx4938_pioptr->din & (1 << gpio);
1018}
1019
1020static void tx4938_gpio_set_raw(unsigned gpio, int value)
1021{
1022 u32 val;
1023 val = tx4938_pioptr->dout;
1024 if (value)
1025 val |= 1 << gpio;
1026 else
1027 val &= ~(1 << gpio);
1028 tx4938_pioptr->dout = val;
1029}
1030
1031static void tx4938_gpio_set(unsigned gpio, int value)
1032{
1033 unsigned long flags;
1034 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1035 tx4938_gpio_set_raw(gpio, value);
1036 mmiowb();
1037 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1038}
1039
1040static int tx4938_gpio_dir_in(unsigned gpio)
1041{
1042 spin_lock_irq(&tx4938_gpio_lock);
1043 tx4938_pioptr->dir &= ~(1 << gpio);
1044 mmiowb();
1045 spin_unlock_irq(&tx4938_gpio_lock);
1046 return 0;
1047}
1048
1049static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1050{
1051 spin_lock_irq(&tx4938_gpio_lock);
1052 tx4938_gpio_set_raw(gpio, value);
1053 tx4938_pioptr->dir |= 1 << gpio;
1054 mmiowb();
1055 spin_unlock_irq(&tx4938_gpio_lock);
1056 return 0;
1057}
1058
1059int gpio_direction_input(unsigned gpio)
1060{
1061 if (gpio < 16)
1062 return tx4938_gpio_dir_in(gpio);
1063 return -EINVAL;
1064}
1065
1066int gpio_direction_output(unsigned gpio, int value)
1067{
1068 if (gpio < 16)
1069 return tx4938_gpio_dir_out(gpio, value);
1070 if (gpio < 16 + 3)
1071 return rbtx4938_spi_gpio_dir_out(gpio, value);
1072 return -EINVAL;
1073}
1074
1075int gpio_get_value(unsigned gpio)
1076{
1077 if (gpio < 16)
1078 return tx4938_gpio_get(gpio);
1079 return 0;
1080}
1081
1082void gpio_set_value(unsigned gpio, int value)
1083{
1084 if (gpio < 16)
1085 tx4938_gpio_set(gpio, value);
1086 else
1087 rbtx4938_spi_gpio_set(gpio, value);
1088}
1089
1090
1091
1092static void __init txx9_spi_init(unsigned long base, int irq)
1093{
1094 struct resource res[] = {
1095 {
1096 .start = base,
1097 .end = base + 0x20 - 1,
1098 .flags = IORESOURCE_MEM,
1099 .parent = &tx4938_reg_resource,
1100 }, {
1101 .start = irq,
1102 .flags = IORESOURCE_IRQ,
1103 },
1104 };
1105 platform_device_register_simple("spi_txx9", 0,
1106 res, ARRAY_SIZE(res));
1107}
1108
1109static int __init rbtx4938_spi_init(void)
1110{
1111 struct spi_board_info srtc_info = {
1112 .modalias = "rtc-rs5c348",
1113 .max_speed_hz = 1000000,
1114 .bus_num = 0,
1115 .chip_select = 16 + SRTC_CS,
1116
1117 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1118 };
1119 spi_register_board_info(&srtc_info, 1);
1120 spi_eeprom_register(SEEPROM1_CS);
1121 spi_eeprom_register(16 + SEEPROM2_CS);
1122 spi_eeprom_register(16 + SEEPROM3_CS);
1123 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1124 return 0;
1125}
1126arch_initcall(rbtx4938_spi_init);
1127
1128
1129
1130struct clk *clk_get(struct device *dev, const char *id)
1131{
1132 if (!strcmp(id, "spi-baseclk"))
1133 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1134 return ERR_PTR(-ENOENT);
1135}
1136EXPORT_SYMBOL(clk_get);
1137
1138int clk_enable(struct clk *clk)
1139{
1140 return 0;
1141}
1142EXPORT_SYMBOL(clk_enable);
1143
1144void clk_disable(struct clk *clk)
1145{
1146}
1147EXPORT_SYMBOL(clk_disable);
1148
1149unsigned long clk_get_rate(struct clk *clk)
1150{
1151 return (unsigned long)clk;
1152}
1153EXPORT_SYMBOL(clk_get_rate);
1154
1155void clk_put(struct clk *clk)
1156{
1157}
1158EXPORT_SYMBOL(clk_put);
1159
