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24#include <linux/delay.h>
25#include <linux/pci.h>
26#include <linux/ide.h>
27#include <linux/irq.h>
28#include <linux/fs.h>
29#include <linux/seq_file.h>
30#include <linux/console.h>
31#include <linux/initrd.h>
32#include <linux/root_dev.h>
33#include <linux/platform_device.h>
34#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
35#include <linux/serial.h>
36#include <linux/tty.h>
37#include <linux/serial_core.h>
38#include <linux/serial_8250.h>
39#else
40#include <linux/mv643xx.h>
41#endif
42#include <asm/bootinfo.h>
43#include <asm/machdep.h>
44#include <asm/mv64x60.h>
45#include <asm/todc.h>
46#include <asm/time.h>
47
48#include <platforms/ev64260.h>
49
50#define BOARD_VENDOR "Marvell/Galileo"
51#define BOARD_MACHINE "EV-64260-BP"
52
53static struct mv64x60_handle bh;
54
55#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
56extern void gen550_progress(char *, unsigned short);
57extern void gen550_init(int, struct uart_port *);
58#endif
59
60static const unsigned int cpu_7xx[16] = {
61 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
62};
63static const unsigned int cpu_745x[2][16] = {
64 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 },
65 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 }
66};
67
68
69TODC_ALLOC();
70
71static int
72ev64260_get_bus_speed(void)
73{
74 return 100000000;
75}
76
77static int
78ev64260_get_cpu_speed(void)
79{
80 unsigned long pvr, hid1, pll_ext;
81
82 pvr = PVR_VER(mfspr(SPRN_PVR));
83
84 if (pvr != PVR_VER(PVR_7450)) {
85 hid1 = mfspr(SPRN_HID1) >> 28;
86 return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
87 }
88 else {
89 hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13;
90 pll_ext = 0;
91 return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
92 }
93}
94
95unsigned long __init
96ev64260_find_end_of_memory(void)
97{
98 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
99 MV64x60_TYPE_GT64260A);
100}
101
102
103
104
105
106
107
108static int __init
109ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
110{
111 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
112
113 if (hose->index == 0) {
114 static char pci_irq_table[][4] =
115
116
117
118
119 {
120 {EV64260_PCI_0_IRQ,0,0,0},
121 {EV64260_PCI_0_IRQ,0,0,0},
122 };
123
124 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
125 return PCI_IRQ_TABLE_LOOKUP;
126 }
127 else {
128 static char pci_irq_table[][4] =
129
130
131
132
133 {
134 { EV64260_PCI_1_IRQ,0,0,0},
135 { EV64260_PCI_1_IRQ,0,0,0},
136 };
137
138 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
139 return PCI_IRQ_TABLE_LOOKUP;
140 }
141}
142
143static void __init
144ev64260_setup_peripherals(void)
145{
146 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
147 EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
148 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
149 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
150 EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
151 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
152 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
153 EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
154 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
155 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
156 EV64260_UART_BASE, EV64260_UART_SIZE, 0);
157 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
158 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
159 EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
160 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
161
162 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
163 ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
164
165 mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
166 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
167
168 if (ev64260_get_bus_speed() > 100000000)
169 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
170
171 mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
172 mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
173
174
175
176
177
178 if (bh.type == MV64x60_TYPE_GT64260A ) {
179 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
180 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
181 }
182
183 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9));
184
185
186
187
188
189
190 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
191 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
192 mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
193 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
194
195
196
197
198
199 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
200
201
202
203
204
205
206
207
208
209
210
211 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
212
213
214
215
216
217
218
219 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
220
221#define GPP_EXTERNAL_INTERRUPTS \
222 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
223
224 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
225
226 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
227
228
229 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
230 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
231
232 return;
233}
234
235static void __init
236ev64260_setup_bridge(void)
237{
238 struct mv64x60_setup_info si;
239 int i;
240
241 memset(&si, 0, sizeof(si));
242
243 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
244
245 si.pci_0.enable_bus = 1;
246 si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
247 si.pci_0.pci_io.pci_base_hi = 0;
248 si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
249 si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
250 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
251 si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
252 si.pci_0.pci_mem[0].pci_base_hi = 0;
253 si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
254 si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
255 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
256 si.pci_0.pci_cmd_bits = 0;
257 si.pci_0.latency_timer = 0x8;
258
259 si.pci_1.enable_bus = 1;
260 si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
261 si.pci_1.pci_io.pci_base_hi = 0;
262 si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
263 si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
264 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
265 si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
266 si.pci_1.pci_mem[0].pci_base_hi = 0;
267 si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
268 si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
269 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
270 si.pci_1.pci_cmd_bits = 0;
271 si.pci_1.latency_timer = 0x8;
272
273 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
274 si.cpu_prot_options[i] = 0;
275 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
276 si.pci_0.acc_cntl_options[i] =
277 GT64260_PCI_ACC_CNTL_DREADEN |
278 GT64260_PCI_ACC_CNTL_RDPREFETCH |
279 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
280 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
281 GT64260_PCI_ACC_CNTL_SWAP_NONE |
282 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
283 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
284 si.pci_1.acc_cntl_options[i] =
285 GT64260_PCI_ACC_CNTL_DREADEN |
286 GT64260_PCI_ACC_CNTL_RDPREFETCH |
287 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
288 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
289 GT64260_PCI_ACC_CNTL_SWAP_NONE |
290 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
291 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
292 }
293
294
295 if (mv64x60_init(&bh, &si))
296 printk(KERN_ERR "Bridge initialization failed.\n");
297
298 pci_dram_offset = 0;
299 ppc_md.pci_swizzle = common_swizzle;
300 ppc_md.pci_map_irq = ev64260_map_irq;
301 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
302
303 mv64x60_set_bus(&bh, 0, 0);
304 bh.hose_a->first_busno = 0;
305 bh.hose_a->last_busno = 0xff;
306 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
307
308 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
309 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
310 bh.hose_b->last_busno = 0xff;
311 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
312 bh.hose_b->first_busno);
313
314 return;
315}
316
317#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
318static void __init
319ev64260_early_serial_map(void)
320{
321 struct uart_port port;
322 static char first_time = 1;
323
324 if (first_time) {
325 memset(&port, 0, sizeof(port));
326
327 port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
328 port.irq = EV64260_UART_0_IRQ;
329 port.uartclk = BASE_BAUD * 16;
330 port.regshift = 2;
331 port.iotype = UPIO_MEM;
332 port.flags = STD_COM_FLAGS;
333
334#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
335 gen550_init(0, &port);
336#endif
337
338 if (early_serial_setup(&port) != 0)
339 printk(KERN_WARNING "Early serial init of port 0"
340 "failed\n");
341
342 first_time = 0;
343 }
344
345 return;
346}
347#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
348static void __init
349ev64260_early_serial_map(void)
350{
351}
352#endif
353
354static void __init
355ev64260_setup_arch(void)
356{
357 if (ppc_md.progress)
358 ppc_md.progress("ev64260_setup_arch: enter", 0);
359
360#ifdef CONFIG_BLK_DEV_INITRD
361 if (initrd_start)
362 ROOT_DEV = Root_RAM0;
363 else
364#endif
365#ifdef CONFIG_ROOT_NFS
366 ROOT_DEV = Root_NFS;
367#else
368 ROOT_DEV = Root_SDA2;
369#endif
370
371 if (ppc_md.progress)
372 ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
373
374
375 _set_L2CR(_get_L2CR() | L2CR_L2E);
376 _set_L3CR(_get_L3CR() | L3CR_L3E);
377
378 if (ppc_md.progress)
379 ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
380
381 ev64260_setup_bridge();
382 ev64260_setup_peripherals();
383
384 if (ppc_md.progress)
385 ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
386
387#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
388 ev64260_early_serial_map();
389#endif
390
391 printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc."
392 "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
393
394 if (ppc_md.progress)
395 ppc_md.progress("ev64260_setup_arch: exit", 0);
396
397 return;
398}
399
400
401#if defined(CONFIG_SERIAL_MPSC)
402static void __init
403ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
404{
405 struct mpsc_pdata *pdata;
406
407 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
408
409 pdata->max_idle = 40;
410 pdata->default_baud = EV64260_DEFAULT_BAUD;
411 pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
412 pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
413
414 return;
415}
416
417static int
418ev64260_platform_notify(struct device *dev)
419{
420 static struct {
421 char *bus_id;
422 void ((*rtn)(struct platform_device *pdev));
423 } dev_map[] = {
424 { MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
425 { MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
426 };
427 struct platform_device *pdev;
428 int i;
429
430 if (dev && dev->bus_id)
431 for (i=0; i<ARRAY_SIZE(dev_map); i++)
432 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
433 BUS_ID_SIZE)) {
434
435 pdev = container_of(dev,
436 struct platform_device, dev);
437 dev_map[i].rtn(pdev);
438 }
439
440 return 0;
441}
442#endif
443
444static void
445ev64260_reset_board(void *addr)
446{
447 local_irq_disable();
448
449
450 _set_L2CR(0);
451 _set_L2CR(0x200000);
452
453
454 __asm__ __volatile__
455 ("mfspr 3,1008\n\t"
456 "ori 5,5,0xcc00\n\t"
457 "ori 4,3,0xc00\n\t"
458 "andc 5,3,5\n\t"
459 "sync\n\t"
460 "mtspr 1008,4\n\t"
461 "isync\n\t"
462 "sync\n\t"
463 "mtspr 1008,5\n\t"
464 "isync\n\t"
465 "sync\n\t");
466
467
468 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
469 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
470 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
471 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
472 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
473 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
474 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
475 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
476
477
478 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
479 0xff800000, 8*1024*1024, 0);
480 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
481
482
483 mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
484 (1<<24) | CONFIG_MV64X60_BASE >> 20);
485
486
487
488
489
490
491 __asm__ __volatile__
492 ("mtspr 26, %0\n\t"
493 "li 4,(1<<6)\n\t"
494 "mtspr 27,4\n\t"
495 "rfi\n\t"
496 :: "r" (addr):"r4");
497
498 return;
499}
500
501static void
502ev64260_restart(char *cmd)
503{
504 volatile ulong i = 10000000;
505
506 ev64260_reset_board((void *)0xfff00100);
507
508 while (i-- > 0);
509 panic("restart failed\n");
510}
511
512static void
513ev64260_halt(void)
514{
515 local_irq_disable();
516 while (1);
517
518}
519
520static void
521ev64260_power_off(void)
522{
523 ev64260_halt();
524
525}
526
527static int
528ev64260_show_cpuinfo(struct seq_file *m)
529{
530 uint pvid;
531
532 pvid = mfspr(SPRN_PVR);
533 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
534 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
535 seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
536 seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
537
538 return 0;
539}
540
541
542static void __init
543ev64260_calibrate_decr(void)
544{
545 ulong freq;
546
547 freq = ev64260_get_bus_speed()/4;
548
549 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
550 freq/1000000, freq%1000000);
551
552 tb_ticks_per_jiffy = freq / HZ;
553 tb_to_us = mulhwu_scale_factor(freq, 1000000);
554
555 return;
556}
557
558
559
560
561static __inline__ void
562ev64260_set_bat(void)
563{
564 mb();
565 mtspr(SPRN_DBAT1U, 0xfb0001fe);
566 mtspr(SPRN_DBAT1L, 0xfb00002a);
567 mb();
568
569 return;
570}
571
572#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
573static void __init
574ev64260_map_io(void)
575{
576 io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
577}
578#endif
579
580void __init
581platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
582 unsigned long r6, unsigned long r7)
583{
584#ifdef CONFIG_BLK_DEV_INITRD
585 extern int initrd_below_start_ok;
586
587 initrd_start=initrd_end=0;
588 initrd_below_start_ok=0;
589#endif
590
591 parse_bootinfo(find_bootinfo());
592
593 isa_mem_base = 0;
594 isa_io_base = EV64260_PCI0_IO_CPU_BASE;
595 pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
596
597 loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
598
599 ppc_md.setup_arch = ev64260_setup_arch;
600 ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
601 ppc_md.init_IRQ = gt64260_init_irq;
602 ppc_md.get_irq = gt64260_get_irq;
603
604 ppc_md.restart = ev64260_restart;
605 ppc_md.power_off = ev64260_power_off;
606 ppc_md.halt = ev64260_halt;
607
608 ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
609
610 ppc_md.init = NULL;
611
612 ppc_md.time_init = todc_time_init;
613 ppc_md.set_rtc_time = todc_set_rtc_time;
614 ppc_md.get_rtc_time = todc_get_rtc_time;
615 ppc_md.nvram_read_val = todc_direct_read_val;
616 ppc_md.nvram_write_val = todc_direct_write_val;
617 ppc_md.calibrate_decr = ev64260_calibrate_decr;
618
619 bh.p_base = CONFIG_MV64X60_NEW_BASE;
620
621 ev64260_set_bat();
622
623#ifdef CONFIG_SERIAL_8250
624#if defined(CONFIG_SERIAL_TEXT_DEBUG)
625 ppc_md.setup_io_mappings = ev64260_map_io;
626 ppc_md.progress = gen550_progress;
627#endif
628#if defined(CONFIG_KGDB)
629 ppc_md.setup_io_mappings = ev64260_map_io;
630 ppc_md.early_serial_map = ev64260_early_serial_map;
631#endif
632#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
633#ifdef CONFIG_SERIAL_TEXT_DEBUG
634 ppc_md.setup_io_mappings = ev64260_map_io;
635 ppc_md.progress = mv64x60_mpsc_progress;
636 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
637#endif
638#ifdef CONFIG_KGDB
639 ppc_md.setup_io_mappings = ev64260_map_io;
640 ppc_md.early_serial_map = ev64260_early_serial_map;
641#endif
642
643#endif
644
645#if defined(CONFIG_SERIAL_MPSC)
646 platform_notify = ev64260_platform_notify;
647#endif
648
649 return;
650}
651
