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14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h>
19#include <linux/fs_enet_pd.h>
20#include <asm/mpc85xx.h>
21#include <asm/irq.h>
22#include <asm/ppc_sys.h>
23#include <asm/cpm2.h>
24
25
26
27
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49};
50
51static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
57};
58
59static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
65};
66
67static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
73};
74
75static struct gianfar_platform_data mpc85xx_fec_pdata = {
76 .device_flags = 0,
77};
78
79static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
81};
82
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85};
86
87static struct fs_platform_info mpc85xx_fcc1_pdata = {
88 .fs_no = fsid_fcc1,
89 .cp_page = CPM_CR_FCC1_PAGE,
90 .cp_block = CPM_CR_FCC1_SBLOCK,
91
92 .rx_ring = 32,
93 .tx_ring = 32,
94 .rx_copybreak = 240,
95 .use_napi = 0,
96 .napi_weight = 17,
97
98 .clk_mask = CMX1_CLK_MASK,
99 .clk_route = CMX1_CLK_ROUTE,
100 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
101
102 .mem_offset = FCC1_MEM_OFFSET,
103};
104
105static struct fs_platform_info mpc85xx_fcc2_pdata = {
106 .fs_no = fsid_fcc2,
107 .cp_page = CPM_CR_FCC2_PAGE,
108 .cp_block = CPM_CR_FCC2_SBLOCK,
109
110 .rx_ring = 32,
111 .tx_ring = 32,
112 .rx_copybreak = 240,
113 .use_napi = 0,
114 .napi_weight = 17,
115
116 .clk_mask = CMX2_CLK_MASK,
117 .clk_route = CMX2_CLK_ROUTE,
118 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
119
120 .mem_offset = FCC2_MEM_OFFSET,
121};
122
123static struct fs_platform_info mpc85xx_fcc3_pdata = {
124 .fs_no = fsid_fcc3,
125 .cp_page = CPM_CR_FCC3_PAGE,
126 .cp_block = CPM_CR_FCC3_SBLOCK,
127
128 .rx_ring = 32,
129 .tx_ring = 32,
130 .rx_copybreak = 240,
131 .use_napi = 0,
132 .napi_weight = 17,
133
134 .clk_mask = CMX3_CLK_MASK,
135 .clk_route = CMX3_CLK_ROUTE,
136 .clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
137
138 .mem_offset = FCC3_MEM_OFFSET,
139};
140
141static struct plat_serial8250_port serial_platform_data[] = {
142 [0] = {
143 .mapbase = 0x4500,
144 .irq = MPC85xx_IRQ_DUART,
145 .iotype = UPIO_MEM,
146 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
147 },
148 [1] = {
149 .mapbase = 0x4600,
150 .irq = MPC85xx_IRQ_DUART,
151 .iotype = UPIO_MEM,
152 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
153 },
154 { },
155};
156
157struct platform_device ppc_sys_platform_devices[] = {
158 [MPC85xx_TSEC1] = {
159 .name = "fsl-gianfar",
160 .id = 1,
161 .dev.platform_data = &mpc85xx_tsec1_pdata,
162 .num_resources = 4,
163 .resource = (struct resource[]) {
164 {
165 .start = MPC85xx_ENET1_OFFSET,
166 .end = MPC85xx_ENET1_OFFSET +
167 MPC85xx_ENET1_SIZE - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .name = "tx",
172 .start = MPC85xx_IRQ_TSEC1_TX,
173 .end = MPC85xx_IRQ_TSEC1_TX,
174 .flags = IORESOURCE_IRQ,
175 },
176 {
177 .name = "rx",
178 .start = MPC85xx_IRQ_TSEC1_RX,
179 .end = MPC85xx_IRQ_TSEC1_RX,
180 .flags = IORESOURCE_IRQ,
181 },
182 {
183 .name = "error",
184 .start = MPC85xx_IRQ_TSEC1_ERROR,
185 .end = MPC85xx_IRQ_TSEC1_ERROR,
186 .flags = IORESOURCE_IRQ,
187 },
188 },
189 },
190 [MPC85xx_TSEC2] = {
191 .name = "fsl-gianfar",
192 .id = 2,
193 .dev.platform_data = &mpc85xx_tsec2_pdata,
194 .num_resources = 4,
195 .resource = (struct resource[]) {
196 {
197 .start = MPC85xx_ENET2_OFFSET,
198 .end = MPC85xx_ENET2_OFFSET +
199 MPC85xx_ENET2_SIZE - 1,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .name = "tx",
204 .start = MPC85xx_IRQ_TSEC2_TX,
205 .end = MPC85xx_IRQ_TSEC2_TX,
206 .flags = IORESOURCE_IRQ,
207 },
208 {
209 .name = "rx",
210 .start = MPC85xx_IRQ_TSEC2_RX,
211 .end = MPC85xx_IRQ_TSEC2_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "error",
216 .start = MPC85xx_IRQ_TSEC2_ERROR,
217 .end = MPC85xx_IRQ_TSEC2_ERROR,
218 .flags = IORESOURCE_IRQ,
219 },
220 },
221 },
222 [MPC85xx_FEC] = {
223 .name = "fsl-gianfar",
224 .id = 3,
225 .dev.platform_data = &mpc85xx_fec_pdata,
226 .num_resources = 2,
227 .resource = (struct resource[]) {
228 {
229 .start = MPC85xx_ENET3_OFFSET,
230 .end = MPC85xx_ENET3_OFFSET +
231 MPC85xx_ENET3_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233
234 },
235 {
236 .start = MPC85xx_IRQ_FEC,
237 .end = MPC85xx_IRQ_FEC,
238 .flags = IORESOURCE_IRQ,
239 },
240 },
241 },
242 [MPC85xx_IIC1] = {
243 .name = "fsl-i2c",
244 .id = 1,
245 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
246 .num_resources = 2,
247 .resource = (struct resource[]) {
248 {
249 .start = MPC85xx_IIC1_OFFSET,
250 .end = MPC85xx_IIC1_OFFSET +
251 MPC85xx_IIC1_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 {
255 .start = MPC85xx_IRQ_IIC1,
256 .end = MPC85xx_IRQ_IIC1,
257 .flags = IORESOURCE_IRQ,
258 },
259 },
260 },
261 [MPC85xx_DMA0] = {
262 .name = "fsl-dma",
263 .id = 0,
264 .num_resources = 2,
265 .resource = (struct resource[]) {
266 {
267 .start = MPC85xx_DMA0_OFFSET,
268 .end = MPC85xx_DMA0_OFFSET +
269 MPC85xx_DMA0_SIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = MPC85xx_IRQ_DMA0,
274 .end = MPC85xx_IRQ_DMA0,
275 .flags = IORESOURCE_IRQ,
276 },
277 },
278 },
279 [MPC85xx_DMA1] = {
280 .name = "fsl-dma",
281 .id = 1,
282 .num_resources = 2,
283 .resource = (struct resource[]) {
284 {
285 .start = MPC85xx_DMA1_OFFSET,
286 .end = MPC85xx_DMA1_OFFSET +
287 MPC85xx_DMA1_SIZE - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = MPC85xx_IRQ_DMA1,
292 .end = MPC85xx_IRQ_DMA1,
293 .flags = IORESOURCE_IRQ,
294 },
295 },
296 },
297 [MPC85xx_DMA2] = {
298 .name = "fsl-dma",
299 .id = 2,
300 .num_resources = 2,
301 .resource = (struct resource[]) {
302 {
303 .start = MPC85xx_DMA2_OFFSET,
304 .end = MPC85xx_DMA2_OFFSET +
305 MPC85xx_DMA2_SIZE - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = MPC85xx_IRQ_DMA2,
310 .end = MPC85xx_IRQ_DMA2,
311 .flags = IORESOURCE_IRQ,
312 },
313 },
314 },
315 [MPC85xx_DMA3] = {
316 .name = "fsl-dma",
317 .id = 3,
318 .num_resources = 2,
319 .resource = (struct resource[]) {
320 {
321 .start = MPC85xx_DMA3_OFFSET,
322 .end = MPC85xx_DMA3_OFFSET +
323 MPC85xx_DMA3_SIZE - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 {
327 .start = MPC85xx_IRQ_DMA3,
328 .end = MPC85xx_IRQ_DMA3,
329 .flags = IORESOURCE_IRQ,
330 },
331 },
332 },
333 [MPC85xx_DUART] = {
334 .name = "serial8250",
335 .id = PLAT8250_DEV_PLATFORM,
336 .dev.platform_data = serial_platform_data,
337 },
338 [MPC85xx_PERFMON] = {
339 .name = "fsl-perfmon",
340 .id = 1,
341 .num_resources = 2,
342 .resource = (struct resource[]) {
343 {
344 .start = MPC85xx_PERFMON_OFFSET,
345 .end = MPC85xx_PERFMON_OFFSET +
346 MPC85xx_PERFMON_SIZE - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 {
350 .start = MPC85xx_IRQ_PERFMON,
351 .end = MPC85xx_IRQ_PERFMON,
352 .flags = IORESOURCE_IRQ,
353 },
354 },
355 },
356 [MPC85xx_SEC2] = {
357 .name = "fsl-sec2",
358 .id = 1,
359 .num_resources = 2,
360 .resource = (struct resource[]) {
361 {
362 .start = MPC85xx_SEC2_OFFSET,
363 .end = MPC85xx_SEC2_OFFSET +
364 MPC85xx_SEC2_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = MPC85xx_IRQ_SEC2,
369 .end = MPC85xx_IRQ_SEC2,
370 .flags = IORESOURCE_IRQ,
371 },
372 },
373 },
374 [MPC85xx_CPM_FCC1] = {
375 .name = "fsl-cpm-fcc",
376 .id = 1,
377 .num_resources = 4,
378 .dev.platform_data = &mpc85xx_fcc1_pdata,
379 .resource = (struct resource[]) {
380 {
381 .name = "fcc_regs",
382 .start = 0x91300,
383 .end = 0x9131F,
384 .flags = IORESOURCE_MEM,
385 },
386 {
387 .name = "fcc_regs_c",
388 .start = 0x91380,
389 .end = 0x9139F,
390 .flags = IORESOURCE_MEM,
391 },
392 {
393 .name = "fcc_pram",
394 .start = 0x88400,
395 .end = 0x884ff,
396 .flags = IORESOURCE_MEM,
397 },
398 {
399 .start = SIU_INT_FCC1,
400 .end = SIU_INT_FCC1,
401 .flags = IORESOURCE_IRQ,
402 },
403 },
404 },
405 [MPC85xx_CPM_FCC2] = {
406 .name = "fsl-cpm-fcc",
407 .id = 2,
408 .num_resources = 4,
409 .dev.platform_data = &mpc85xx_fcc2_pdata,
410 .resource = (struct resource[]) {
411 {
412 .name = "fcc_regs",
413 .start = 0x91320,
414 .end = 0x9133F,
415 .flags = IORESOURCE_MEM,
416 },
417 {
418 .name = "fcc_regs_c",
419 .start = 0x913A0,
420 .end = 0x913CF,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "fcc_pram",
425 .start = 0x88500,
426 .end = 0x885ff,
427 .flags = IORESOURCE_MEM,
428 },
429 {
430 .start = SIU_INT_FCC2,
431 .end = SIU_INT_FCC2,
432 .flags = IORESOURCE_IRQ,
433 },
434 },
435 },
436 [MPC85xx_CPM_FCC3] = {
437 .name = "fsl-cpm-fcc",
438 .id = 3,
439 .num_resources = 4,
440 .dev.platform_data = &mpc85xx_fcc3_pdata,
441 .resource = (struct resource[]) {
442 {
443 .name = "fcc_regs",
444 .start = 0x91340,
445 .end = 0x9135F,
446 .flags = IORESOURCE_MEM,
447 },
448 {
449 .name = "fcc_regs_c",
450 .start = 0x913D0,
451 .end = 0x913FF,
452 .flags = IORESOURCE_MEM,
453 },
454 {
455 .name = "fcc_pram",
456 .start = 0x88600,
457 .end = 0x886ff,
458 .flags = IORESOURCE_MEM,
459 },
460 {
461 .start = SIU_INT_FCC3,
462 .end = SIU_INT_FCC3,
463 .flags = IORESOURCE_IRQ,
464 },
465 },
466 },
467 [MPC85xx_CPM_I2C] = {
468 .name = "fsl-cpm-i2c",
469 .id = 1,
470 .num_resources = 2,
471 .resource = (struct resource[]) {
472 {
473 .start = 0x91860,
474 .end = 0x918BF,
475 .flags = IORESOURCE_MEM,
476 },
477 {
478 .start = SIU_INT_I2C,
479 .end = SIU_INT_I2C,
480 .flags = IORESOURCE_IRQ,
481 },
482 },
483 },
484 [MPC85xx_CPM_SCC1] = {
485 .name = "fsl-cpm-scc",
486 .id = 1,
487 .num_resources = 2,
488 .resource = (struct resource[]) {
489 {
490 .start = 0x91A00,
491 .end = 0x91A1F,
492 .flags = IORESOURCE_MEM,
493 },
494 {
495 .start = SIU_INT_SCC1,
496 .end = SIU_INT_SCC1,
497 .flags = IORESOURCE_IRQ,
498 },
499 },
500 },
501 [MPC85xx_CPM_SCC2] = {
502 .name = "fsl-cpm-scc",
503 .id = 2,
504 .num_resources = 2,
505 .resource = (struct resource[]) {
506 {
507 .start = 0x91A20,
508 .end = 0x91A3F,
509 .flags = IORESOURCE_MEM,
510 },
511 {
512 .start = SIU_INT_SCC2,
513 .end = SIU_INT_SCC2,
514 .flags = IORESOURCE_IRQ,
515 },
516 },
517 },
518 [MPC85xx_CPM_SCC3] = {
519 .name = "fsl-cpm-scc",
520 .id = 3,
521 .num_resources = 2,
522 .resource = (struct resource[]) {
523 {
524 .start = 0x91A40,
525 .end = 0x91A5F,
526 .flags = IORESOURCE_MEM,
527 },
528 {
529 .start = SIU_INT_SCC3,
530 .end = SIU_INT_SCC3,
531 .flags = IORESOURCE_IRQ,
532 },
533 },
534 },
535 [MPC85xx_CPM_SCC4] = {
536 .name = "fsl-cpm-scc",
537 .id = 4,
538 .num_resources = 2,
539 .resource = (struct resource[]) {
540 {
541 .start = 0x91A60,
542 .end = 0x91A7F,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 .start = SIU_INT_SCC4,
547 .end = SIU_INT_SCC4,
548 .flags = IORESOURCE_IRQ,
549 },
550 },
551 },
552 [MPC85xx_CPM_SPI] = {
553 .name = "fsl-cpm-spi",
554 .id = 1,
555 .num_resources = 2,
556 .resource = (struct resource[]) {
557 {
558 .start = 0x91AA0,
559 .end = 0x91AFF,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 .start = SIU_INT_SPI,
564 .end = SIU_INT_SPI,
565 .flags = IORESOURCE_IRQ,
566 },
567 },
568 },
569 [MPC85xx_CPM_MCC1] = {
570 .name = "fsl-cpm-mcc",
571 .id = 1,
572 .num_resources = 2,
573 .resource = (struct resource[]) {
574 {
575 .start = 0x91B30,
576 .end = 0x91B3F,
577 .flags = IORESOURCE_MEM,
578 },
579 {
580 .start = SIU_INT_MCC1,
581 .end = SIU_INT_MCC1,
582 .flags = IORESOURCE_IRQ,
583 },
584 },
585 },
586 [MPC85xx_CPM_MCC2] = {
587 .name = "fsl-cpm-mcc",
588 .id = 2,
589 .num_resources = 2,
590 .resource = (struct resource[]) {
591 {
592 .start = 0x91B50,
593 .end = 0x91B5F,
594 .flags = IORESOURCE_MEM,
595 },
596 {
597 .start = SIU_INT_MCC2,
598 .end = SIU_INT_MCC2,
599 .flags = IORESOURCE_IRQ,
600 },
601 },
602 },
603 [MPC85xx_CPM_SMC1] = {
604 .name = "fsl-cpm-smc",
605 .id = 1,
606 .num_resources = 2,
607 .resource = (struct resource[]) {
608 {
609 .start = 0x91A80,
610 .end = 0x91A8F,
611 .flags = IORESOURCE_MEM,
612 },
613 {
614 .start = SIU_INT_SMC1,
615 .end = SIU_INT_SMC1,
616 .flags = IORESOURCE_IRQ,
617 },
618 },
619 },
620 [MPC85xx_CPM_SMC2] = {
621 .name = "fsl-cpm-smc",
622 .id = 2,
623 .num_resources = 2,
624 .resource = (struct resource[]) {
625 {
626 .start = 0x91A90,
627 .end = 0x91A9F,
628 .flags = IORESOURCE_MEM,
629 },
630 {
631 .start = SIU_INT_SMC2,
632 .end = SIU_INT_SMC2,
633 .flags = IORESOURCE_IRQ,
634 },
635 },
636 },
637 [MPC85xx_CPM_USB] = {
638 .name = "fsl-cpm-usb",
639 .id = 2,
640 .num_resources = 2,
641 .resource = (struct resource[]) {
642 {
643 .start = 0x91B60,
644 .end = 0x91B7F,
645 .flags = IORESOURCE_MEM,
646 },
647 {
648 .start = SIU_INT_USB,
649 .end = SIU_INT_USB,
650 .flags = IORESOURCE_IRQ,
651 },
652 },
653 },
654 [MPC85xx_eTSEC1] = {
655 .name = "fsl-gianfar",
656 .id = 1,
657 .dev.platform_data = &mpc85xx_etsec1_pdata,
658 .num_resources = 4,
659 .resource = (struct resource[]) {
660 {
661 .start = MPC85xx_ENET1_OFFSET,
662 .end = MPC85xx_ENET1_OFFSET +
663 MPC85xx_ENET1_SIZE - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 {
667 .name = "tx",
668 .start = MPC85xx_IRQ_TSEC1_TX,
669 .end = MPC85xx_IRQ_TSEC1_TX,
670 .flags = IORESOURCE_IRQ,
671 },
672 {
673 .name = "rx",
674 .start = MPC85xx_IRQ_TSEC1_RX,
675 .end = MPC85xx_IRQ_TSEC1_RX,
676 .flags = IORESOURCE_IRQ,
677 },
678 {
679 .name = "error",
680 .start = MPC85xx_IRQ_TSEC1_ERROR,
681 .end = MPC85xx_IRQ_TSEC1_ERROR,
682 .flags = IORESOURCE_IRQ,
683 },
684 },
685 },
686 [MPC85xx_eTSEC2] = {
687 .name = "fsl-gianfar",
688 .id = 2,
689 .dev.platform_data = &mpc85xx_etsec2_pdata,
690 .num_resources = 4,
691 .resource = (struct resource[]) {
692 {
693 .start = MPC85xx_ENET2_OFFSET,
694 .end = MPC85xx_ENET2_OFFSET +
695 MPC85xx_ENET2_SIZE - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 {
699 .name = "tx",
700 .start = MPC85xx_IRQ_TSEC2_TX,
701 .end = MPC85xx_IRQ_TSEC2_TX,
702 .flags = IORESOURCE_IRQ,
703 },
704 {
705 .name = "rx",
706 .start = MPC85xx_IRQ_TSEC2_RX,
707 .end = MPC85xx_IRQ_TSEC2_RX,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .name = "error",
712 .start = MPC85xx_IRQ_TSEC2_ERROR,
713 .end = MPC85xx_IRQ_TSEC2_ERROR,
714 .flags = IORESOURCE_IRQ,
715 },
716 },
717 },
718 [MPC85xx_eTSEC3] = {
719 .name = "fsl-gianfar",
720 .id = 3,
721 .dev.platform_data = &mpc85xx_etsec3_pdata,
722 .num_resources = 4,
723 .resource = (struct resource[]) {
724 {
725 .start = MPC85xx_ENET3_OFFSET,
726 .end = MPC85xx_ENET3_OFFSET +
727 MPC85xx_ENET3_SIZE - 1,
728 .flags = IORESOURCE_MEM,
729 },
730 {
731 .name = "tx",
732 .start = MPC85xx_IRQ_TSEC3_TX,
733 .end = MPC85xx_IRQ_TSEC3_TX,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .name = "rx",
738 .start = MPC85xx_IRQ_TSEC3_RX,
739 .end = MPC85xx_IRQ_TSEC3_RX,
740 .flags = IORESOURCE_IRQ,
741 },
742 {
743 .name = "error",
744 .start = MPC85xx_IRQ_TSEC3_ERROR,
745 .end = MPC85xx_IRQ_TSEC3_ERROR,
746 .flags = IORESOURCE_IRQ,
747 },
748 },
749 },
750 [MPC85xx_eTSEC4] = {
751 .name = "fsl-gianfar",
752 .id = 4,
753 .dev.platform_data = &mpc85xx_etsec4_pdata,
754 .num_resources = 4,
755 .resource = (struct resource[]) {
756 {
757 .start = 0x27000,
758 .end = 0x27fff,
759 .flags = IORESOURCE_MEM,
760 },
761 {
762 .name = "tx",
763 .start = MPC85xx_IRQ_TSEC4_TX,
764 .end = MPC85xx_IRQ_TSEC4_TX,
765 .flags = IORESOURCE_IRQ,
766 },
767 {
768 .name = "rx",
769 .start = MPC85xx_IRQ_TSEC4_RX,
770 .end = MPC85xx_IRQ_TSEC4_RX,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .name = "error",
775 .start = MPC85xx_IRQ_TSEC4_ERROR,
776 .end = MPC85xx_IRQ_TSEC4_ERROR,
777 .flags = IORESOURCE_IRQ,
778 },
779 },
780 },
781 [MPC85xx_IIC2] = {
782 .name = "fsl-i2c",
783 .id = 2,
784 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
785 .num_resources = 2,
786 .resource = (struct resource[]) {
787 {
788 .start = 0x03100,
789 .end = 0x031ff,
790 .flags = IORESOURCE_MEM,
791 },
792 {
793 .start = MPC85xx_IRQ_IIC1,
794 .end = MPC85xx_IRQ_IIC1,
795 .flags = IORESOURCE_IRQ,
796 },
797 },
798 },
799 [MPC85xx_MDIO] = {
800 .name = "fsl-gianfar_mdio",
801 .id = 0,
802 .dev.platform_data = &mpc85xx_mdio_pdata,
803 .num_resources = 1,
804 .resource = (struct resource[]) {
805 {
806 .start = 0x24520,
807 .end = 0x2453f,
808 .flags = IORESOURCE_MEM,
809 },
810 },
811 },
812};
813
814static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
815{
816 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
817 return 0;
818}
819
820static int __init mach_mpc85xx_init(void)
821{
822 ppc_sys_device_fixup = mach_mpc85xx_fixup;
823 return 0;
824}
825
826postcore_initcall(mach_mpc85xx_init);
827
