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12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/string.h>
18#include <linux/mv643xx.h>
19
20#include <asm/byteorder.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/uaccess.h>
24#include <asm/machdep.h>
25#include <asm/pci-bridge.h>
26#include <asm/delay.h>
27#include <asm/mv64x60.h>
28
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31
32
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34
35
36
37struct mv64x60_32bit_window
38 gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = {
39
40 [MV64x60_CPU2MEM_0_WIN] = {
41 .base_reg = MV64x60_CPU2MEM_0_BASE,
42 .size_reg = MV64x60_CPU2MEM_0_SIZE,
43 .base_bits = 12,
44 .size_bits = 12,
45 .get_from_field = mv64x60_shift_left,
46 .map_to_field = mv64x60_shift_right,
47 .extra = 0 },
48 [MV64x60_CPU2MEM_1_WIN] = {
49 .base_reg = MV64x60_CPU2MEM_1_BASE,
50 .size_reg = MV64x60_CPU2MEM_1_SIZE,
51 .base_bits = 12,
52 .size_bits = 12,
53 .get_from_field = mv64x60_shift_left,
54 .map_to_field = mv64x60_shift_right,
55 .extra = 0 },
56 [MV64x60_CPU2MEM_2_WIN] = {
57 .base_reg = MV64x60_CPU2MEM_2_BASE,
58 .size_reg = MV64x60_CPU2MEM_2_SIZE,
59 .base_bits = 12,
60 .size_bits = 12,
61 .get_from_field = mv64x60_shift_left,
62 .map_to_field = mv64x60_shift_right,
63 .extra = 0 },
64 [MV64x60_CPU2MEM_3_WIN] = {
65 .base_reg = MV64x60_CPU2MEM_3_BASE,
66 .size_reg = MV64x60_CPU2MEM_3_SIZE,
67 .base_bits = 12,
68 .size_bits = 12,
69 .get_from_field = mv64x60_shift_left,
70 .map_to_field = mv64x60_shift_right,
71 .extra = 0 },
72
73 [MV64x60_CPU2DEV_0_WIN] = {
74 .base_reg = MV64x60_CPU2DEV_0_BASE,
75 .size_reg = MV64x60_CPU2DEV_0_SIZE,
76 .base_bits = 12,
77 .size_bits = 12,
78 .get_from_field = mv64x60_shift_left,
79 .map_to_field = mv64x60_shift_right,
80 .extra = 0 },
81 [MV64x60_CPU2DEV_1_WIN] = {
82 .base_reg = MV64x60_CPU2DEV_1_BASE,
83 .size_reg = MV64x60_CPU2DEV_1_SIZE,
84 .base_bits = 12,
85 .size_bits = 12,
86 .get_from_field = mv64x60_shift_left,
87 .map_to_field = mv64x60_shift_right,
88 .extra = 0 },
89 [MV64x60_CPU2DEV_2_WIN] = {
90 .base_reg = MV64x60_CPU2DEV_2_BASE,
91 .size_reg = MV64x60_CPU2DEV_2_SIZE,
92 .base_bits = 12,
93 .size_bits = 12,
94 .get_from_field = mv64x60_shift_left,
95 .map_to_field = mv64x60_shift_right,
96 .extra = 0 },
97 [MV64x60_CPU2DEV_3_WIN] = {
98 .base_reg = MV64x60_CPU2DEV_3_BASE,
99 .size_reg = MV64x60_CPU2DEV_3_SIZE,
100 .base_bits = 12,
101 .size_bits = 12,
102 .get_from_field = mv64x60_shift_left,
103 .map_to_field = mv64x60_shift_right,
104 .extra = 0 },
105
106 [MV64x60_CPU2BOOT_WIN] = {
107 .base_reg = MV64x60_CPU2BOOT_0_BASE,
108 .size_reg = MV64x60_CPU2BOOT_0_SIZE,
109 .base_bits = 12,
110 .size_bits = 12,
111 .get_from_field = mv64x60_shift_left,
112 .map_to_field = mv64x60_shift_right,
113 .extra = 0 },
114
115 [MV64x60_CPU2PCI0_IO_WIN] = {
116 .base_reg = MV64x60_CPU2PCI0_IO_BASE,
117 .size_reg = MV64x60_CPU2PCI0_IO_SIZE,
118 .base_bits = 12,
119 .size_bits = 12,
120 .get_from_field = mv64x60_shift_left,
121 .map_to_field = mv64x60_shift_right,
122 .extra = 0 },
123 [MV64x60_CPU2PCI0_MEM_0_WIN] = {
124 .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE,
125 .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE,
126 .base_bits = 12,
127 .size_bits = 12,
128 .get_from_field = mv64x60_shift_left,
129 .map_to_field = mv64x60_shift_right,
130 .extra = 0 },
131 [MV64x60_CPU2PCI0_MEM_1_WIN] = {
132 .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE,
133 .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE,
134 .base_bits = 12,
135 .size_bits = 12,
136 .get_from_field = mv64x60_shift_left,
137 .map_to_field = mv64x60_shift_right,
138 .extra = 0 },
139 [MV64x60_CPU2PCI0_MEM_2_WIN] = {
140 .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE,
141 .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE,
142 .base_bits = 12,
143 .size_bits = 12,
144 .get_from_field = mv64x60_shift_left,
145 .map_to_field = mv64x60_shift_right,
146 .extra = 0 },
147 [MV64x60_CPU2PCI0_MEM_3_WIN] = {
148 .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE,
149 .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE,
150 .base_bits = 12,
151 .size_bits = 12,
152 .get_from_field = mv64x60_shift_left,
153 .map_to_field = mv64x60_shift_right,
154 .extra = 0 },
155
156 [MV64x60_CPU2PCI1_IO_WIN] = {
157 .base_reg = MV64x60_CPU2PCI1_IO_BASE,
158 .size_reg = MV64x60_CPU2PCI1_IO_SIZE,
159 .base_bits = 12,
160 .size_bits = 12,
161 .get_from_field = mv64x60_shift_left,
162 .map_to_field = mv64x60_shift_right,
163 .extra = 0 },
164 [MV64x60_CPU2PCI1_MEM_0_WIN] = {
165 .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE,
166 .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE,
167 .base_bits = 12,
168 .size_bits = 12,
169 .get_from_field = mv64x60_shift_left,
170 .map_to_field = mv64x60_shift_right,
171 .extra = 0 },
172 [MV64x60_CPU2PCI1_MEM_1_WIN] = {
173 .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE,
174 .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE,
175 .base_bits = 12,
176 .size_bits = 12,
177 .get_from_field = mv64x60_shift_left,
178 .map_to_field = mv64x60_shift_right,
179 .extra = 0 },
180 [MV64x60_CPU2PCI1_MEM_2_WIN] = {
181 .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE,
182 .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE,
183 .base_bits = 12,
184 .size_bits = 12,
185 .get_from_field = mv64x60_shift_left,
186 .map_to_field = mv64x60_shift_right,
187 .extra = 0 },
188 [MV64x60_CPU2PCI1_MEM_3_WIN] = {
189 .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE,
190 .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE,
191 .base_bits = 12,
192 .size_bits = 12,
193 .get_from_field = mv64x60_shift_left,
194 .map_to_field = mv64x60_shift_right,
195 .extra = 0 },
196
197
198 [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
199 .base_reg = MV64x60_CPU2PCI0_IO_REMAP,
200 .size_reg = 0,
201 .base_bits = 12,
202 .size_bits = 0,
203 .get_from_field = mv64x60_shift_left,
204 .map_to_field = mv64x60_shift_right,
205 .extra = 0 },
206
207 [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
208 .base_reg = MV64x60_CPU2PCI1_IO_REMAP,
209 .size_reg = 0,
210 .base_bits = 12,
211 .size_bits = 0,
212 .get_from_field = mv64x60_shift_left,
213 .map_to_field = mv64x60_shift_right,
214 .extra = 0 },
215
216 [MV64x60_CPU_PROT_0_WIN] = {
217 .base_reg = MV64x60_CPU_PROT_BASE_0,
218 .size_reg = MV64x60_CPU_PROT_SIZE_0,
219 .base_bits = 12,
220 .size_bits = 12,
221 .get_from_field = mv64x60_shift_left,
222 .map_to_field = mv64x60_shift_right,
223 .extra = 0 },
224 [MV64x60_CPU_PROT_1_WIN] = {
225 .base_reg = MV64x60_CPU_PROT_BASE_1,
226 .size_reg = MV64x60_CPU_PROT_SIZE_1,
227 .base_bits = 12,
228 .size_bits = 12,
229 .get_from_field = mv64x60_shift_left,
230 .map_to_field = mv64x60_shift_right,
231 .extra = 0 },
232 [MV64x60_CPU_PROT_2_WIN] = {
233 .base_reg = MV64x60_CPU_PROT_BASE_2,
234 .size_reg = MV64x60_CPU_PROT_SIZE_2,
235 .base_bits = 12,
236 .size_bits = 12,
237 .get_from_field = mv64x60_shift_left,
238 .map_to_field = mv64x60_shift_right,
239 .extra = 0 },
240 [MV64x60_CPU_PROT_3_WIN] = {
241 .base_reg = MV64x60_CPU_PROT_BASE_3,
242 .size_reg = MV64x60_CPU_PROT_SIZE_3,
243 .base_bits = 12,
244 .size_bits = 12,
245 .get_from_field = mv64x60_shift_left,
246 .map_to_field = mv64x60_shift_right,
247 .extra = 0 },
248
249 [MV64x60_CPU_SNOOP_0_WIN] = {
250 .base_reg = GT64260_CPU_SNOOP_BASE_0,
251 .size_reg = GT64260_CPU_SNOOP_SIZE_0,
252 .base_bits = 12,
253 .size_bits = 12,
254 .get_from_field = mv64x60_shift_left,
255 .map_to_field = mv64x60_shift_right,
256 .extra = 0 },
257 [MV64x60_CPU_SNOOP_1_WIN] = {
258 .base_reg = GT64260_CPU_SNOOP_BASE_1,
259 .size_reg = GT64260_CPU_SNOOP_SIZE_1,
260 .base_bits = 12,
261 .size_bits = 12,
262 .get_from_field = mv64x60_shift_left,
263 .map_to_field = mv64x60_shift_right,
264 .extra = 0 },
265 [MV64x60_CPU_SNOOP_2_WIN] = {
266 .base_reg = GT64260_CPU_SNOOP_BASE_2,
267 .size_reg = GT64260_CPU_SNOOP_SIZE_2,
268 .base_bits = 12,
269 .size_bits = 12,
270 .get_from_field = mv64x60_shift_left,
271 .map_to_field = mv64x60_shift_right,
272 .extra = 0 },
273 [MV64x60_CPU_SNOOP_3_WIN] = {
274 .base_reg = GT64260_CPU_SNOOP_BASE_3,
275 .size_reg = GT64260_CPU_SNOOP_SIZE_3,
276 .base_bits = 12,
277 .size_bits = 12,
278 .get_from_field = mv64x60_shift_left,
279 .map_to_field = mv64x60_shift_right,
280 .extra = 0 },
281
282 [MV64x60_PCI02MEM_REMAP_0_WIN] = {
283 .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
284 .size_reg = 0,
285 .base_bits = 20,
286 .size_bits = 0,
287 .get_from_field = mv64x60_mask,
288 .map_to_field = mv64x60_mask,
289 .extra = 0 },
290 [MV64x60_PCI02MEM_REMAP_1_WIN] = {
291 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
292 .size_reg = 0,
293 .base_bits = 20,
294 .size_bits = 0,
295 .get_from_field = mv64x60_mask,
296 .map_to_field = mv64x60_mask,
297 .extra = 0 },
298 [MV64x60_PCI02MEM_REMAP_2_WIN] = {
299 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
300 .size_reg = 0,
301 .base_bits = 20,
302 .size_bits = 0,
303 .get_from_field = mv64x60_mask,
304 .map_to_field = mv64x60_mask,
305 .extra = 0 },
306 [MV64x60_PCI02MEM_REMAP_3_WIN] = {
307 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
308 .size_reg = 0,
309 .base_bits = 20,
310 .size_bits = 0,
311 .get_from_field = mv64x60_mask,
312 .map_to_field = mv64x60_mask,
313 .extra = 0 },
314
315 [MV64x60_PCI12MEM_REMAP_0_WIN] = {
316 .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
317 .size_reg = 0,
318 .base_bits = 20,
319 .size_bits = 0,
320 .get_from_field = mv64x60_mask,
321 .map_to_field = mv64x60_mask,
322 .extra = 0 },
323 [MV64x60_PCI12MEM_REMAP_1_WIN] = {
324 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
325 .size_reg = 0,
326 .base_bits = 20,
327 .size_bits = 0,
328 .get_from_field = mv64x60_mask,
329 .map_to_field = mv64x60_mask,
330 .extra = 0 },
331 [MV64x60_PCI12MEM_REMAP_2_WIN] = {
332 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
333 .size_reg = 0,
334 .base_bits = 20,
335 .size_bits = 0,
336 .get_from_field = mv64x60_mask,
337 .map_to_field = mv64x60_mask,
338 .extra = 0 },
339 [MV64x60_PCI12MEM_REMAP_3_WIN] = {
340 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
341 .size_reg = 0,
342 .base_bits = 20,
343 .size_bits = 0,
344 .get_from_field = mv64x60_mask,
345 .map_to_field = mv64x60_mask,
346 .extra = 0 },
347
348
349
350};
351
352struct mv64x60_64bit_window
353 gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = {
354
355 [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
356 .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
357 .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
358 .size_reg = 0,
359 .base_lo_bits = 12,
360 .size_bits = 0,
361 .get_from_field = mv64x60_shift_left,
362 .map_to_field = mv64x60_shift_right,
363 .extra = 0 },
364 [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
365 .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
366 .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
367 .size_reg = 0,
368 .base_lo_bits = 12,
369 .size_bits = 0,
370 .get_from_field = mv64x60_shift_left,
371 .map_to_field = mv64x60_shift_right,
372 .extra = 0 },
373 [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
374 .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
375 .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
376 .size_reg = 0,
377 .base_lo_bits = 12,
378 .size_bits = 0,
379 .get_from_field = mv64x60_shift_left,
380 .map_to_field = mv64x60_shift_right,
381 .extra = 0 },
382 [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
383 .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
384 .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
385 .size_reg = 0,
386 .base_lo_bits = 12,
387 .size_bits = 0,
388 .get_from_field = mv64x60_shift_left,
389 .map_to_field = mv64x60_shift_right,
390 .extra = 0 },
391
392 [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
393 .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
394 .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
395 .size_reg = 0,
396 .base_lo_bits = 12,
397 .size_bits = 0,
398 .get_from_field = mv64x60_shift_left,
399 .map_to_field = mv64x60_shift_right,
400 .extra = 0 },
401 [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
402 .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
403 .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
404 .size_reg = 0,
405 .base_lo_bits = 12,
406 .size_bits = 0,
407 .get_from_field = mv64x60_shift_left,
408 .map_to_field = mv64x60_shift_right,
409 .extra = 0 },
410 [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
411 .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
412 .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
413 .size_reg = 0,
414 .base_lo_bits = 12,
415 .size_bits = 0,
416 .get_from_field = mv64x60_shift_left,
417 .map_to_field = mv64x60_shift_right,
418 .extra = 0 },
419 [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
420 .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
421 .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
422 .size_reg = 0,
423 .base_lo_bits = 12,
424 .size_bits = 0,
425 .get_from_field = mv64x60_shift_left,
426 .map_to_field = mv64x60_shift_right,
427 .extra = 0 },
428
429 [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
430 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
431 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
432 .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE,
433 .base_lo_bits = 12,
434 .size_bits = 12,
435 .get_from_field = mv64x60_shift_left,
436 .map_to_field = mv64x60_shift_right,
437 .extra = 0 },
438 [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
439 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
440 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
441 .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE,
442 .base_lo_bits = 12,
443 .size_bits = 12,
444 .get_from_field = mv64x60_shift_left,
445 .map_to_field = mv64x60_shift_right,
446 .extra = 0 },
447 [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
448 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
449 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
450 .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE,
451 .base_lo_bits = 12,
452 .size_bits = 12,
453 .get_from_field = mv64x60_shift_left,
454 .map_to_field = mv64x60_shift_right,
455 .extra = 0 },
456 [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
457 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
458 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
459 .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE,
460 .base_lo_bits = 12,
461 .size_bits = 12,
462 .get_from_field = mv64x60_shift_left,
463 .map_to_field = mv64x60_shift_right,
464 .extra = 0 },
465
466 [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
467 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
468 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
469 .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE,
470 .base_lo_bits = 12,
471 .size_bits = 12,
472 .get_from_field = mv64x60_shift_left,
473 .map_to_field = mv64x60_shift_right,
474 .extra = 0 },
475 [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
476 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
477 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
478 .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE,
479 .base_lo_bits = 12,
480 .size_bits = 12,
481 .get_from_field = mv64x60_shift_left,
482 .map_to_field = mv64x60_shift_right,
483 .extra = 0 },
484 [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
485 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
486 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
487 .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE,
488 .base_lo_bits = 12,
489 .size_bits = 12,
490 .get_from_field = mv64x60_shift_left,
491 .map_to_field = mv64x60_shift_right,
492 .extra = 0 },
493 [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
494 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
495 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
496 .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE,
497 .base_lo_bits = 12,
498 .size_bits = 12,
499 .get_from_field = mv64x60_shift_left,
500 .map_to_field = mv64x60_shift_right,
501 .extra = 0 },
502
503 [MV64x60_PCI02MEM_SNOOP_0_WIN] = {
504 .base_hi_reg = GT64260_PCI0_SNOOP_0_BASE_HI,
505 .base_lo_reg = GT64260_PCI0_SNOOP_0_BASE_LO,
506 .size_reg = GT64260_PCI0_SNOOP_0_SIZE,
507 .base_lo_bits = 12,
508 .size_bits = 12,
509 .get_from_field = mv64x60_shift_left,
510 .map_to_field = mv64x60_shift_right,
511 .extra = 0 },
512 [MV64x60_PCI02MEM_SNOOP_1_WIN] = {
513 .base_hi_reg = GT64260_PCI0_SNOOP_1_BASE_HI,
514 .base_lo_reg = GT64260_PCI0_SNOOP_1_BASE_LO,
515 .size_reg = GT64260_PCI0_SNOOP_1_SIZE,
516 .base_lo_bits = 12,
517 .size_bits = 12,
518 .get_from_field = mv64x60_shift_left,
519 .map_to_field = mv64x60_shift_right,
520 .extra = 0 },
521 [MV64x60_PCI02MEM_SNOOP_2_WIN] = {
522 .base_hi_reg = GT64260_PCI0_SNOOP_2_BASE_HI,
523 .base_lo_reg = GT64260_PCI0_SNOOP_2_BASE_LO,
524 .size_reg = GT64260_PCI0_SNOOP_2_SIZE,
525 .base_lo_bits = 12,
526 .size_bits = 12,
527 .get_from_field = mv64x60_shift_left,
528 .map_to_field = mv64x60_shift_right,
529 .extra = 0 },
530 [MV64x60_PCI02MEM_SNOOP_3_WIN] = {
531 .base_hi_reg = GT64260_PCI0_SNOOP_3_BASE_HI,
532 .base_lo_reg = GT64260_PCI0_SNOOP_3_BASE_LO,
533 .size_reg = GT64260_PCI0_SNOOP_3_SIZE,
534 .base_lo_bits = 12,
535 .size_bits = 12,
536 .get_from_field = mv64x60_shift_left,
537 .map_to_field = mv64x60_shift_right,
538 .extra = 0 },
539
540 [MV64x60_PCI12MEM_SNOOP_0_WIN] = {
541 .base_hi_reg = GT64260_PCI1_SNOOP_0_BASE_HI,
542 .base_lo_reg = GT64260_PCI1_SNOOP_0_BASE_LO,
543 .size_reg = GT64260_PCI1_SNOOP_0_SIZE,
544 .base_lo_bits = 12,
545 .size_bits = 12,
546 .get_from_field = mv64x60_shift_left,
547 .map_to_field = mv64x60_shift_right,
548 .extra = 0 },
549 [MV64x60_PCI12MEM_SNOOP_1_WIN] = {
550 .base_hi_reg = GT64260_PCI1_SNOOP_1_BASE_HI,
551 .base_lo_reg = GT64260_PCI1_SNOOP_1_BASE_LO,
552 .size_reg = GT64260_PCI1_SNOOP_1_SIZE,
553 .base_lo_bits = 12,
554 .size_bits = 12,
555 .get_from_field = mv64x60_shift_left,
556 .map_to_field = mv64x60_shift_right,
557 .extra = 0 },
558 [MV64x60_PCI12MEM_SNOOP_2_WIN] = {
559 .base_hi_reg = GT64260_PCI1_SNOOP_2_BASE_HI,
560 .base_lo_reg = GT64260_PCI1_SNOOP_2_BASE_LO,
561 .size_reg = GT64260_PCI1_SNOOP_2_SIZE,
562 .base_lo_bits = 12,
563 .size_bits = 12,
564 .get_from_field = mv64x60_shift_left,
565 .map_to_field = mv64x60_shift_right,
566 .extra = 0 },
567 [MV64x60_PCI12MEM_SNOOP_3_WIN] = {
568 .base_hi_reg = GT64260_PCI1_SNOOP_3_BASE_HI,
569 .base_lo_reg = GT64260_PCI1_SNOOP_3_BASE_LO,
570 .size_reg = GT64260_PCI1_SNOOP_3_SIZE,
571 .base_lo_bits = 12,
572 .size_bits = 12,
573 .get_from_field = mv64x60_shift_left,
574 .map_to_field = mv64x60_shift_right,
575 .extra = 0 },
576};
577
578struct mv64x60_32bit_window
579 mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = {
580
581 [MV64x60_CPU2MEM_0_WIN] = {
582 .base_reg = MV64x60_CPU2MEM_0_BASE,
583 .size_reg = MV64x60_CPU2MEM_0_SIZE,
584 .base_bits = 16,
585 .size_bits = 16,
586 .get_from_field = mv64x60_shift_left,
587 .map_to_field = mv64x60_shift_right,
588 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 0 },
589 [MV64x60_CPU2MEM_1_WIN] = {
590 .base_reg = MV64x60_CPU2MEM_1_BASE,
591 .size_reg = MV64x60_CPU2MEM_1_SIZE,
592 .base_bits = 16,
593 .size_bits = 16,
594 .get_from_field = mv64x60_shift_left,
595 .map_to_field = mv64x60_shift_right,
596 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 1 },
597 [MV64x60_CPU2MEM_2_WIN] = {
598 .base_reg = MV64x60_CPU2MEM_2_BASE,
599 .size_reg = MV64x60_CPU2MEM_2_SIZE,
600 .base_bits = 16,
601 .size_bits = 16,
602 .get_from_field = mv64x60_shift_left,
603 .map_to_field = mv64x60_shift_right,
604 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 2 },
605 [MV64x60_CPU2MEM_3_WIN] = {
606 .base_reg = MV64x60_CPU2MEM_3_BASE,
607 .size_reg = MV64x60_CPU2MEM_3_SIZE,
608 .base_bits = 16,
609 .size_bits = 16,
610 .get_from_field = mv64x60_shift_left,
611 .map_to_field = mv64x60_shift_right,
612 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 3 },
613
614 [MV64x60_CPU2DEV_0_WIN] = {
615 .base_reg = MV64x60_CPU2DEV_0_BASE,
616 .size_reg = MV64x60_CPU2DEV_0_SIZE,
617 .base_bits = 16,
618 .size_bits = 16,
619 .get_from_field = mv64x60_shift_left,
620 .map_to_field = mv64x60_shift_right,
621 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 4 },
622 [MV64x60_CPU2DEV_1_WIN] = {
623 .base_reg = MV64x60_CPU2DEV_1_BASE,
624 .size_reg = MV64x60_CPU2DEV_1_SIZE,
625 .base_bits = 16,
626 .size_bits = 16,
627 .get_from_field = mv64x60_shift_left,
628 .map_to_field = mv64x60_shift_right,
629 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 5 },
630 [MV64x60_CPU2DEV_2_WIN] = {
631 .base_reg = MV64x60_CPU2DEV_2_BASE,
632 .size_reg = MV64x60_CPU2DEV_2_SIZE,
633 .base_bits = 16,
634 .size_bits = 16,
635 .get_from_field = mv64x60_shift_left,
636 .map_to_field = mv64x60_shift_right,
637 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 6 },
638 [MV64x60_CPU2DEV_3_WIN] = {
639 .base_reg = MV64x60_CPU2DEV_3_BASE,
640 .size_reg = MV64x60_CPU2DEV_3_SIZE,
641 .base_bits = 16,
642 .size_bits = 16,
643 .get_from_field = mv64x60_shift_left,
644 .map_to_field = mv64x60_shift_right,
645 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 7 },
646
647 [MV64x60_CPU2BOOT_WIN] = {
648 .base_reg = MV64x60_CPU2BOOT_0_BASE,
649 .size_reg = MV64x60_CPU2BOOT_0_SIZE,
650 .base_bits = 16,
651 .size_bits = 16,
652 .get_from_field = mv64x60_shift_left,
653 .map_to_field = mv64x60_shift_right,
654 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 8 },
655
656 [MV64x60_CPU2PCI0_IO_WIN] = {
657 .base_reg = MV64x60_CPU2PCI0_IO_BASE,
658 .size_reg = MV64x60_CPU2PCI0_IO_SIZE,
659 .base_bits = 16,
660 .size_bits = 16,
661 .get_from_field = mv64x60_shift_left,
662 .map_to_field = mv64x60_shift_right,
663 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 9 },
664 [MV64x60_CPU2PCI0_MEM_0_WIN] = {
665 .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE,
666 .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE,
667 .base_bits = 16,
668 .size_bits = 16,
669 .get_from_field = mv64x60_shift_left,
670 .map_to_field = mv64x60_shift_right,
671 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 10 },
672 [MV64x60_CPU2PCI0_MEM_1_WIN] = {
673 .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE,
674 .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE,
675 .base_bits = 16,
676 .size_bits = 16,
677 .get_from_field = mv64x60_shift_left,
678 .map_to_field = mv64x60_shift_right,
679 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 11 },
680 [MV64x60_CPU2PCI0_MEM_2_WIN] = {
681 .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE,
682 .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE,
683 .base_bits = 16,
684 .size_bits = 16,
685 .get_from_field = mv64x60_shift_left,
686 .map_to_field = mv64x60_shift_right,
687 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 12 },
688 [MV64x60_CPU2PCI0_MEM_3_WIN] = {
689 .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE,
690 .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE,
691 .base_bits = 16,
692 .size_bits = 16,
693 .get_from_field = mv64x60_shift_left,
694 .map_to_field = mv64x60_shift_right,
695 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 13 },
696
697 [MV64x60_CPU2PCI1_IO_WIN] = {
698 .base_reg = MV64x60_CPU2PCI1_IO_BASE,
699 .size_reg = MV64x60_CPU2PCI1_IO_SIZE,
700 .base_bits = 16,
701 .size_bits = 16,
702 .get_from_field = mv64x60_shift_left,
703 .map_to_field = mv64x60_shift_right,
704 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 14 },
705 [MV64x60_CPU2PCI1_MEM_0_WIN] = {
706 .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE,
707 .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE,
708 .base_bits = 16,
709 .size_bits = 16,
710 .get_from_field = mv64x60_shift_left,
711 .map_to_field = mv64x60_shift_right,
712 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 15 },
713 [MV64x60_CPU2PCI1_MEM_1_WIN] = {
714 .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE,
715 .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE,
716 .base_bits = 16,
717 .size_bits = 16,
718 .get_from_field = mv64x60_shift_left,
719 .map_to_field = mv64x60_shift_right,
720 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 16 },
721 [MV64x60_CPU2PCI1_MEM_2_WIN] = {
722 .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE,
723 .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE,
724 .base_bits = 16,
725 .size_bits = 16,
726 .get_from_field = mv64x60_shift_left,
727 .map_to_field = mv64x60_shift_right,
728 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 17 },
729 [MV64x60_CPU2PCI1_MEM_3_WIN] = {
730 .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE,
731 .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE,
732 .base_bits = 16,
733 .size_bits = 16,
734 .get_from_field = mv64x60_shift_left,
735 .map_to_field = mv64x60_shift_right,
736 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 18 },
737
738 [MV64x60_CPU2SRAM_WIN] = {
739 .base_reg = MV64360_CPU2SRAM_BASE,
740 .size_reg = 0,
741 .base_bits = 16,
742 .size_bits = 0,
743 .get_from_field = mv64x60_shift_left,
744 .map_to_field = mv64x60_shift_right,
745 .extra = MV64x60_EXTRA_CPUWIN_ENAB | 19 },
746
747 [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
748 .base_reg = MV64x60_CPU2PCI0_IO_REMAP,
749 .size_reg = 0,
750 .base_bits = 16,
751 .size_bits = 0,
752 .get_from_field = mv64x60_shift_left,
753 .map_to_field = mv64x60_shift_right,
754 .extra = 0 },
755
756 [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
757 .base_reg = MV64x60_CPU2PCI1_IO_REMAP,
758 .size_reg = 0,
759 .base_bits = 16,
760 .size_bits = 0,
761 .get_from_field = mv64x60_shift_left,
762 .map_to_field = mv64x60_shift_right,
763 .extra = 0 },
764
765 [MV64x60_CPU_PROT_0_WIN] = {
766 .base_reg = MV64x60_CPU_PROT_BASE_0,
767 .size_reg = MV64x60_CPU_PROT_SIZE_0,
768 .base_bits = 16,
769 .size_bits = 16,
770 .get_from_field = mv64x60_shift_left,
771 .map_to_field = mv64x60_shift_right,
772 .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
773 [MV64x60_CPU_PROT_1_WIN] = {
774 .base_reg = MV64x60_CPU_PROT_BASE_1,
775 .size_reg = MV64x60_CPU_PROT_SIZE_1,
776 .base_bits = 16,
777 .size_bits = 16,
778 .get_from_field = mv64x60_shift_left,
779 .map_to_field = mv64x60_shift_right,
780 .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
781 [MV64x60_CPU_PROT_2_WIN] = {
782 .base_reg = MV64x60_CPU_PROT_BASE_2,
783 .size_reg = MV64x60_CPU_PROT_SIZE_2,
784 .base_bits = 16,
785 .size_bits = 16,
786 .get_from_field = mv64x60_shift_left,
787 .map_to_field = mv64x60_shift_right,
788 .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
789 [MV64x60_CPU_PROT_3_WIN] = {
790 .base_reg = MV64x60_CPU_PROT_BASE_3,
791 .size_reg = MV64x60_CPU_PROT_SIZE_3,
792 .base_bits = 16,
793 .size_bits = 16,
794 .get_from_field = mv64x60_shift_left,
795 .map_to_field = mv64x60_shift_right,
796 .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
797
798
799 [MV64x60_PCI02MEM_REMAP_0_WIN] = {
800 .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
801 .size_reg = 0,
802 .base_bits = 20,
803 .size_bits = 0,
804 .get_from_field = mv64x60_mask,
805 .map_to_field = mv64x60_mask,
806 .extra = 0 },
807 [MV64x60_PCI02MEM_REMAP_1_WIN] = {
808 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
809 .size_reg = 0,
810 .base_bits = 20,
811 .size_bits = 0,
812 .get_from_field = mv64x60_mask,
813 .map_to_field = mv64x60_mask,
814 .extra = 0 },
815 [MV64x60_PCI02MEM_REMAP_2_WIN] = {
816 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
817 .size_reg = 0,
818 .base_bits = 20,
819 .size_bits = 0,
820 .get_from_field = mv64x60_mask,
821 .map_to_field = mv64x60_mask,
822 .extra = 0 },
823 [MV64x60_PCI02MEM_REMAP_3_WIN] = {
824 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
825 .size_reg = 0,
826 .base_bits = 20,
827 .size_bits = 0,
828 .get_from_field = mv64x60_mask,
829 .map_to_field = mv64x60_mask,
830 .extra = 0 },
831
832 [MV64x60_PCI12MEM_REMAP_0_WIN] = {
833 .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
834 .size_reg = 0,
835 .base_bits = 20,
836 .size_bits = 0,
837 .get_from_field = mv64x60_mask,
838 .map_to_field = mv64x60_mask,
839 .extra = 0 },
840 [MV64x60_PCI12MEM_REMAP_1_WIN] = {
841 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
842 .size_reg = 0,
843 .base_bits = 20,
844 .size_bits = 0,
845 .get_from_field = mv64x60_mask,
846 .map_to_field = mv64x60_mask,
847 .extra = 0 },
848 [MV64x60_PCI12MEM_REMAP_2_WIN] = {
849 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
850 .size_reg = 0,
851 .base_bits = 20,
852 .size_bits = 0,
853 .get_from_field = mv64x60_mask,
854 .map_to_field = mv64x60_mask,
855 .extra = 0 },
856 [MV64x60_PCI12MEM_REMAP_3_WIN] = {
857 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
858 .size_reg = 0,
859 .base_bits = 20,
860 .size_bits = 0,
861 .get_from_field = mv64x60_mask,
862 .map_to_field = mv64x60_mask,
863 .extra = 0 },
864
865 [MV64x60_ENET2MEM_0_WIN] = {
866 .base_reg = MV64360_ENET2MEM_0_BASE,
867 .size_reg = MV64360_ENET2MEM_0_SIZE,
868 .base_bits = 16,
869 .size_bits = 16,
870 .get_from_field = mv64x60_mask,
871 .map_to_field = mv64x60_mask,
872 .extra = MV64x60_EXTRA_ENET_ENAB | 0 },
873 [MV64x60_ENET2MEM_1_WIN] = {
874 .base_reg = MV64360_ENET2MEM_1_BASE,
875 .size_reg = MV64360_ENET2MEM_1_SIZE,
876 .base_bits = 16,
877 .size_bits = 16,
878 .get_from_field = mv64x60_mask,
879 .map_to_field = mv64x60_mask,
880 .extra = MV64x60_EXTRA_ENET_ENAB | 1 },
881 [MV64x60_ENET2MEM_2_WIN] = {
882 .base_reg = MV64360_ENET2MEM_2_BASE,
883 .size_reg = MV64360_ENET2MEM_2_SIZE,
884 .base_bits = 16,
885 .size_bits = 16,
886 .get_from_field = mv64x60_mask,
887 .map_to_field = mv64x60_mask,
888 .extra = MV64x60_EXTRA_ENET_ENAB | 2 },
889 [MV64x60_ENET2MEM_3_WIN] = {
890 .base_reg = MV64360_ENET2MEM_3_BASE,
891 .size_reg = MV64360_ENET2MEM_3_SIZE,
892 .base_bits = 16,
893 .size_bits = 16,
894 .get_from_field = mv64x60_mask,
895 .map_to_field = mv64x60_mask,
896 .extra = MV64x60_EXTRA_ENET_ENAB | 3 },
897 [MV64x60_ENET2MEM_4_WIN] = {
898 .base_reg = MV64360_ENET2MEM_4_BASE,
899 .size_reg = MV64360_ENET2MEM_4_SIZE,
900 .base_bits = 16,
901 .size_bits = 16,
902 .get_from_field = mv64x60_mask,
903 .map_to_field = mv64x60_mask,
904 .extra = MV64x60_EXTRA_ENET_ENAB | 4 },
905 [MV64x60_ENET2MEM_5_WIN] = {
906 .base_reg = MV64360_ENET2MEM_5_BASE,
907 .size_reg = MV64360_ENET2MEM_5_SIZE,
908 .base_bits = 16,
909 .size_bits = 16,
910 .get_from_field = mv64x60_mask,
911 .map_to_field = mv64x60_mask,
912 .extra = MV64x60_EXTRA_ENET_ENAB | 5 },
913
914 [MV64x60_MPSC2MEM_0_WIN] = {
915 .base_reg = MV64360_MPSC2MEM_0_BASE,
916 .size_reg = MV64360_MPSC2MEM_0_SIZE,
917 .base_bits = 16,
918 .size_bits = 16,
919 .get_from_field = mv64x60_mask,
920 .map_to_field = mv64x60_mask,
921 .extra = MV64x60_EXTRA_MPSC_ENAB | 0 },
922 [MV64x60_MPSC2MEM_1_WIN] = {
923 .base_reg = MV64360_MPSC2MEM_1_BASE,
924 .size_reg = MV64360_MPSC2MEM_1_SIZE,
925 .base_bits = 16,
926 .size_bits = 16,
927 .get_from_field = mv64x60_mask,
928 .map_to_field = mv64x60_mask,
929 .extra = MV64x60_EXTRA_MPSC_ENAB | 1 },
930 [MV64x60_MPSC2MEM_2_WIN] = {
931 .base_reg = MV64360_MPSC2MEM_2_BASE,
932 .size_reg = MV64360_MPSC2MEM_2_SIZE,
933 .base_bits = 16,
934 .size_bits = 16,
935 .get_from_field = mv64x60_mask,
936 .map_to_field = mv64x60_mask,
937 .extra = MV64x60_EXTRA_MPSC_ENAB | 2 },
938 [MV64x60_MPSC2MEM_3_WIN] = {
939 .base_reg = MV64360_MPSC2MEM_3_BASE,
940 .size_reg = MV64360_MPSC2MEM_3_SIZE,
941 .base_bits = 16,
942 .size_bits = 16,
943 .get_from_field = mv64x60_mask,
944 .map_to_field = mv64x60_mask,
945 .extra = MV64x60_EXTRA_MPSC_ENAB | 3 },
946
947 [MV64x60_IDMA2MEM_0_WIN] = {
948 .base_reg = MV64360_IDMA2MEM_0_BASE,
949 .size_reg = MV64360_IDMA2MEM_0_SIZE,
950 .base_bits = 16,
951 .size_bits = 16,
952 .get_from_field = mv64x60_mask,
953 .map_to_field = mv64x60_mask,
954 .extra = MV64x60_EXTRA_IDMA_ENAB | 0 },
955 [MV64x60_IDMA2MEM_1_WIN] = {
956 .base_reg = MV64360_IDMA2MEM_1_BASE,
957 .size_reg = MV64360_IDMA2MEM_1_SIZE,
958 .base_bits = 16,
959 .size_bits = 16,
960 .get_from_field = mv64x60_mask,
961 .map_to_field = mv64x60_mask,
962 .extra = MV64x60_EXTRA_IDMA_ENAB | 1 },
963 [MV64x60_IDMA2MEM_2_WIN] = {
964 .base_reg = MV64360_IDMA2MEM_2_BASE,
965 .size_reg = MV64360_IDMA2MEM_2_SIZE,
966 .base_bits = 16,
967 .size_bits = 16,
968 .get_from_field = mv64x60_mask,
969 .map_to_field = mv64x60_mask,
970 .extra = MV64x60_EXTRA_IDMA_ENAB | 2 },
971 [MV64x60_IDMA2MEM_3_WIN] = {
972 .base_reg = MV64360_IDMA2MEM_3_BASE,
973 .size_reg = MV64360_IDMA2MEM_3_SIZE,
974 .base_bits = 16,
975 .size_bits = 16,
976 .get_from_field = mv64x60_mask,
977 .map_to_field = mv64x60_mask,
978 .extra = MV64x60_EXTRA_IDMA_ENAB | 3 },
979 [MV64x60_IDMA2MEM_4_WIN] = {
980 .base_reg = MV64360_IDMA2MEM_4_BASE,
981 .size_reg = MV64360_IDMA2MEM_4_SIZE,
982 .base_bits = 16,
983 .size_bits = 16,
984 .get_from_field = mv64x60_mask,
985 .map_to_field = mv64x60_mask,
986 .extra = MV64x60_EXTRA_IDMA_ENAB | 4 },
987 [MV64x60_IDMA2MEM_5_WIN] = {
988 .base_reg = MV64360_IDMA2MEM_5_BASE,
989 .size_reg = MV64360_IDMA2MEM_5_SIZE,
990 .base_bits = 16,
991 .size_bits = 16,
992 .get_from_field = mv64x60_mask,
993 .map_to_field = mv64x60_mask,
994 .extra = MV64x60_EXTRA_IDMA_ENAB | 5 },
995 [MV64x60_IDMA2MEM_6_WIN] = {
996 .base_reg = MV64360_IDMA2MEM_6_BASE,
997 .size_reg = MV64360_IDMA2MEM_6_SIZE,
998 .base_bits = 16,
999 .size_bits = 16,
1000 .get_from_field = mv64x60_mask,
1001 .map_to_field = mv64x60_mask,
1002 .extra = MV64x60_EXTRA_IDMA_ENAB | 6 },
1003 [MV64x60_IDMA2MEM_7_WIN] = {
1004 .base_reg = MV64360_IDMA2MEM_7_BASE,
1005 .size_reg = MV64360_IDMA2MEM_7_SIZE,
1006 .base_bits = 16,
1007 .size_bits = 16,
1008 .get_from_field = mv64x60_mask,
1009 .map_to_field = mv64x60_mask,
1010 .extra = MV64x60_EXTRA_IDMA_ENAB | 7 },
1011};
1012
1013struct mv64x60_64bit_window
1014 mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = {
1015
1016 [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
1017 .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
1018 .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
1019 .size_reg = 0,
1020 .base_lo_bits = 16,
1021 .size_bits = 0,
1022 .get_from_field = mv64x60_shift_left,
1023 .map_to_field = mv64x60_shift_right,
1024 .extra = 0 },
1025 [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
1026 .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
1027 .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
1028 .size_reg = 0,
1029 .base_lo_bits = 16,
1030 .size_bits = 0,
1031 .get_from_field = mv64x60_shift_left,
1032 .map_to_field = mv64x60_shift_right,
1033 .extra = 0 },
1034 [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
1035 .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
1036 .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
1037 .size_reg = 0,
1038 .base_lo_bits = 16,
1039 .size_bits = 0,
1040 .get_from_field = mv64x60_shift_left,
1041 .map_to_field = mv64x60_shift_right,
1042 .extra = 0 },
1043 [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
1044 .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
1045 .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
1046 .size_reg = 0,
1047 .base_lo_bits = 16,
1048 .size_bits = 0,
1049 .get_from_field = mv64x60_shift_left,
1050 .map_to_field = mv64x60_shift_right,
1051 .extra = 0 },
1052
1053 [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
1054 .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
1055 .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
1056 .size_reg = 0,
1057 .base_lo_bits = 16,
1058 .size_bits = 0,
1059 .get_from_field = mv64x60_shift_left,
1060 .map_to_field = mv64x60_shift_right,
1061 .extra = 0 },
1062 [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
1063 .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
1064 .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
1065 .size_reg = 0,
1066 .base_lo_bits = 16,
1067 .size_bits = 0,
1068 .get_from_field = mv64x60_shift_left,
1069 .map_to_field = mv64x60_shift_right,
1070 .extra = 0 },
1071 [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
1072 .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
1073 .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
1074 .size_reg = 0,
1075 .base_lo_bits = 16,
1076 .size_bits = 0,
1077 .get_from_field = mv64x60_shift_left,
1078 .map_to_field = mv64x60_shift_right,
1079 .extra = 0 },
1080 [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
1081 .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
1082 .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
1083 .size_reg = 0,
1084 .base_lo_bits = 16,
1085 .size_bits = 0,
1086 .get_from_field = mv64x60_shift_left,
1087 .map_to_field = mv64x60_shift_right,
1088 .extra = 0 },
1089
1090 [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
1091 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
1092 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
1093 .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE,
1094 .base_lo_bits = 20,
1095 .size_bits = 20,
1096 .get_from_field = mv64x60_mask,
1097 .map_to_field = mv64x60_mask,
1098 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1099 [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
1100 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
1101 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
1102 .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE,
1103 .base_lo_bits = 20,
1104 .size_bits = 20,
1105 .get_from_field = mv64x60_mask,
1106 .map_to_field = mv64x60_mask,
1107 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1108 [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
1109 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
1110 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
1111 .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE,
1112 .base_lo_bits = 20,
1113 .size_bits = 20,
1114 .get_from_field = mv64x60_mask,
1115 .map_to_field = mv64x60_mask,
1116 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1117 [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
1118 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
1119 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
1120 .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE,
1121 .base_lo_bits = 20,
1122 .size_bits = 20,
1123 .get_from_field = mv64x60_mask,
1124 .map_to_field = mv64x60_mask,
1125 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1126
1127 [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
1128 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
1129 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
1130 .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE,
1131 .base_lo_bits = 20,
1132 .size_bits = 20,
1133 .get_from_field = mv64x60_mask,
1134 .map_to_field = mv64x60_mask,
1135 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1136 [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
1137 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
1138 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
1139 .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE,
1140 .base_lo_bits = 20,
1141 .size_bits = 20,
1142 .get_from_field = mv64x60_mask,
1143 .map_to_field = mv64x60_mask,
1144 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1145 [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
1146 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
1147 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
1148 .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE,
1149 .base_lo_bits = 20,
1150 .size_bits = 20,
1151 .get_from_field = mv64x60_mask,
1152 .map_to_field = mv64x60_mask,
1153 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1154 [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
1155 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
1156 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
1157 .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE,
1158 .base_lo_bits = 20,
1159 .size_bits = 20,
1160 .get_from_field = mv64x60_mask,
1161 .map_to_field = mv64x60_mask,
1162 .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1163
1164
1165};
1166
