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14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <syslib/virtex_devices.h>
19#include <platforms/4xx/xparameters/xparameters.h>
20#include <asm/io.h>
21
22
23
24
25#define XPAR_UARTLITE(num) { \
26 .name = "uartlite", \
27 .id = num, \
28 .num_resources = 2, \
29 .resource = (struct resource[]) { \
30 { \
31 .start = XPAR_UARTLITE_##num##_BASEADDR + 3, \
32 .end = XPAR_UARTLITE_##num##_HIGHADDR, \
33 .flags = IORESOURCE_MEM, \
34 }, \
35 { \
36 .start = XPAR_INTC_0_UARTLITE_##num##_VEC_ID, \
37 .flags = IORESOURCE_IRQ, \
38 }, \
39 }, \
40}
41
42
43
44
45#define XPAR_UART(num) { \
46 .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \
47 .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
48 .iotype = UPIO_MEM, \
49 .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \
50 .flags = UPF_BOOT_AUTOCONF, \
51 .regshift = 2, \
52}
53
54
55
56
57#define XPAR_SYSACE(num) { \
58 .name = "xsysace", \
59 .id = XPAR_SYSACE_##num##_DEVICE_ID, \
60 .num_resources = 2, \
61 .resource = (struct resource[]) { \
62 { \
63 .start = XPAR_SYSACE_##num##_BASEADDR, \
64 .end = XPAR_SYSACE_##num##_HIGHADDR, \
65 .flags = IORESOURCE_MEM, \
66 }, \
67 { \
68 .start = XPAR_INTC_0_SYSACE_##num##_VEC_ID, \
69 .flags = IORESOURCE_IRQ, \
70 }, \
71 }, \
72}
73
74
75
76
77#define XPAR_TFT(num) { \
78 .name = "xilinxfb", \
79 .id = num, \
80 .num_resources = 1, \
81 .resource = (struct resource[]) { \
82 { \
83 .start = XPAR_TFT_##num##_BASEADDR, \
84 .end = XPAR_TFT_##num##_BASEADDR+7, \
85 .flags = IORESOURCE_IO, \
86 }, \
87 }, \
88}
89
90#define XPAR_AC97_CONTROLLER_REFERENCE(num) { \
91 .name = "ml403_ac97cr", \
92 .id = num, \
93 .num_resources = 3, \
94 .resource = (struct resource[]) { \
95 { \
96 .start = XPAR_OPB_AC97_CONTROLLER_REF_##num##_BASEADDR, \
97 .end = XPAR_OPB_AC97_CONTROLLER_REF_##num##_HIGHADDR, \
98 .flags = IORESOURCE_MEM, \
99 }, \
100 { \
101 .start = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_PLAYBACK_VEC_ID, \
102 .end = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_PLAYBACK_VEC_ID, \
103 .flags = IORESOURCE_IRQ, \
104 }, \
105 { \
106 .start = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_RECORD_VEC_ID, \
107 .end = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_RECORD_VEC_ID, \
108 .flags = IORESOURCE_IRQ, \
109 }, \
110 }, \
111}
112
113
114struct plat_serial8250_port virtex_serial_platform_data[] = {
115#if defined(XPAR_UARTNS550_0_BASEADDR)
116 XPAR_UART(0),
117#endif
118#if defined(XPAR_UARTNS550_1_BASEADDR)
119 XPAR_UART(1),
120#endif
121#if defined(XPAR_UARTNS550_2_BASEADDR)
122 XPAR_UART(2),
123#endif
124#if defined(XPAR_UARTNS550_3_BASEADDR)
125 XPAR_UART(3),
126#endif
127#if defined(XPAR_UARTNS550_4_BASEADDR)
128 XPAR_UART(4),
129#endif
130#if defined(XPAR_UARTNS550_5_BASEADDR)
131 XPAR_UART(5),
132#endif
133#if defined(XPAR_UARTNS550_6_BASEADDR)
134 XPAR_UART(6),
135#endif
136#if defined(XPAR_UARTNS550_7_BASEADDR)
137 XPAR_UART(7),
138#endif
139 { },
140};
141
142
143struct platform_device virtex_platform_devices[] = {
144
145#if defined(XPAR_UARTLITE_0_BASEADDR)
146 XPAR_UARTLITE(0),
147#endif
148#if defined(XPAR_UARTLITE_1_BASEADDR)
149 XPAR_UARTLITE(1),
150#endif
151#if defined(XPAR_UARTLITE_2_BASEADDR)
152 XPAR_UARTLITE(2),
153#endif
154#if defined(XPAR_UARTLITE_3_BASEADDR)
155 XPAR_UARTLITE(3),
156#endif
157#if defined(XPAR_UARTLITE_4_BASEADDR)
158 XPAR_UARTLITE(4),
159#endif
160#if defined(XPAR_UARTLITE_5_BASEADDR)
161 XPAR_UARTLITE(5),
162#endif
163#if defined(XPAR_UARTLITE_6_BASEADDR)
164 XPAR_UARTLITE(6),
165#endif
166#if defined(XPAR_UARTLITE_7_BASEADDR)
167 XPAR_UARTLITE(7),
168#endif
169
170
171#if defined(XPAR_UARTNS550_0_BASEADDR)
172 {
173 .name = "serial8250",
174 .id = 0,
175 .dev.platform_data = virtex_serial_platform_data,
176 },
177#endif
178
179
180#if defined(XPAR_SYSACE_0_BASEADDR)
181 XPAR_SYSACE(0),
182#endif
183#if defined(XPAR_SYSACE_1_BASEADDR)
184 XPAR_SYSACE(1),
185#endif
186
187#if defined(XPAR_TFT_0_BASEADDR)
188 XPAR_TFT(0),
189#endif
190#if defined(XPAR_TFT_1_BASEADDR)
191 XPAR_TFT(1),
192#endif
193#if defined(XPAR_TFT_2_BASEADDR)
194 XPAR_TFT(2),
195#endif
196#if defined(XPAR_TFT_3_BASEADDR)
197 XPAR_TFT(3),
198#endif
199
200
201#if defined(XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR)
202 XPAR_AC97_CONTROLLER_REFERENCE(0),
203#endif
204#if defined(XPAR_OPB_AC97_CONTROLLER_REF_1_BASEADDR)
205 XPAR_AC97_CONTROLLER_REFERENCE(1),
206#endif
207};
208
209
210static void __init
211virtex_early_serial_init(int num, struct plat_serial8250_port *pdata)
212{
213#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
214 struct uart_port serial_req;
215
216 memset(&serial_req, 0, sizeof(serial_req));
217 serial_req.mapbase = pdata->mapbase;
218 serial_req.membase = pdata->membase;
219 serial_req.irq = pdata->irq;
220 serial_req.uartclk = pdata->uartclk;
221 serial_req.regshift = pdata->regshift;
222 serial_req.iotype = pdata->iotype;
223 serial_req.flags = pdata->flags;
224 gen550_init(num, &serial_req);
225#endif
226}
227
228void __init
229virtex_early_serial_map(void)
230{
231#ifdef CONFIG_SERIAL_8250
232 struct plat_serial8250_port *pdata;
233 int i = 0;
234
235 pdata = virtex_serial_platform_data;
236 while(pdata && pdata->flags) {
237 pdata->membase = ioremap(pdata->mapbase, 0x100);
238 virtex_early_serial_init(i, pdata);
239 pdata++;
240 i++;
241 }
242#endif
243}
244
245
246
247
248
249
250
251int __attribute__ ((weak))
252virtex_device_fixup(struct platform_device *dev)
253{
254 return 0;
255}
256
257static int __init virtex_init(void)
258{
259 struct platform_device *index = virtex_platform_devices;
260 unsigned int ret = 0;
261 int i;
262
263 for (i = 0; i < ARRAY_SIZE(virtex_platform_devices); i++, index++) {
264 if (virtex_device_fixup(index) != 0)
265 continue;
266
267 if (platform_device_register(index)) {
268 ret = 1;
269 printk(KERN_ERR "cannot register dev %s:%d\n",
270 index->name, index->id);
271 }
272 }
273 return ret;
274}
275
276subsys_initcall(virtex_init);
277
