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8#include <asm/head.h>
9#include <asm/asi.h>
10#include <asm/contregs.h>
11#include <asm/page.h>
12#include <asm/psr.h>
13#include <asm/ptrace.h>
14#include <asm/winmacro.h>
15#include <asm/asmmacro.h>
16#include <asm/thread_info.h>
17
18
19#define t_psr l0
20#define t_pc l1
21#define t_npc l2
22#define t_wim l3
23#define t_twinmask l4
24#define t_kstack l5
25#define t_retpc l6
26#define t_systable l7
27#define curptr g6
28
29 .text
30 .align 4
31
32
33 .globl tsetup_7win_patch1, tsetup_7win_patch2
34 .globl tsetup_7win_patch3, tsetup_7win_patch4
35 .globl tsetup_7win_patch5, tsetup_7win_patch6
36tsetup_7win_patch1: sll %t_wim, 0x6, %t_wim
37tsetup_7win_patch2: and %g2, 0x7f, %g2
38tsetup_7win_patch3: and %g2, 0x7f, %g2
39tsetup_7win_patch4: and %g1, 0x7f, %g1
40tsetup_7win_patch5: sll %t_wim, 0x6, %t_wim
41tsetup_7win_patch6: and %g2, 0x7f, %g2
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74 .globl trap_setup, tsetup_patch1, tsetup_patch2
75 .globl tsetup_patch3, tsetup_patch4
76 .globl tsetup_patch5, tsetup_patch6
77trap_setup:
78
79
80
81 mov 1, %t_twinmask
82 andcc %t_psr, PSR_PS, %g0 ! fromsupv_p = (psr & PSR_PS)
83 be trap_setup_from_user ! nope, from user mode
84 sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
85
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87
88
89 sub %fp, (STACKFRAME_SZ + TRACEREG_SZ), %t_kstack
90 STORE_PT_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
91
92
93 andcc %t_twinmask, %t_wim, %g0
94 bne trap_setup_kernel_spill ! in trap window, clean up
95 nop
96
97
98
99
100 jmpl %t_retpc + 0x8, %g0 ! return to caller
101 mov %t_kstack, %sp ! jump onto new stack
102
103trap_setup_kernel_spill:
104 ld [%curptr + TI_UWINMASK], %g1
105 orcc %g0, %g1, %g0
106 bne trap_setup_user_spill ! there are some user windows, yuck
107
108
109
110 srl %t_wim, 0x1, %g2 ! begin computation of new %wim
111tsetup_patch1:
112 sll %t_wim, 0x7, %t_wim ! patched on 7 window Sparcs
113 or %t_wim, %g2, %g2
114tsetup_patch2:
115 and %g2, 0xff, %g2 ! patched on 7 window Sparcs
116
117 save %g0, %g0, %g0
118
119
120 wr %g2, 0x0, %wim
121
122
123 STORE_WINDOW(sp)
124
125 restore %g0, %g0, %g0
126
127 jmpl %t_retpc + 0x8, %g0 ! return to caller
128 mov %t_kstack, %sp ! and onto new kernel stack
129
130#define STACK_OFFSET (THREAD_SIZE - TRACEREG_SZ - STACKFRAME_SZ)
131
132trap_setup_from_user:
133
134 LOAD_CURRENT(t_kstack, t_twinmask)
135
136 sethi %hi(STACK_OFFSET), %t_twinmask
137 or %t_twinmask, %lo(STACK_OFFSET), %t_twinmask
138 add %t_kstack, %t_twinmask, %t_kstack
139
140 mov 1, %t_twinmask
141 sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
142
143
144 STORE_PT_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
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149 sethi %hi(STACK_OFFSET), %curptr
150 or %curptr, %lo(STACK_OFFSET), %curptr
151 sub %t_kstack, %curptr, %curptr
152#else
153 sethi %hi(~(THREAD_SIZE - 1)), %curptr
154 and %t_kstack, %curptr, %curptr
155#endif
156
157
158 st %g0, [%curptr + TI_W_SAVED]
159
160
161 andcc %t_twinmask, %t_wim, %g0
162 bne trap_setup_user_spill ! yep we are
163 orn %g0, %t_twinmask, %g1 ! negate trap win mask into %g1
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182 subcc %t_wim, %t_twinmask, %g2
183 bneg,a 1f
184 sub %g2, 0x1, %g2
1851:
186 andn %g2, %t_twinmask, %g2
187tsetup_patch3:
188 and %g2, 0xff, %g2 ! patched on 7win Sparcs
189 st %g2, [%curptr + TI_UWINMASK] ! store new umask
190
191 jmpl %t_retpc + 0x8, %g0 ! return to caller
192 mov %t_kstack, %sp ! and onto kernel stack
193
194trap_setup_user_spill:
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201tsetup_patch4:
202 and %g1, 0xff, %g1 ! patched on 7win Sparcs, mask
203 srl %t_wim, 0x1, %g2 ! compute new %wim
204tsetup_patch5:
205 sll %t_wim, 0x7, %t_wim ! patched on 7win Sparcs
206 or %t_wim, %g2, %g2 ! %g2 is new %wim
207tsetup_patch6:
208 and %g2, 0xff, %g2 ! patched on 7win Sparcs
209 andn %g1, %g2, %g1 ! clear this bit in %g1
210 st %g1, [%curptr + TI_UWINMASK]
211
212 save %g0, %g0, %g0
213
214 wr %g2, 0x0, %wim
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218
219 .globl tsetup_mmu_patchme
220tsetup_mmu_patchme:
221 b tsetup_sun4c_stackchk
222 andcc %sp, 0x7, %g0
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228
229#define glob_tmp g1
230
231 .globl tsetup_sun4c_stackchk
232tsetup_sun4c_stackchk:
233
234 bne trap_setup_user_stack_is_bolixed
235 sra %sp, 29, %glob_tmp
236
237 add %glob_tmp, 0x1, %glob_tmp
238 andncc %glob_tmp, 0x1, %g0
239 bne trap_setup_user_stack_is_bolixed
240 and %sp, 0xfff, %glob_tmp ! delay slot
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245 add %glob_tmp, 0x38, %glob_tmp
246 andncc %glob_tmp, 0xff8, %g0
247 be tsetup_sun4c_onepage ! only one page to check
248 lda [%sp] ASI_PTE, %glob_tmp ! have to check first page anyways
249
250tsetup_sun4c_twopages:
251
252 srl %glob_tmp, 29, %glob_tmp
253 cmp %glob_tmp, 0x6
254 bne trap_setup_user_stack_is_bolixed
255 add %sp, 0x38, %glob_tmp
256
257 sra %glob_tmp, 29, %glob_tmp
258 add %glob_tmp, 0x1, %glob_tmp
259 andncc %glob_tmp, 0x1, %g0
260 bne trap_setup_user_stack_is_bolixed
261 add %sp, 0x38, %glob_tmp
262
263 lda [%glob_tmp] ASI_PTE, %glob_tmp
264
265tsetup_sun4c_onepage:
266 srl %glob_tmp, 29, %glob_tmp
267 cmp %glob_tmp, 0x6 ! can user write to it?
268 bne trap_setup_user_stack_is_bolixed ! failure
269 nop
270
271 STORE_WINDOW(sp)
272
273 restore %g0, %g0, %g0
274
275 jmpl %t_retpc + 0x8, %g0
276 mov %t_kstack, %sp
277
278 .globl tsetup_srmmu_stackchk
279tsetup_srmmu_stackchk:
280
281 bne trap_setup_user_stack_is_bolixed
282 sethi %hi(PAGE_OFFSET), %glob_tmp
283
284 cmp %glob_tmp, %sp
285 bleu,a 1f
286 lda [%g0] ASI_M_MMUREGS, %glob_tmp ! read MMU control
287
288trap_setup_user_stack_is_bolixed:
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292 SAVE_BOLIXED_USER_STACK(curptr, g3)
293 restore %g0, %g0, %g0
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295 jmpl %t_retpc + 0x8, %g0
296 mov %t_kstack, %sp
297
2981:
299
300 or %glob_tmp, 0x2, %glob_tmp ! or in no_fault bit
301 sta %glob_tmp, [%g0] ASI_M_MMUREGS ! set it
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304 STORE_WINDOW(sp)
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307 andn %glob_tmp, 0x2, %glob_tmp
308 sta %glob_tmp, [%g0] ASI_M_MMUREGS
309 mov AC_M_SFAR, %glob_tmp
310 lda [%glob_tmp] ASI_M_MMUREGS, %g0
311 mov AC_M_SFSR, %glob_tmp
312 lda [%glob_tmp] ASI_M_MMUREGS, %glob_tmp ! save away status of winstore
313 andcc %glob_tmp, 0x2, %g0 ! did we fault?
314 bne trap_setup_user_stack_is_bolixed ! failure
315 nop
316
317 restore %g0, %g0, %g0
318
319 jmpl %t_retpc + 0x8, %g0
320 mov %t_kstack, %sp
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322