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13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19#include <linux/blkdev.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/compiler.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/delay.h>
26#include <linux/time.h>
27#include <linux/hdreg.h>
28#include <linux/dma-mapping.h>
29#include <linux/completion.h>
30#include <linux/scatterlist.h>
31#include <asm/io.h>
32#include <asm/uaccess.h>
33
34#if 0
35#define CARM_DEBUG
36#define CARM_VERBOSE_DEBUG
37#else
38#undef CARM_DEBUG
39#undef CARM_VERBOSE_DEBUG
40#endif
41#undef CARM_NDEBUG
42
43#define DRV_NAME "sx8"
44#define DRV_VERSION "1.0"
45#define PFX DRV_NAME ": "
46
47MODULE_AUTHOR("Jeff Garzik");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50MODULE_VERSION(DRV_VERSION);
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68static int max_queue = 1;
69module_param(max_queue, int, 0444);
70MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71
72
73#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
74
75
76#define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
77#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
78#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79
80
81#ifdef CARM_DEBUG
82#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
83#ifdef CARM_VERBOSE_DEBUG
84#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
85#else
86#define VPRINTK(fmt, args...)
87#endif
88#else
89#define DPRINTK(fmt, args...)
90#define VPRINTK(fmt, args...)
91#endif
92
93#ifdef CARM_NDEBUG
94#define assert(expr)
95#else
96#define assert(expr) \
97 if(unlikely(!(expr))) { \
98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
99 #expr,__FILE__,__FUNCTION__,__LINE__); \
100 }
101#endif
102
103
104struct carm_host;
105
106enum {
107
108 CARM_MAX_PORTS = 8,
109 CARM_SHM_SIZE = (4096 << 7),
110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
112
113
114 CARM_MAX_REQ = 64,
115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4),
116
117
118 CARM_MAX_REQ_SG = 32,
119 CARM_MAX_HOST_SG = 600,
120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4),
121
122
123 CARM_IHQP = 0x1c,
124 CARM_INT_STAT = 0x10,
125 CARM_INT_MASK = 0x14,
126 CARM_HMUC = 0x18,
127 RBUF_ADDR_LO = 0x20,
128 RBUF_ADDR_HI = 0x24,
129 RBUF_BYTE_SZ = 0x28,
130 CARM_RESP_IDX = 0x2c,
131 CARM_CMS0 = 0x30,
132 CARM_LMUC = 0x48,
133 CARM_HMPHA = 0x6c,
134 CARM_INITC = 0xb5,
135
136
137 INT_RESERVED = 0xfffffff0,
138 INT_WATCHDOG = (1 << 3),
139 INT_Q_OVERFLOW = (1 << 2),
140 INT_Q_AVAILABLE = (1 << 1),
141 INT_RESPONSE = (1 << 0),
142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
144 INT_RESPONSE,
145
146
147 CARM_HAVE_RESP = 0x01,
148 CARM_MSG_READ = 1,
149 CARM_MSG_WRITE = 2,
150 CARM_MSG_VERIFY = 3,
151 CARM_MSG_GET_CAPACITY = 4,
152 CARM_MSG_FLUSH = 5,
153 CARM_MSG_IOCTL = 6,
154 CARM_MSG_ARRAY = 8,
155 CARM_MSG_MISC = 9,
156 CARM_CME = (1 << 2),
157 CARM_RME = (1 << 1),
158 CARM_WZBC = (1 << 0),
159 CARM_RMI = (1 << 0),
160 CARM_Q_FULL = (1 << 3),
161 CARM_MSG_SIZE = 288,
162 CARM_Q_LEN = 48,
163
164
165 CARM_IOC_SCAN_CHAN = 5,
166 CARM_IOC_GET_TCQ = 13,
167 CARM_IOC_SET_TCQ = 14,
168
169 IOC_SCAN_CHAN_NODEV = 0x1f,
170 IOC_SCAN_CHAN_OFFSET = 0x40,
171
172
173 CARM_ARRAY_INFO = 0,
174
175 ARRAY_NO_EXIST = (1 << 31),
176
177
178 RMSG_SZ = 8,
179 RMSG_Q_LEN = 48,
180 RMSG_OK = 1,
181
182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
183
184 PDC_SHM_SIZE = (4096 << 7),
185
186
187 MISC_GET_FW_VER = 2,
188 MISC_ALLOC_MEM = 3,
189 MISC_SET_TIME = 5,
190
191
192 FW_VER_4PORT = (1 << 2),
193 FW_VER_NON_RAID = (1 << 1),
194 FW_VER_ZCR = (1 << 0),
195
196
197 FL_NON_RAID = FW_VER_NON_RAID,
198 FL_4PORT = FW_VER_4PORT,
199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
200 FL_DAC = (1 << 16),
201 FL_DYN_MAJOR = (1 << 17),
202};
203
204enum {
205 CARM_SG_BOUNDARY = 0xffffUL,
206};
207
208enum scatter_gather_types {
209 SGT_32BIT = 0,
210 SGT_64BIT = 1,
211};
212
213enum host_states {
214 HST_INVALID,
215 HST_ALLOC_BUF,
216 HST_ERROR,
217 HST_PORT_SCAN,
218 HST_DEV_SCAN_START,
219 HST_DEV_SCAN,
220 HST_DEV_ACTIVATE,
221 HST_PROBE_FINISHED,
222 HST_PROBE_START,
223 HST_SYNC_TIME,
224 HST_GET_FW_VER,
225};
226
227#ifdef CARM_DEBUG
228static const char *state_name[] = {
229 "HST_INVALID",
230 "HST_ALLOC_BUF",
231 "HST_ERROR",
232 "HST_PORT_SCAN",
233 "HST_DEV_SCAN_START",
234 "HST_DEV_SCAN",
235 "HST_DEV_ACTIVATE",
236 "HST_PROBE_FINISHED",
237 "HST_PROBE_START",
238 "HST_SYNC_TIME",
239 "HST_GET_FW_VER",
240};
241#endif
242
243struct carm_port {
244 unsigned int port_no;
245 struct gendisk *disk;
246 struct carm_host *host;
247
248
249 u64 capacity;
250 char name[41];
251 u16 dev_geom_head;
252 u16 dev_geom_sect;
253 u16 dev_geom_cyl;
254};
255
256struct carm_request {
257 unsigned int tag;
258 int n_elem;
259 unsigned int msg_type;
260 unsigned int msg_subtype;
261 unsigned int msg_bucket;
262 struct request *rq;
263 struct carm_port *port;
264 struct scatterlist sg[CARM_MAX_REQ_SG];
265};
266
267struct carm_host {
268 unsigned long flags;
269 void __iomem *mmio;
270 void *shm;
271 dma_addr_t shm_dma;
272
273 int major;
274 int id;
275 char name[32];
276
277 spinlock_t lock;
278 struct pci_dev *pdev;
279 unsigned int state;
280 u32 fw_ver;
281
282 struct request_queue *oob_q;
283 unsigned int n_oob;
284
285 unsigned int hw_sg_used;
286
287 unsigned int resp_idx;
288
289 unsigned int wait_q_prod;
290 unsigned int wait_q_cons;
291 struct request_queue *wait_q[CARM_MAX_WAIT_Q];
292
293 unsigned int n_msgs;
294 u64 msg_alloc;
295 struct carm_request req[CARM_MAX_REQ];
296 void *msg_base;
297 dma_addr_t msg_dma;
298
299 int cur_scan_dev;
300 unsigned long dev_active;
301 unsigned long dev_present;
302 struct carm_port port[CARM_MAX_PORTS];
303
304 struct work_struct fsm_task;
305
306 struct completion probe_comp;
307};
308
309struct carm_response {
310 __le32 ret_handle;
311 __le32 status;
312} __attribute__((packed));
313
314struct carm_msg_sg {
315 __le32 start;
316 __le32 len;
317} __attribute__((packed));
318
319struct carm_msg_rw {
320 u8 type;
321 u8 id;
322 u8 sg_count;
323 u8 sg_type;
324 __le32 handle;
325 __le32 lba;
326 __le16 lba_count;
327 __le16 lba_high;
328 struct carm_msg_sg sg[32];
329} __attribute__((packed));
330
331struct carm_msg_allocbuf {
332 u8 type;
333 u8 subtype;
334 u8 n_sg;
335 u8 sg_type;
336 __le32 handle;
337 __le32 addr;
338 __le32 len;
339 __le32 evt_pool;
340 __le32 n_evt;
341 __le32 rbuf_pool;
342 __le32 n_rbuf;
343 __le32 msg_pool;
344 __le32 n_msg;
345 struct carm_msg_sg sg[8];
346} __attribute__((packed));
347
348struct carm_msg_ioctl {
349 u8 type;
350 u8 subtype;
351 u8 array_id;
352 u8 reserved1;
353 __le32 handle;
354 __le32 data_addr;
355 u32 reserved2;
356} __attribute__((packed));
357
358struct carm_msg_sync_time {
359 u8 type;
360 u8 subtype;
361 u16 reserved1;
362 __le32 handle;
363 u32 reserved2;
364 __le32 timestamp;
365} __attribute__((packed));
366
367struct carm_msg_get_fw_ver {
368 u8 type;
369 u8 subtype;
370 u16 reserved1;
371 __le32 handle;
372 __le32 data_addr;
373 u32 reserved2;
374} __attribute__((packed));
375
376struct carm_fw_ver {
377 __le32 version;
378 u8 features;
379 u8 reserved1;
380 u16 reserved2;
381} __attribute__((packed));
382
383struct carm_array_info {
384 __le32 size;
385
386 __le16 size_hi;
387 __le16 stripe_size;
388
389 __le32 mode;
390
391 __le16 stripe_blk_sz;
392 __le16 reserved1;
393
394 __le16 cyl;
395 __le16 head;
396
397 __le16 sect;
398 u8 array_id;
399 u8 reserved2;
400
401 char name[40];
402
403 __le32 array_status;
404
405
406} __attribute__((packed));
407
408static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
409static void carm_remove_one (struct pci_dev *pdev);
410static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo);
411
412static struct pci_device_id carm_pci_tbl[] = {
413 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
414 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
415 { }
416};
417MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
418
419static struct pci_driver carm_driver = {
420 .name = DRV_NAME,
421 .id_table = carm_pci_tbl,
422 .probe = carm_init_one,
423 .remove = carm_remove_one,
424};
425
426static struct block_device_operations carm_bd_ops = {
427 .owner = THIS_MODULE,
428 .getgeo = carm_bdev_getgeo,
429};
430
431static unsigned int carm_host_id;
432static unsigned long carm_major_alloc;
433
434
435
436static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
437{
438 struct carm_port *port = bdev->bd_disk->private_data;
439
440 geo->heads = (u8) port->dev_geom_head;
441 geo->sectors = (u8) port->dev_geom_sect;
442 geo->cylinders = port->dev_geom_cyl;
443 return 0;
444}
445
446static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
447
448static inline int carm_lookup_bucket(u32 msg_size)
449{
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
453 if (msg_size <= msg_sizes[i])
454 return i;
455
456 return -ENOENT;
457}
458
459static void carm_init_buckets(void __iomem *mmio)
460{
461 unsigned int i;
462
463 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
464 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
465}
466
467static inline void *carm_ref_msg(struct carm_host *host,
468 unsigned int msg_idx)
469{
470 return host->msg_base + (msg_idx * CARM_MSG_SIZE);
471}
472
473static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
474 unsigned int msg_idx)
475{
476 return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
477}
478
479static int carm_send_msg(struct carm_host *host,
480 struct carm_request *crq)
481{
482 void __iomem *mmio = host->mmio;
483 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
484 u32 cm_bucket = crq->msg_bucket;
485 u32 tmp;
486 int rc = 0;
487
488 VPRINTK("ENTER\n");
489
490 tmp = readl(mmio + CARM_HMUC);
491 if (tmp & CARM_Q_FULL) {
492#if 0
493 tmp = readl(mmio + CARM_INT_MASK);
494 tmp |= INT_Q_AVAILABLE;
495 writel(tmp, mmio + CARM_INT_MASK);
496 readl(mmio + CARM_INT_MASK);
497#endif
498 DPRINTK("host msg queue full\n");
499 rc = -EBUSY;
500 } else {
501 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
502 readl(mmio + CARM_IHQP);
503 }
504
505 return rc;
506}
507
508static struct carm_request *carm_get_request(struct carm_host *host)
509{
510 unsigned int i;
511
512
513 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
514 return NULL;
515
516 for (i = 0; i < max_queue; i++)
517 if ((host->msg_alloc & (1ULL << i)) == 0) {
518 struct carm_request *crq = &host->req[i];
519 crq->port = NULL;
520 crq->n_elem = 0;
521
522 host->msg_alloc |= (1ULL << i);
523 host->n_msgs++;
524
525 assert(host->n_msgs <= CARM_MAX_REQ);
526 sg_init_table(crq->sg, CARM_MAX_REQ_SG);
527 return crq;
528 }
529
530 DPRINTK("no request available, returning NULL\n");
531 return NULL;
532}
533
534static int carm_put_request(struct carm_host *host, struct carm_request *crq)
535{
536 assert(crq->tag < max_queue);
537
538 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
539 return -EINVAL;
540
541 assert(host->hw_sg_used >= crq->n_elem);
542
543 host->msg_alloc &= ~(1ULL << crq->tag);
544 host->hw_sg_used -= crq->n_elem;
545 host->n_msgs--;
546
547 return 0;
548}
549
550static struct carm_request *carm_get_special(struct carm_host *host)
551{
552 unsigned long flags;
553 struct carm_request *crq = NULL;
554 struct request *rq;
555 int tries = 5000;
556
557 while (tries-- > 0) {
558 spin_lock_irqsave(&host->lock, flags);
559 crq = carm_get_request(host);
560 spin_unlock_irqrestore(&host->lock, flags);
561
562 if (crq)
563 break;
564 msleep(10);
565 }
566
567 if (!crq)
568 return NULL;
569
570 rq = blk_get_request(host->oob_q, WRITE , GFP_KERNEL);
571 if (!rq) {
572 spin_lock_irqsave(&host->lock, flags);
573 carm_put_request(host, crq);
574 spin_unlock_irqrestore(&host->lock, flags);
575 return NULL;
576 }
577
578 crq->rq = rq;
579 return crq;
580}
581
582static int carm_array_info (struct carm_host *host, unsigned int array_idx)
583{
584 struct carm_msg_ioctl *ioc;
585 unsigned int idx;
586 u32 msg_data;
587 dma_addr_t msg_dma;
588 struct carm_request *crq;
589 int rc;
590
591 crq = carm_get_special(host);
592 if (!crq) {
593 rc = -ENOMEM;
594 goto err_out;
595 }
596
597 idx = crq->tag;
598
599 ioc = carm_ref_msg(host, idx);
600 msg_dma = carm_ref_msg_dma(host, idx);
601 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
602
603 crq->msg_type = CARM_MSG_ARRAY;
604 crq->msg_subtype = CARM_ARRAY_INFO;
605 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
606 sizeof(struct carm_array_info));
607 BUG_ON(rc < 0);
608 crq->msg_bucket = (u32) rc;
609
610 memset(ioc, 0, sizeof(*ioc));
611 ioc->type = CARM_MSG_ARRAY;
612 ioc->subtype = CARM_ARRAY_INFO;
613 ioc->array_id = (u8) array_idx;
614 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
615 ioc->data_addr = cpu_to_le32(msg_data);
616
617 spin_lock_irq(&host->lock);
618 assert(host->state == HST_DEV_SCAN_START ||
619 host->state == HST_DEV_SCAN);
620 spin_unlock_irq(&host->lock);
621
622 DPRINTK("blk_insert_request, tag == %u\n", idx);
623 blk_insert_request(host->oob_q, crq->rq, 1, crq);
624
625 return 0;
626
627err_out:
628 spin_lock_irq(&host->lock);
629 host->state = HST_ERROR;
630 spin_unlock_irq(&host->lock);
631 return rc;
632}
633
634typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
635
636static int carm_send_special (struct carm_host *host, carm_sspc_t func)
637{
638 struct carm_request *crq;
639 struct carm_msg_ioctl *ioc;
640 void *mem;
641 unsigned int idx, msg_size;
642 int rc;
643
644 crq = carm_get_special(host);
645 if (!crq)
646 return -ENOMEM;
647
648 idx = crq->tag;
649
650 mem = carm_ref_msg(host, idx);
651
652 msg_size = func(host, idx, mem);
653
654 ioc = mem;
655 crq->msg_type = ioc->type;
656 crq->msg_subtype = ioc->subtype;
657 rc = carm_lookup_bucket(msg_size);
658 BUG_ON(rc < 0);
659 crq->msg_bucket = (u32) rc;
660
661 DPRINTK("blk_insert_request, tag == %u\n", idx);
662 blk_insert_request(host->oob_q, crq->rq, 1, crq);
663
664 return 0;
665}
666
667static unsigned int carm_fill_sync_time(struct carm_host *host,
668 unsigned int idx, void *mem)
669{
670 struct timeval tv;
671 struct carm_msg_sync_time *st = mem;
672
673 do_gettimeofday(&tv);
674
675 memset(st, 0, sizeof(*st));
676 st->type = CARM_MSG_MISC;
677 st->subtype = MISC_SET_TIME;
678 st->handle = cpu_to_le32(TAG_ENCODE(idx));
679 st->timestamp = cpu_to_le32(tv.tv_sec);
680
681 return sizeof(struct carm_msg_sync_time);
682}
683
684static unsigned int carm_fill_alloc_buf(struct carm_host *host,
685 unsigned int idx, void *mem)
686{
687 struct carm_msg_allocbuf *ab = mem;
688
689 memset(ab, 0, sizeof(*ab));
690 ab->type = CARM_MSG_MISC;
691 ab->subtype = MISC_ALLOC_MEM;
692 ab->handle = cpu_to_le32(TAG_ENCODE(idx));
693 ab->n_sg = 1;
694 ab->sg_type = SGT_32BIT;
695 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
696 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
697 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
698 ab->n_evt = cpu_to_le32(1024);
699 ab->rbuf_pool = cpu_to_le32(host->shm_dma);
700 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
701 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
702 ab->n_msg = cpu_to_le32(CARM_Q_LEN);
703 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
704 ab->sg[0].len = cpu_to_le32(65536);
705
706 return sizeof(struct carm_msg_allocbuf);
707}
708
709static unsigned int carm_fill_scan_channels(struct carm_host *host,
710 unsigned int idx, void *mem)
711{
712 struct carm_msg_ioctl *ioc = mem;
713 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
714 IOC_SCAN_CHAN_OFFSET);
715
716 memset(ioc, 0, sizeof(*ioc));
717 ioc->type = CARM_MSG_IOCTL;
718 ioc->subtype = CARM_IOC_SCAN_CHAN;
719 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
720 ioc->data_addr = cpu_to_le32(msg_data);
721
722
723 mem += IOC_SCAN_CHAN_OFFSET;
724 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
725
726 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
727}
728
729static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
730 unsigned int idx, void *mem)
731{
732 struct carm_msg_get_fw_ver *ioc = mem;
733 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
734
735 memset(ioc, 0, sizeof(*ioc));
736 ioc->type = CARM_MSG_MISC;
737 ioc->subtype = MISC_GET_FW_VER;
738 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
739 ioc->data_addr = cpu_to_le32(msg_data);
740
741 return sizeof(struct carm_msg_get_fw_ver) +
742 sizeof(struct carm_fw_ver);
743}
744
745static inline void carm_end_request_queued(struct carm_host *host,
746 struct carm_request *crq,
747 int uptodate)
748{
749 struct request *req = crq->rq;
750 int rc;
751
752 rc = end_that_request_first(req, uptodate, req->hard_nr_sectors);
753 assert(rc == 0);
754
755 end_that_request_last(req, uptodate);
756
757 rc = carm_put_request(host, crq);
758 assert(rc == 0);
759}
760
761static inline void carm_push_q (struct carm_host *host, struct request_queue *q)
762{
763 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
764
765 blk_stop_queue(q);
766 VPRINTK("STOPPED QUEUE %p\n", q);
767
768 host->wait_q[idx] = q;
769 host->wait_q_prod++;
770 BUG_ON(host->wait_q_prod == host->wait_q_cons);
771}
772
773static inline struct request_queue *carm_pop_q(struct carm_host *host)
774{
775 unsigned int idx;
776
777 if (host->wait_q_prod == host->wait_q_cons)
778 return NULL;
779
780 idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
781 host->wait_q_cons++;
782
783 return host->wait_q[idx];
784}
785
786static inline void carm_round_robin(struct carm_host *host)
787{
788 struct request_queue *q = carm_pop_q(host);
789 if (q) {
790 blk_start_queue(q);
791 VPRINTK("STARTED QUEUE %p\n", q);
792 }
793}
794
795static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
796 int is_ok)
797{
798 carm_end_request_queued(host, crq, is_ok);
799 if (max_queue == 1)
800 carm_round_robin(host);
801 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
802 (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
803 carm_round_robin(host);
804 }
805}
806
807static void carm_oob_rq_fn(struct request_queue *q)
808{
809 struct carm_host *host = q->queuedata;
810 struct carm_request *crq;
811 struct request *rq;
812 int rc;
813
814 while (1) {
815 DPRINTK("get req\n");
816 rq = elv_next_request(q);
817 if (!rq)
818 break;
819
820 blkdev_dequeue_request(rq);
821
822 crq = rq->special;
823 assert(crq != NULL);
824 assert(crq->rq == rq);
825
826 crq->n_elem = 0;
827
828 DPRINTK("send req\n");
829 rc = carm_send_msg(host, crq);
830 if (rc) {
831 blk_requeue_request(q, rq);
832 carm_push_q(host, q);
833 return;
834 }
835 }
836}
837
838static void carm_rq_fn(struct request_queue *q)
839{
840 struct carm_port *port = q->queuedata;
841 struct carm_host *host = port->host;
842 struct carm_msg_rw *msg;
843 struct carm_request *crq;
844 struct request *rq;
845 struct scatterlist *sg;
846 int writing = 0, pci_dir, i, n_elem, rc;
847 u32 tmp;
848 unsigned int msg_size;
849
850queue_one_request:
851 VPRINTK("get req\n");
852 rq = elv_next_request(q);
853 if (!rq)
854 return;
855
856 crq = carm_get_request(host);
857 if (!crq) {
858 carm_push_q(host, q);
859 return;
860 }
861 crq->rq = rq;
862
863 blkdev_dequeue_request(rq);
864
865 if (rq_data_dir(rq) == WRITE) {
866 writing = 1;
867 pci_dir = PCI_DMA_TODEVICE;
868 } else {
869 pci_dir = PCI_DMA_FROMDEVICE;
870 }
871
872
873 sg = &crq->sg[0];
874 n_elem = blk_rq_map_sg(q, rq, sg);
875 if (n_elem <= 0) {
876 carm_end_rq(host, crq, 0);
877 return;
878 }
879
880
881 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir);
882 if (n_elem <= 0) {
883 carm_end_rq(host, crq, 0);
884 return;
885 }
886 crq->n_elem = n_elem;
887 crq->port = port;
888 host->hw_sg_used += n_elem;
889
890
891
892
893
894 VPRINTK("build msg\n");
895 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
896
897 if (writing) {
898 msg->type = CARM_MSG_WRITE;
899 crq->msg_type = CARM_MSG_WRITE;
900 } else {
901 msg->type = CARM_MSG_READ;
902 crq->msg_type = CARM_MSG_READ;
903 }
904
905 msg->id = port->port_no;
906 msg->sg_count = n_elem;
907 msg->sg_type = SGT_32BIT;
908 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
909 msg->lba = cpu_to_le32(rq->sector & 0xffffffff);
910 tmp = (rq->sector >> 16) >> 16;
911 msg->lba_high = cpu_to_le16( (u16) tmp );
912 msg->lba_count = cpu_to_le16(rq->nr_sectors);
913
914 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
915 for (i = 0; i < n_elem; i++) {
916 struct carm_msg_sg *carm_sg = &msg->sg[i];
917 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
918 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
919 msg_size += sizeof(struct carm_msg_sg);
920 }
921
922 rc = carm_lookup_bucket(msg_size);
923 BUG_ON(rc < 0);
924 crq->msg_bucket = (u32) rc;
925
926
927
928
929
930 VPRINTK("send msg, tag == %u\n", crq->tag);
931 rc = carm_send_msg(host, crq);
932 if (rc) {
933 carm_put_request(host, crq);
934 blk_requeue_request(q, rq);
935 carm_push_q(host, q);
936 return;
937 }
938
939 goto queue_one_request;
940}
941
942static void carm_handle_array_info(struct carm_host *host,
943 struct carm_request *crq, u8 *mem,
944 int is_ok)
945{
946 struct carm_port *port;
947 u8 *msg_data = mem + sizeof(struct carm_array_info);
948 struct carm_array_info *desc = (struct carm_array_info *) msg_data;
949 u64 lo, hi;
950 int cur_port;
951 size_t slen;
952
953 DPRINTK("ENTER\n");
954
955 carm_end_rq(host, crq, is_ok);
956
957 if (!is_ok)
958 goto out;
959 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
960 goto out;
961
962 cur_port = host->cur_scan_dev;
963
964
965 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
966 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
967 cur_port, (int) desc->array_id);
968 goto out;
969 }
970
971 port = &host->port[cur_port];
972
973 lo = (u64) le32_to_cpu(desc->size);
974 hi = (u64) le16_to_cpu(desc->size_hi);
975
976 port->capacity = lo | (hi << 32);
977 port->dev_geom_head = le16_to_cpu(desc->head);
978 port->dev_geom_sect = le16_to_cpu(desc->sect);
979 port->dev_geom_cyl = le16_to_cpu(desc->cyl);
980
981 host->dev_active |= (1 << cur_port);
982
983 strncpy(port->name, desc->name, sizeof(port->name));
984 port->name[sizeof(port->name) - 1] = 0;
985 slen = strlen(port->name);
986 while (slen && (port->name[slen - 1] == ' ')) {
987 port->name[slen - 1] = 0;
988 slen--;
989 }
990
991 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
992 pci_name(host->pdev), port->port_no,
993 (unsigned long long) port->capacity);
994 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
995 pci_name(host->pdev), port->port_no, port->name);
996
997out:
998 assert(host->state == HST_DEV_SCAN);
999 schedule_work(&host->fsm_task);
1000}
1001
1002static void carm_handle_scan_chan(struct carm_host *host,
1003 struct carm_request *crq, u8 *mem,
1004 int is_ok)
1005{
1006 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
1007 unsigned int i, dev_count = 0;
1008 int new_state = HST_DEV_SCAN_START;
1009
1010 DPRINTK("ENTER\n");
1011
1012 carm_end_rq(host, crq, is_ok);
1013
1014 if (!is_ok) {
1015 new_state = HST_ERROR;
1016 goto out;
1017 }
1018
1019
1020 for (i = 0; i < 8; i++)
1021 if (msg_data[i] == 0) {
1022 host->dev_present |= (1 << i);
1023 dev_count++;
1024 }
1025
1026 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
1027 pci_name(host->pdev), dev_count);
1028
1029out:
1030 assert(host->state == HST_PORT_SCAN);
1031 host->state = new_state;
1032 schedule_work(&host->fsm_task);
1033}
1034
1035static void carm_handle_generic(struct carm_host *host,
1036 struct carm_request *crq, int is_ok,
1037 int cur_state, int next_state)
1038{
1039 DPRINTK("ENTER\n");
1040
1041 carm_end_rq(host, crq, is_ok);
1042
1043 assert(host->state == cur_state);
1044 if (is_ok)
1045 host->state = next_state;
1046 else
1047 host->state = HST_ERROR;
1048 schedule_work(&host->fsm_task);
1049}
1050
1051static inline void carm_handle_rw(struct carm_host *host,
1052 struct carm_request *crq, int is_ok)
1053{
1054 int pci_dir;
1055
1056 VPRINTK("ENTER\n");
1057
1058 if (rq_data_dir(crq->rq) == WRITE)
1059 pci_dir = PCI_DMA_TODEVICE;
1060 else
1061 pci_dir = PCI_DMA_FROMDEVICE;
1062
1063 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir);
1064
1065 carm_end_rq(host, crq, is_ok);
1066}
1067
1068static inline void carm_handle_resp(struct carm_host *host,
1069 __le32 ret_handle_le, u32 status)
1070{
1071 u32 handle = le32_to_cpu(ret_handle_le);
1072 unsigned int msg_idx;
1073 struct carm_request *crq;
1074 int is_ok = (status == RMSG_OK);
1075 u8 *mem;
1076
1077 VPRINTK("ENTER, handle == 0x%x\n", handle);
1078
1079 if (unlikely(!TAG_VALID(handle))) {
1080 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
1081 pci_name(host->pdev), handle);
1082 return;
1083 }
1084
1085 msg_idx = TAG_DECODE(handle);
1086 VPRINTK("tag == %u\n", msg_idx);
1087
1088 crq = &host->req[msg_idx];
1089
1090
1091 if (likely(crq->msg_type == CARM_MSG_READ ||
1092 crq->msg_type == CARM_MSG_WRITE)) {
1093 carm_handle_rw(host, crq, is_ok);
1094 return;
1095 }
1096
1097 mem = carm_ref_msg(host, msg_idx);
1098
1099 switch (crq->msg_type) {
1100 case CARM_MSG_IOCTL: {
1101 switch (crq->msg_subtype) {
1102 case CARM_IOC_SCAN_CHAN:
1103 carm_handle_scan_chan(host, crq, mem, is_ok);
1104 break;
1105 default:
1106
1107 goto err_out;
1108 }
1109 break;
1110 }
1111
1112 case CARM_MSG_MISC: {
1113 switch (crq->msg_subtype) {
1114 case MISC_ALLOC_MEM:
1115 carm_handle_generic(host, crq, is_ok,
1116 HST_ALLOC_BUF, HST_SYNC_TIME);
1117 break;
1118 case MISC_SET_TIME:
1119 carm_handle_generic(host, crq, is_ok,
1120 HST_SYNC_TIME, HST_GET_FW_VER);
1121 break;
1122 case MISC_GET_FW_VER: {
1123 struct carm_fw_ver *ver = (struct carm_fw_ver *)
1124 mem + sizeof(struct carm_msg_get_fw_ver);
1125 if (is_ok) {
1126 host->fw_ver = le32_to_cpu(ver->version);
1127 host->flags |= (ver->features & FL_FW_VER_MASK);
1128 }
1129 carm_handle_generic(host, crq, is_ok,
1130 HST_GET_FW_VER, HST_PORT_SCAN);
1131 break;
1132 }
1133 default:
1134
1135 goto err_out;
1136 }
1137 break;
1138 }
1139
1140 case CARM_MSG_ARRAY: {
1141 switch (crq->msg_subtype) {
1142 case CARM_ARRAY_INFO:
1143 carm_handle_array_info(host, crq, mem, is_ok);
1144 break;
1145 default:
1146
1147 goto err_out;
1148 }
1149 break;
1150 }
1151
1152 default:
1153
1154 goto err_out;
1155 }
1156
1157 return;
1158
1159err_out:
1160 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1161 pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
1162 carm_end_rq(host, crq, 0);
1163}
1164
1165static inline void carm_handle_responses(struct carm_host *host)
1166{
1167 void __iomem *mmio = host->mmio;
1168 struct carm_response *resp = (struct carm_response *) host->shm;
1169 unsigned int work = 0;
1170 unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1171
1172 while (1) {
1173 u32 status = le32_to_cpu(resp[idx].status);
1174
1175 if (status == 0xffffffff) {
1176 VPRINTK("ending response on index %u\n", idx);
1177 writel(idx << 3, mmio + CARM_RESP_IDX);
1178 break;
1179 }
1180
1181
1182 else if ((status & (1 << 31)) == 0) {
1183 VPRINTK("handling msg response on index %u\n", idx);
1184 carm_handle_resp(host, resp[idx].ret_handle, status);
1185 resp[idx].status = cpu_to_le32(0xffffffff);
1186 }
1187
1188
1189 else if ((status & 0xff000000) == (1 << 31)) {
1190 u8 *evt_type_ptr = (u8 *) &resp[idx];
1191 u8 evt_type = *evt_type_ptr;
1192 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1193 pci_name(host->pdev), (int) evt_type);
1194 resp[idx].status = cpu_to_le32(0xffffffff);
1195 }
1196
1197 idx = NEXT_RESP(idx);
1198 work++;
1199 }
1200
1201 VPRINTK("EXIT, work==%u\n", work);
1202 host->resp_idx += work;
1203}
1204
1205static irqreturn_t carm_interrupt(int irq, void *__host)
1206{
1207 struct carm_host *host = __host;
1208 void __iomem *mmio;
1209 u32 mask;
1210 int handled = 0;
1211 unsigned long flags;
1212
1213 if (!host) {
1214 VPRINTK("no host\n");
1215 return IRQ_NONE;
1216 }
1217
1218 spin_lock_irqsave(&host->lock, flags);
1219
1220 mmio = host->mmio;
1221
1222
1223 mask = readl(mmio + CARM_INT_STAT);
1224
1225 if (mask == 0 || mask == 0xffffffff) {
1226 VPRINTK("no work, mask == 0x%x\n", mask);
1227 goto out;
1228 }
1229
1230 if (mask & INT_ACK_MASK)
1231 writel(mask, mmio + CARM_INT_STAT);
1232
1233 if (unlikely(host->state == HST_INVALID)) {
1234 VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1235 goto out;
1236 }
1237
1238 if (mask & CARM_HAVE_RESP) {
1239 handled = 1;
1240 carm_handle_responses(host);
1241 }
1242
1243out:
1244 spin_unlock_irqrestore(&host->lock, flags);
1245 VPRINTK("EXIT\n");
1246 return IRQ_RETVAL(handled);
1247}
1248
1249static void carm_fsm_task (struct work_struct *work)
1250{
1251 struct carm_host *host =
1252 container_of(work, struct carm_host, fsm_task);
1253 unsigned long flags;
1254 unsigned int state;
1255 int rc, i, next_dev;
1256 int reschedule = 0;
1257 int new_state = HST_INVALID;
1258
1259 spin_lock_irqsave(&host->lock, flags);
1260 state = host->state;
1261 spin_unlock_irqrestore(&host->lock, flags);
1262
1263 DPRINTK("ENTER, state == %s\n", state_name[state]);
1264
1265 switch (state) {
1266 case HST_PROBE_START:
1267 new_state = HST_ALLOC_BUF;
1268 reschedule = 1;
1269 break;
1270
1271 case HST_ALLOC_BUF:
1272 rc = carm_send_special(host, carm_fill_alloc_buf);
1273 if (rc) {
1274 new_state = HST_ERROR;
1275 reschedule = 1;
1276 }
1277 break;
1278
1279 case HST_SYNC_TIME:
1280 rc = carm_send_special(host, carm_fill_sync_time);
1281 if (rc) {
1282 new_state = HST_ERROR;
1283 reschedule = 1;
1284 }
1285 break;
1286
1287 case HST_GET_FW_VER:
1288 rc = carm_send_special(host, carm_fill_get_fw_ver);
1289 if (rc) {
1290 new_state = HST_ERROR;
1291 reschedule = 1;
1292 }
1293 break;
1294
1295 case HST_PORT_SCAN:
1296 rc = carm_send_special(host, carm_fill_scan_channels);
1297 if (rc) {
1298 new_state = HST_ERROR;
1299 reschedule = 1;
1300 }
1301 break;
1302
1303 case HST_DEV_SCAN_START:
1304 host->cur_scan_dev = -1;
1305 new_state = HST_DEV_SCAN;
1306 reschedule = 1;
1307 break;
1308
1309 case HST_DEV_SCAN:
1310 next_dev = -1;
1311 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1312 if (host->dev_present & (1 << i)) {
1313 next_dev = i;
1314 break;
1315 }
1316
1317 if (next_dev >= 0) {
1318 host->cur_scan_dev = next_dev;
1319 rc = carm_array_info(host, next_dev);
1320 if (rc) {
1321 new_state = HST_ERROR;
1322 reschedule = 1;
1323 }
1324 } else {
1325 new_state = HST_DEV_ACTIVATE;
1326 reschedule = 1;
1327 }
1328 break;
1329
1330 case HST_DEV_ACTIVATE: {
1331 int activated = 0;
1332 for (i = 0; i < CARM_MAX_PORTS; i++)
1333 if (host->dev_active & (1 << i)) {
1334 struct carm_port *port = &host->port[i];
1335 struct gendisk *disk = port->disk;
1336
1337 set_capacity(disk, port->capacity);
1338 add_disk(disk);
1339 activated++;
1340 }
1341
1342 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1343 pci_name(host->pdev), activated);
1344
1345 new_state = HST_PROBE_FINISHED;
1346 reschedule = 1;
1347 break;
1348 }
1349
1350 case HST_PROBE_FINISHED:
1351 complete(&host->probe_comp);
1352 break;
1353
1354 case HST_ERROR:
1355
1356 break;
1357
1358 default:
1359
1360 printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1361 assert(0);
1362 break;
1363 }
1364
1365 if (new_state != HST_INVALID) {
1366 spin_lock_irqsave(&host->lock, flags);
1367 host->state = new_state;
1368 spin_unlock_irqrestore(&host->lock, flags);
1369 }
1370 if (reschedule)
1371 schedule_work(&host->fsm_task);
1372}
1373
1374static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1375{
1376 unsigned int i;
1377
1378 for (i = 0; i < 50000; i++) {
1379 u32 tmp = readl(mmio + CARM_LMUC);
1380 udelay(100);
1381
1382 if (test_bit) {
1383 if ((tmp & bits) == bits)
1384 return 0;
1385 } else {
1386 if ((tmp & bits) == 0)
1387 return 0;
1388 }
1389
1390 cond_resched();
1391 }
1392
1393 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1394 bits, test_bit ? "yes" : "no");
1395 return -EBUSY;
1396}
1397
1398static void carm_init_responses(struct carm_host *host)
1399{
1400 void __iomem *mmio = host->mmio;
1401 unsigned int i;
1402 struct carm_response *resp = (struct carm_response *) host->shm;
1403
1404 for (i = 0; i < RMSG_Q_LEN; i++)
1405 resp[i].status = cpu_to_le32(0xffffffff);
1406
1407 writel(0, mmio + CARM_RESP_IDX);
1408}
1409
1410static int carm_init_host(struct carm_host *host)
1411{
1412 void __iomem *mmio = host->mmio;
1413 u32 tmp;
1414 u8 tmp8;
1415 int rc;
1416
1417 DPRINTK("ENTER\n");
1418
1419 writel(0, mmio + CARM_INT_MASK);
1420
1421 tmp8 = readb(mmio + CARM_INITC);
1422 if (tmp8 & 0x01) {
1423 tmp8 &= ~0x01;
1424 writeb(tmp8, mmio + CARM_INITC);
1425 readb(mmio + CARM_INITC);
1426
1427 DPRINTK("snooze...\n");
1428 msleep(5000);
1429 }
1430
1431 tmp = readl(mmio + CARM_HMUC);
1432 if (tmp & CARM_CME) {
1433 DPRINTK("CME bit present, waiting\n");
1434 rc = carm_init_wait(mmio, CARM_CME, 1);
1435 if (rc) {
1436 DPRINTK("EXIT, carm_init_wait 1 failed\n");
1437 return rc;
1438 }
1439 }
1440 if (tmp & CARM_RME) {
1441 DPRINTK("RME bit present, waiting\n");
1442 rc = carm_init_wait(mmio, CARM_RME, 1);
1443 if (rc) {
1444 DPRINTK("EXIT, carm_init_wait 2 failed\n");
1445 return rc;
1446 }
1447 }
1448
1449 tmp &= ~(CARM_RME | CARM_CME);
1450 writel(tmp, mmio + CARM_HMUC);
1451 readl(mmio + CARM_HMUC);
1452
1453 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1454 if (rc) {
1455 DPRINTK("EXIT, carm_init_wait 3 failed\n");
1456 return rc;
1457 }
1458
1459 carm_init_buckets(mmio);
1460
1461 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1462 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1463 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1464
1465 tmp = readl(mmio + CARM_HMUC);
1466 tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1467 writel(tmp, mmio + CARM_HMUC);
1468 readl(mmio + CARM_HMUC);
1469
1470 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1471 if (rc) {
1472 DPRINTK("EXIT, carm_init_wait 4 failed\n");
1473 return rc;
1474 }
1475
1476 writel(0, mmio + CARM_HMPHA);
1477 writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1478
1479 carm_init_responses(host);
1480
1481
1482 spin_lock_irq(&host->lock);
1483 assert(host->state == HST_INVALID);
1484 host->state = HST_PROBE_START;
1485 spin_unlock_irq(&host->lock);
1486 schedule_work(&host->fsm_task);
1487
1488 DPRINTK("EXIT\n");
1489 return 0;
1490}
1491
1492static int carm_init_disks(struct carm_host *host)
1493{
1494 unsigned int i;
1495 int rc = 0;
1496
1497 for (i = 0; i < CARM_MAX_PORTS; i++) {
1498 struct gendisk *disk;
1499 struct request_queue *q;
1500 struct carm_port *port;
1501
1502 port = &host->port[i];
1503 port->host = host;
1504 port->port_no = i;
1505
1506 disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1507 if (!disk) {
1508 rc = -ENOMEM;
1509 break;
1510 }
1511
1512 port->disk = disk;
1513 sprintf(disk->disk_name, DRV_NAME "/%u",
1514 (unsigned int) (host->id * CARM_MAX_PORTS) + i);
1515 disk->major = host->major;
1516 disk->first_minor = i * CARM_MINORS_PER_MAJOR;
1517 disk->fops = &carm_bd_ops;
1518 disk->private_data = port;
1519
1520 q = blk_init_queue(carm_rq_fn, &host->lock);
1521 if (!q) {
1522 rc = -ENOMEM;
1523 break;
1524 }
1525 disk->queue = q;
1526 blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG);
1527 blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG);
1528 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1529
1530 q->queuedata = port;
1531 }
1532
1533 return rc;
1534}
1535
1536static void carm_free_disks(struct carm_host *host)
1537{
1538 unsigned int i;
1539
1540 for (i = 0; i < CARM_MAX_PORTS; i++) {
1541 struct gendisk *disk = host->port[i].disk;
1542 if (disk) {
1543 struct request_queue *q = disk->queue;
1544
1545 if (disk->flags & GENHD_FL_UP)
1546 del_gendisk(disk);
1547 if (q)
1548 blk_cleanup_queue(q);
1549 put_disk(disk);
1550 }
1551 }
1552}
1553
1554static int carm_init_shm(struct carm_host *host)
1555{
1556 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE,
1557 &host->shm_dma);
1558 if (!host->shm)
1559 return -ENOMEM;
1560
1561 host->msg_base = host->shm + RBUF_LEN;
1562 host->msg_dma = host->shm_dma + RBUF_LEN;
1563
1564 memset(host->shm, 0xff, RBUF_LEN);
1565 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1566
1567 return 0;
1568}
1569
1570static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1571{
1572 static unsigned int printed_version;
1573 struct carm_host *host;
1574 unsigned int pci_dac;
1575 int rc;
1576 struct request_queue *q;
1577 unsigned int i;
1578
1579 if (!printed_version++)
1580 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1581
1582 rc = pci_enable_device(pdev);
1583 if (rc)
1584 return rc;
1585
1586 rc = pci_request_regions(pdev, DRV_NAME);
1587 if (rc)
1588 goto err_out;
1589
1590#ifdef IF_64BIT_DMA_IS_POSSIBLE
1591 rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1592 if (!rc) {
1593 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1594 if (rc) {
1595 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n",
1596 pci_name(pdev));
1597 goto err_out_regions;
1598 }
1599 pci_dac = 1;
1600 } else {
1601#endif
1602 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1603 if (rc) {
1604 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1605 pci_name(pdev));
1606 goto err_out_regions;
1607 }
1608 pci_dac = 0;
1609#ifdef IF_64BIT_DMA_IS_POSSIBLE
1610 }
1611#endif
1612
1613 host = kzalloc(sizeof(*host), GFP_KERNEL);
1614 if (!host) {
1615 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1616 pci_name(pdev));
1617 rc = -ENOMEM;
1618 goto err_out_regions;
1619 }
1620
1621 host->pdev = pdev;
1622 host->flags = pci_dac ? FL_DAC : 0;
1623 spin_lock_init(&host->lock);
1624 INIT_WORK(&host->fsm_task, carm_fsm_task);
1625 init_completion(&host->probe_comp);
1626
1627 for (i = 0; i < ARRAY_SIZE(host->req); i++)
1628 host->req[i].tag = i;
1629
1630 host->mmio = ioremap(pci_resource_start(pdev, 0),
1631 pci_resource_len(pdev, 0));
1632 if (!host->mmio) {
1633 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1634 pci_name(pdev));
1635 rc = -ENOMEM;
1636 goto err_out_kfree;
1637 }
1638
1639 rc = carm_init_shm(host);
1640 if (rc) {
1641 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1642 pci_name(pdev));
1643 goto err_out_iounmap;
1644 }
1645
1646 q = blk_init_queue(carm_oob_rq_fn, &host->lock);
1647 if (!q) {
1648 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
1649 pci_name(pdev));
1650 rc = -ENOMEM;
1651 goto err_out_pci_free;
1652 }
1653 host->oob_q = q;
1654 q->queuedata = host;
1655
1656
1657
1658
1659 if (!test_and_set_bit(0, &carm_major_alloc))
1660 host->major = 160;
1661 else if (!test_and_set_bit(1, &carm_major_alloc))
1662 host->major = 161;
1663 else
1664 host->flags |= FL_DYN_MAJOR;
1665
1666 host->id = carm_host_id;
1667 sprintf(host->name, DRV_NAME "%d", carm_host_id);
1668
1669 rc = register_blkdev(host->major, host->name);
1670 if (rc < 0)
1671 goto err_out_free_majors;
1672 if (host->flags & FL_DYN_MAJOR)
1673 host->major = rc;
1674
1675 rc = carm_init_disks(host);
1676 if (rc)
1677 goto err_out_blkdev_disks;
1678
1679 pci_set_master(pdev);
1680
1681 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host);
1682 if (rc) {
1683 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1684 pci_name(pdev));
1685 goto err_out_blkdev_disks;
1686 }
1687
1688 rc = carm_init_host(host);
1689 if (rc)
1690 goto err_out_free_irq;
1691
1692 DPRINTK("waiting for probe_comp\n");
1693 wait_for_completion(&host->probe_comp);
1694
1695 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n",
1696 host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
1697 (unsigned long long)pci_resource_start(pdev, 0),
1698 pdev->irq, host->major);
1699
1700 carm_host_id++;
1701 pci_set_drvdata(pdev, host);
1702 return 0;
1703
1704err_out_free_irq:
1705 free_irq(pdev->irq, host);
1706err_out_blkdev_disks:
1707 carm_free_disks(host);
1708 unregister_blkdev(host->major, host->name);
1709err_out_free_majors:
1710 if (host->major == 160)
1711 clear_bit(0, &carm_major_alloc);
1712 else if (host->major == 161)
1713 clear_bit(1, &carm_major_alloc);
1714 blk_cleanup_queue(host->oob_q);
1715err_out_pci_free:
1716 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1717err_out_iounmap:
1718 iounmap(host->mmio);
1719err_out_kfree:
1720 kfree(host);
1721err_out_regions:
1722 pci_release_regions(pdev);
1723err_out:
1724 pci_disable_device(pdev);
1725 return rc;
1726}
1727
1728static void carm_remove_one (struct pci_dev *pdev)
1729{
1730 struct carm_host *host = pci_get_drvdata(pdev);
1731
1732 if (!host) {
1733 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1734 pci_name(pdev));
1735 return;
1736 }
1737
1738 free_irq(pdev->irq, host);
1739 carm_free_disks(host);
1740 unregister_blkdev(host->major, host->name);
1741 if (host->major == 160)
1742 clear_bit(0, &carm_major_alloc);
1743 else if (host->major == 161)
1744 clear_bit(1, &carm_major_alloc);
1745 blk_cleanup_queue(host->oob_q);
1746 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1747 iounmap(host->mmio);
1748 kfree(host);
1749 pci_release_regions(pdev);
1750 pci_disable_device(pdev);
1751 pci_set_drvdata(pdev, NULL);
1752}
1753
1754static int __init carm_init(void)
1755{
1756 return pci_register_driver(&carm_driver);
1757}
1758
1759static void __exit carm_exit(void)
1760{
1761 pci_unregister_driver(&carm_driver);
1762}
1763
1764module_init(carm_init);
1765module_exit(carm_exit);
1766
1767
1768
