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29#ifndef _AGP_BACKEND_PRIV_H
30#define _AGP_BACKEND_PRIV_H 1
31
32#include <asm/agp.h>
33
34#define PFX "agpgart: "
35
36
37#ifdef AGP_DEBUG
38#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __FUNCTION__ , ## y)
39#else
40#define DBG(x,y...) do { } while (0)
41#endif
42
43extern struct agp_bridge_data *agp_bridge;
44
45enum aper_size_type {
46 U8_APER_SIZE,
47 U16_APER_SIZE,
48 U32_APER_SIZE,
49 LVL2_APER_SIZE,
50 FIXED_APER_SIZE
51};
52
53struct gatt_mask {
54 unsigned long mask;
55 u32 type;
56
57
58
59};
60
61#define AGP_PAGE_DESTROY_UNMAP 1
62#define AGP_PAGE_DESTROY_FREE 2
63
64struct aper_size_info_8 {
65 int size;
66 int num_entries;
67 int page_order;
68 u8 size_value;
69};
70
71struct aper_size_info_16 {
72 int size;
73 int num_entries;
74 int page_order;
75 u16 size_value;
76};
77
78struct aper_size_info_32 {
79 int size;
80 int num_entries;
81 int page_order;
82 u32 size_value;
83};
84
85struct aper_size_info_lvl2 {
86 int size;
87 int num_entries;
88 u32 size_value;
89};
90
91struct aper_size_info_fixed {
92 int size;
93 int num_entries;
94 int page_order;
95};
96
97struct agp_bridge_driver {
98 struct module *owner;
99 const void *aperture_sizes;
100 int num_aperture_sizes;
101 enum aper_size_type size_type;
102 int cant_use_aperture;
103 int needs_scratch_page;
104 const struct gatt_mask *masks;
105 int (*fetch_size)(void);
106 int (*configure)(void);
107 void (*agp_enable)(struct agp_bridge_data *, u32);
108 void (*cleanup)(void);
109 void (*tlb_flush)(struct agp_memory *);
110 unsigned long (*mask_memory)(struct agp_bridge_data *, unsigned long, int);
111 void (*cache_flush)(void);
112 int (*create_gatt_table)(struct agp_bridge_data *);
113 int (*free_gatt_table)(struct agp_bridge_data *);
114 int (*insert_memory)(struct agp_memory *, off_t, int);
115 int (*remove_memory)(struct agp_memory *, off_t, int);
116 struct agp_memory *(*alloc_by_type) (size_t, int);
117 void (*free_by_type)(struct agp_memory *);
118 void *(*agp_alloc_page)(struct agp_bridge_data *);
119 void (*agp_destroy_page)(void *, int flags);
120 int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
121};
122
123struct agp_bridge_data {
124 const struct agp_version *version;
125 const struct agp_bridge_driver *driver;
126 struct vm_operations_struct *vm_ops;
127 void *previous_size;
128 void *current_size;
129 void *dev_private_data;
130 struct pci_dev *dev;
131 u32 __iomem *gatt_table;
132 u32 *gatt_table_real;
133 unsigned long scratch_page;
134 unsigned long scratch_page_real;
135 unsigned long gart_bus_addr;
136 unsigned long gatt_bus_addr;
137 u32 mode;
138 enum chipset_type type;
139 unsigned long *key_list;
140 atomic_t current_memory_agp;
141 atomic_t agp_in_use;
142 int max_memory_agp;
143 int aperture_size_idx;
144 int capndx;
145 int flags;
146 char major_version;
147 char minor_version;
148 struct list_head list;
149 u32 apbase_config;
150};
151
152#define KB(x) ((x) * 1024)
153#define MB(x) (KB (KB (x)))
154#define GB(x) (MB (KB (x)))
155
156#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
157#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
158#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
159#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
160#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
161#define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i)
162#define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i)
163#define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i)
164#define MAXKEY (4096 * 32)
165
166#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
167
168
169
170#define INTEL_APSIZE 0xb4
171#define INTEL_ATTBASE 0xb8
172#define INTEL_AGPCTRL 0xb0
173#define INTEL_NBXCFG 0x50
174#define INTEL_ERRSTS 0x91
175
176
177#define I830_GMCH_CTRL 0x52
178#define I830_GMCH_ENABLED 0x4
179#define I830_GMCH_MEM_MASK 0x1
180#define I830_GMCH_MEM_64M 0x1
181#define I830_GMCH_MEM_128M 0
182#define I830_GMCH_GMS_MASK 0x70
183#define I830_GMCH_GMS_DISABLED 0x00
184#define I830_GMCH_GMS_LOCAL 0x10
185#define I830_GMCH_GMS_STOLEN_512 0x20
186#define I830_GMCH_GMS_STOLEN_1024 0x30
187#define I830_GMCH_GMS_STOLEN_8192 0x40
188#define I830_RDRAM_CHANNEL_TYPE 0x03010
189#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
190#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
191
192
193#define INTEL_I830_ERRSTS 0x92
194
195
196#define I855_GMCH_GMS_MASK 0xF0
197#define I855_GMCH_GMS_STOLEN_0M 0x0
198#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
199#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
200#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
201#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
202#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
203#define I85X_CAPID 0x44
204#define I85X_VARIANT_MASK 0x7
205#define I85X_VARIANT_SHIFT 5
206#define I855_GME 0x0
207#define I855_GM 0x4
208#define I852_GME 0x2
209#define I852_GM 0x5
210
211
212#define INTEL_I845_AGPM 0x51
213#define INTEL_I845_ERRSTS 0xc8
214
215
216#define INTEL_I860_MCHCFG 0x50
217#define INTEL_I860_ERRSTS 0xc8
218
219
220#define I810_GMADDR 0x10
221#define I810_MMADDR 0x14
222#define I810_PTE_BASE 0x10000
223#define I810_PTE_MAIN_UNCACHED 0x00000000
224#define I810_PTE_LOCAL 0x00000002
225#define I810_PTE_VALID 0x00000001
226#define I830_PTE_SYSTEM_CACHED 0x00000006
227#define I810_SMRAM_MISCC 0x70
228#define I810_GFX_MEM_WIN_SIZE 0x00010000
229#define I810_GFX_MEM_WIN_32M 0x00010000
230#define I810_GMS 0x000000c0
231#define I810_GMS_DISABLE 0x00000000
232#define I810_PGETBL_CTL 0x2020
233#define I810_PGETBL_ENABLED 0x00000001
234#define I965_PGETBL_SIZE_MASK 0x0000000e
235#define I965_PGETBL_SIZE_512KB (0 << 1)
236#define I965_PGETBL_SIZE_256KB (1 << 1)
237#define I965_PGETBL_SIZE_128KB (2 << 1)
238#define G33_PGETBL_SIZE_MASK (3 << 8)
239#define G33_PGETBL_SIZE_1M (1 << 8)
240#define G33_PGETBL_SIZE_2M (2 << 8)
241
242#define I810_DRAM_CTL 0x3000
243#define I810_DRAM_ROW_0 0x00000001
244#define I810_DRAM_ROW_0_SDRAM 0x00000001
245
246struct agp_device_ids {
247 unsigned short device_id;
248 enum chipset_type chipset;
249 const char *chipset_name;
250 int (*chipset_setup) (struct pci_dev *pdev);
251};
252
253
254struct agp_bridge_data *agp_alloc_bridge(void);
255void agp_put_bridge(struct agp_bridge_data *bridge);
256int agp_add_bridge(struct agp_bridge_data *bridge);
257void agp_remove_bridge(struct agp_bridge_data *bridge);
258
259
260int agp_frontend_initialize(void);
261void agp_frontend_cleanup(void);
262
263
264void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
265int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
266int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
267struct agp_memory *agp_create_memory(int scratch_pages);
268int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
269int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
270struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
271void agp_generic_free_by_type(struct agp_memory *curr);
272void *agp_generic_alloc_page(struct agp_bridge_data *bridge);
273void agp_generic_destroy_page(void *addr, int flags);
274void agp_free_key(int key);
275int agp_num_entries(void);
276u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
277void agp_device_command(u32 command, int agp_v3);
278int agp_3_5_enable(struct agp_bridge_data *bridge);
279void global_cache_flush(void);
280void get_agp_version(struct agp_bridge_data *bridge);
281unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
282 unsigned long addr, int type);
283int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
284 int type);
285struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
286
287
288struct agp_memory *agp_generic_alloc_user(size_t page_count, int type);
289void agp_alloc_page_array(size_t size, struct agp_memory *mem);
290void agp_free_page_array(struct agp_memory *mem);
291
292
293
294int agp3_generic_fetch_size(void);
295void agp3_generic_tlbflush(struct agp_memory *mem);
296int agp3_generic_configure(void);
297void agp3_generic_cleanup(void);
298
299
300#define AGP_GENERIC_SIZES_ENTRIES 11
301extern const struct aper_size_info_16 agp3_generic_sizes[];
302
303#define virt_to_gart(x) (phys_to_gart(virt_to_phys(x)))
304#define gart_to_virt(x) (phys_to_virt(gart_to_phys(x)))
305
306extern int agp_off;
307extern int agp_try_unsupported_boot;
308
309long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
310
311
312#define AGP_APBASE 0x10
313
314#define AGPSTAT 0x4
315#define AGPCMD 0x8
316#define AGPNISTAT 0xc
317#define AGPCTRL 0x10
318#define AGPAPSIZE 0x14
319#define AGPNEPG 0x16
320#define AGPGARTLO 0x18
321#define AGPGARTHI 0x1c
322#define AGPNICMD 0x20
323
324#define AGP_MAJOR_VERSION_SHIFT (20)
325#define AGP_MINOR_VERSION_SHIFT (16)
326
327#define AGPSTAT_RQ_DEPTH (0xff000000)
328#define AGPSTAT_RQ_DEPTH_SHIFT 24
329
330#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10)
331#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13)
332#define AGPSTAT_ARQSZ_SHIFT 13
333
334#define AGPSTAT_SBA (1<<9)
335#define AGPSTAT_AGP_ENABLE (1<<8)
336#define AGPSTAT_FW (1<<4)
337#define AGPSTAT_MODE_3_0 (1<<3)
338
339#define AGPSTAT2_1X (1<<0)
340#define AGPSTAT2_2X (1<<1)
341#define AGPSTAT2_4X (1<<2)
342
343#define AGPSTAT3_RSVD (1<<2)
344#define AGPSTAT3_8X (1<<1)
345#define AGPSTAT3_4X (1)
346
347#define AGPCTRL_APERENB (1<<8)
348#define AGPCTRL_GTLBEN (1<<7)
349
350#define AGP2_RESERVED_MASK 0x00fffcc8
351#define AGP3_RESERVED_MASK 0x00ff00c4
352
353#define AGP_ERRATA_FASTWRITES 1<<0
354#define AGP_ERRATA_SBA 1<<1
355#define AGP_ERRATA_1X 1<<2
356
357#endif
358
