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12#define REG_Y0BAR 0x00
13#define REG_Y1BAR 0x04
14#define REG_Y2BAR 0x08
15
16
17#define REG_IMGPITCH 0x24
18#define IMGP_YP_SHFT 2
19#define IMGP_YP_MASK 0x00003ffc
20#define IMGP_UVP_SHFT 18
21#define IMGP_UVP_MASK 0x3ffc0000
22#define REG_IRQSTATRAW 0x28
23#define IRQ_EOF0 0x00000001
24#define IRQ_EOF1 0x00000002
25#define IRQ_EOF2 0x00000004
26#define IRQ_SOF0 0x00000008
27#define IRQ_SOF1 0x00000010
28#define IRQ_SOF2 0x00000020
29#define IRQ_OVERFLOW 0x00000040
30#define IRQ_TWSIW 0x00010000
31#define IRQ_TWSIR 0x00020000
32#define IRQ_TWSIE 0x00040000
33#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
34#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
35#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
36#define REG_IRQMASK 0x2c
37#define REG_IRQSTAT 0x30
38
39#define REG_IMGSIZE 0x34
40#define IMGSZ_V_MASK 0x1fff0000
41#define IMGSZ_V_SHIFT 16
42#define IMGSZ_H_MASK 0x00003fff
43#define REG_IMGOFFSET 0x38
44
45#define REG_CTRL0 0x3c
46#define C0_ENABLE 0x00000001
47
48
49#define C0_DF_MASK 0x00fffffc
50
51
52#define C0_RGB4_RGBX 0x00000000
53#define C0_RGB4_XRGB 0x00000004
54#define C0_RGB4_BGRX 0x00000008
55#define C0_RGB4_XBGR 0x0000000c
56#define C0_RGB5_RGGB 0x00000000
57#define C0_RGB5_GRBG 0x00000004
58#define C0_RGB5_GBRG 0x00000008
59#define C0_RGB5_BGGR 0x0000000c
60
61
62
63#define C0_DF_YUV 0x00000000
64#define C0_DF_RGB 0x000000a0
65#define C0_DF_BAYER 0x00000140
66
67#define C0_RGBF_565 0x00000000
68#define C0_RGBF_444 0x00000800
69#define C0_RGB_BGR 0x00001000
70#define C0_YUV_PLANAR 0x00000000
71#define C0_YUV_PACKED 0x00008000
72#define C0_YUV_420PL 0x0000a000
73
74#define C0_YUVE_YUYV 0x00000000
75#define C0_YUVE_YVYU 0x00010000
76#define C0_YUVE_VYUY 0x00020000
77#define C0_YUVE_UYVY 0x00030000
78#define C0_YUVE_XYUV 0x00000000
79#define C0_YUVE_XYVU 0x00010000
80#define C0_YUVE_XUVY 0x00020000
81#define C0_YUVE_XVUY 0x00030000
82
83#define C0_HPOL_LOW 0x01000000
84#define C0_VPOL_LOW 0x02000000
85#define C0_VCLK_LOW 0x04000000
86#define C0_DOWNSCALE 0x08000000
87#define C0_SIFM_MASK 0xc0000000
88#define C0_SIF_HVSYNC 0x00000000
89#define CO_SOF_NOSYNC 0x40000000
90
91
92#define REG_CTRL1 0x40
93#define C1_444ALPHA 0x00f00000
94#define C1_ALPHA_SHFT 20
95#define C1_DMAB32 0x00000000
96#define C1_DMAB16 0x02000000
97#define C1_DMAB64 0x04000000
98#define C1_DMAB_MASK 0x06000000
99#define C1_TWOBUFS 0x08000000
100#define C1_PWRDWN 0x10000000
101
102#define REG_CLKCTRL 0x88
103#define CLK_DIV_MASK 0x0000ffff
104
105#define REG_GPR 0xb4
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108
109#define GPR_C1EN 0x00000020
110#define GPR_C0EN 0x00000010
111#define GPR_C1 0x00000002
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116
117#define GPR_C0 0x00000001
118
119#define REG_TWSIC0 0xb8
120#define TWSIC0_EN 0x00000001
121#define TWSIC0_MODE 0x00000002
122#define TWSIC0_SID 0x000003fc
123#define TWSIC0_SID_SHIFT 2
124#define TWSIC0_CLKDIV 0x0007fc00
125#define TWSIC0_MASKACK 0x00400000
126#define TWSIC0_OVMAGIC 0x00800000
127
128#define REG_TWSIC1 0xbc
129#define TWSIC1_DATA 0x0000ffff
130#define TWSIC1_ADDR 0x00ff0000
131#define TWSIC1_ADDR_SHIFT 16
132#define TWSIC1_READ 0x01000000
133#define TWSIC1_WSTAT 0x02000000
134#define TWSIC1_RVALID 0x04000000
135#define TWSIC1_ERROR 0x08000000
136
137
138#define REG_UBAR 0xc4
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142
143
144#define REG_GL_CSR 0x3004
145#define GCSR_SRS 0x00000001
146#define GCSR_SRC 0x00000002
147#define GCSR_MRS 0x00000004
148#define GCSR_MRC 0x00000008
149#define GCSR_CCIC_EN 0x00004000
150#define REG_GL_IMASK 0x300c
151#define GIMSK_CCIC_EN 0x00000004
152
153#define REG_GL_FCR 0x3038
154#define GFCR_GPIO_ON 0x08
155#define REG_GL_GPIOR 0x315c
156#define GGPIO_OUT 0x80000
157#define GGPIO_VAL 0x00008
158
159#define REG_LEN REG_GL_IMASK + 4
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164
165#define VGA_WIDTH 640
166#define VGA_HEIGHT 480
167