LXR linux/drivers/net/ixgbe/ixgbe

   1/*******************************************************************************
   2
   3  Intel 10 Gigabit PCI Express Linux driver
   4  Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  Linux NICS <linux.nics@intel.com>
  24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27*******************************************************************************/
  28
  29#ifndef _IXGBE_TYPE_H_
  30#define _IXGBE_TYPE_H_
  31
  32#include <linux/types.h>
  33
  34/* Vendor ID */
  35#define IXGBE_INTEL_VENDOR_ID   0x8086
  36
  37/* Device IDs */
  38#define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
  39#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
  40#define IXGBE_DEV_ID_82598AT_DUAL_PORT   0x10C8
  41#define IXGBE_DEV_ID_82598EB_CX4         0x10DD
  42
  43/* General Registers */
  44#define IXGBE_CTRL      0x00000
  45#define IXGBE_STATUS    0x00008
  46#define IXGBE_CTRL_EXT  0x00018
  47#define IXGBE_ESDP      0x00020
  48#define IXGBE_EODSDP    0x00028
  49#define IXGBE_LEDCTL    0x00200
  50#define IXGBE_FRTIMER   0x00048
  51#define IXGBE_TCPTIMER  0x0004C
  52
  53/* NVM Registers */
  54#define IXGBE_EEC       0x10010
  55#define IXGBE_EERD      0x10014
  56#define IXGBE_FLA       0x1001C
  57#define IXGBE_EEMNGCTL  0x10110
  58#define IXGBE_EEMNGDATA 0x10114
  59#define IXGBE_FLMNGCTL  0x10118
  60#define IXGBE_FLMNGDATA 0x1011C
  61#define IXGBE_FLMNGCNT  0x10120
  62#define IXGBE_FLOP      0x1013C
  63#define IXGBE_GRC       0x10200
  64
  65/* Interrupt Registers */
  66#define IXGBE_EICR      0x00800
  67#define IXGBE_EICS      0x00808
  68#define IXGBE_EIMS      0x00880
  69#define IXGBE_EIMC      0x00888
  70#define IXGBE_EIAC      0x00810
  71#define IXGBE_EIAM      0x00890
  72#define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */
  73#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
  74#define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
  75#define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
  76#define IXGBE_PBACL     0x11068
  77#define IXGBE_GPIE      0x00898
  78
  79/* Flow Control Registers */
  80#define IXGBE_PFCTOP    0x03008
  81#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
  82#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
  83#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
  84#define IXGBE_FCRTV     0x032A0
  85#define IXGBE_TFCS      0x0CE00
  86
  87/* Receive DMA Registers */
  88#define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/
  89#define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40))
  90#define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40))
  91#define IXGBE_RDH(_i)   (0x01010 + ((_i) * 0x40))
  92#define IXGBE_RDT(_i)   (0x01018 + ((_i) * 0x40))
  93#define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40))
  94#define IXGBE_RSCCTL(_i) (0x0102C + ((_i) * 0x40))
  95#define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4))
  96                                             /* array of 16 (0x02100-0x0213C) */
  97#define IXGBE_DCA_RXCTRL(_i)    (0x02200 + ((_i) * 4))
  98                                             /* array of 16 (0x02200-0x0223C) */
  99#define IXGBE_RDRXCTL    0x02F00
 100#define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 101                                             /* 8 of these 0x03C00 - 0x03C1C */
 102#define IXGBE_RXCTRL    0x03000
 103#define IXGBE_DROPEN    0x03D04
 104#define IXGBE_RXPBSIZE_SHIFT 10
 105
 106/* Receive Registers */
 107#define IXGBE_RXCSUM    0x05000
 108#define IXGBE_RFCTL     0x05008
 109#define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
 110                                   /* Multicast Table Array - 128 entries */
 111#define IXGBE_RAL(_i)   (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */
 112#define IXGBE_RAH(_i)   (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */
 113#define IXGBE_PSRTYPE   0x05480
 114                                   /* 0x5480-0x54BC Packet split receive type */
 115#define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
 116                                         /* array of 4096 1-bit vlan filters */
 117#define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 118                                     /*array of 4096 4-bit vlan vmdq indicies */
 119#define IXGBE_FCTRL     0x05080
 120#define IXGBE_VLNCTRL   0x05088
 121#define IXGBE_MCSTCTRL  0x05090
 122#define IXGBE_MRQC      0x05818
 123#define IXGBE_VMD_CTL   0x0581C
 124#define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 125#define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 126#define IXGBE_IMIRVP    0x05AC0
 127#define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 128#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 129
 130/* Transmit DMA registers */
 131#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/
 132#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
 133#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
 134#define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
 135#define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
 136#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
 137#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
 138#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
 139#define IXGBE_DTXCTL    0x07E00
 140#define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4))
 141                                              /* there are 16 of these (0-15) */
 142#define IXGBE_TIPG      0x0CB00
 143#define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) *0x04))
 144                                                      /* there are 8 of these */
 145#define IXGBE_MNGTXMAP  0x0CD10
 146#define IXGBE_TIPG_FIBER_DEFAULT 3
 147#define IXGBE_TXPBSIZE_SHIFT    10
 148
 149/* Wake up registers */
 150#define IXGBE_WUC       0x05800
 151#define IXGBE_WUFC      0x05808
 152#define IXGBE_WUS       0x05810
 153#define IXGBE_IPAV      0x05838
 154#define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 155#define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 156#define IXGBE_WUPL      0x05900
 157#define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 158#define IXGBE_FHFT      0x09000 /* Flex host filter table 9000-93FC */
 159
 160/* Music registers */
 161#define IXGBE_RMCS      0x03D00
 162#define IXGBE_DPMCS     0x07F40
 163#define IXGBE_PDPMCS    0x0CD00
 164#define IXGBE_RUPPBMR   0x050A0
 165#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 166#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 167#define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 168#define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 169#define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 170#define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 171
 172/* Stats registers */
 173#define IXGBE_CRCERRS   0x04000
 174#define IXGBE_ILLERRC   0x04004
 175#define IXGBE_ERRBC     0x04008
 176#define IXGBE_MSPDC     0x04010
 177#define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 178#define IXGBE_MLFC      0x04034
 179#define IXGBE_MRFC      0x04038
 180#define IXGBE_RLEC      0x04040
 181#define IXGBE_LXONTXC   0x03F60
 182#define IXGBE_LXONRXC   0x0CF60
 183#define IXGBE_LXOFFTXC  0x03F68
 184#define IXGBE_LXOFFRXC  0x0CF68
 185#define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 186#define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 187#define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 188#define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 189#define IXGBE_PRC64     0x0405C
 190#define IXGBE_PRC127    0x04060
 191#define IXGBE_PRC255    0x04064
 192#define IXGBE_PRC511    0x04068
 193#define IXGBE_PRC1023   0x0406C
 194#define IXGBE_PRC1522   0x04070
 195#define IXGBE_GPRC      0x04074
 196#define IXGBE_BPRC      0x04078
 197#define IXGBE_MPRC      0x0407C
 198#define IXGBE_GPTC      0x04080
 199#define IXGBE_GORCL     0x04088
 200#define IXGBE_GORCH     0x0408C
 201#define IXGBE_GOTCL     0x04090
 202#define IXGBE_GOTCH     0x04094
 203#define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 204#define IXGBE_RUC       0x040A4
 205#define IXGBE_RFC       0x040A8
 206#define IXGBE_ROC       0x040AC
 207#define IXGBE_RJC       0x040B0
 208#define IXGBE_MNGPRC    0x040B4
 209#define IXGBE_MNGPDC    0x040B8
 210#define IXGBE_MNGPTC    0x0CF90
 211#define IXGBE_TORL      0x040C0
 212#define IXGBE_TORH      0x040C4
 213#define IXGBE_TPR       0x040D0
 214#define IXGBE_TPT       0x040D4
 215#define IXGBE_PTC64     0x040D8
 216#define IXGBE_PTC127    0x040DC
 217#define IXGBE_PTC255    0x040E0
 218#define IXGBE_PTC511    0x040E4
 219#define IXGBE_PTC1023   0x040E8
 220#define IXGBE_PTC1522   0x040EC
 221#define IXGBE_MPTC      0x040F0
 222#define IXGBE_BPTC      0x040F4
 223#define IXGBE_XEC       0x04120
 224
 225#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
 226#define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */
 227
 228#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
 229#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
 230#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 231#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
 232
 233/* Management */
 234#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 235#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 236#define IXGBE_MANC      0x05820
 237#define IXGBE_MFVAL     0x05824
 238#define IXGBE_MANC2H    0x05860
 239#define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 240#define IXGBE_MIPAF     0x058B0
 241#define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 242#define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 243#define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
 244
 245/* ARC Subsystem registers */
 246#define IXGBE_HICR      0x15F00
 247#define IXGBE_FWSTS     0x15F0C
 248#define IXGBE_HSMC0R    0x15F04
 249#define IXGBE_HSMC1R    0x15F08
 250#define IXGBE_SWSR      0x15F10
 251#define IXGBE_HFDR      0x15FE8
 252#define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
 253
 254/* PCI-E registers */
 255#define IXGBE_GCR       0x11000
 256#define IXGBE_GTV       0x11004
 257#define IXGBE_FUNCTAG   0x11008
 258#define IXGBE_GLT       0x1100C
 259#define IXGBE_GSCL_1    0x11010
 260#define IXGBE_GSCL_2    0x11014
 261#define IXGBE_GSCL_3    0x11018
 262#define IXGBE_GSCL_4    0x1101C
 263#define IXGBE_GSCN_0    0x11020
 264#define IXGBE_GSCN_1    0x11024
 265#define IXGBE_GSCN_2    0x11028
 266#define IXGBE_GSCN_3    0x1102C
 267#define IXGBE_FACTPS    0x10150
 268#define IXGBE_PCIEANACTL  0x11040
 269#define IXGBE_SWSM      0x10140
 270#define IXGBE_FWSM      0x10148
 271#define IXGBE_GSSR      0x10160
 272#define IXGBE_MREVID    0x11064
 273#define IXGBE_DCA_ID    0x11070
 274#define IXGBE_DCA_CTRL  0x11074
 275
 276/* Diagnostic Registers */
 277#define IXGBE_RDSTATCTL 0x02C20
 278#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
 279#define IXGBE_RDHMPN    0x02F08
 280#define IXGBE_RIC_DW0   0x02F10
 281#define IXGBE_RIC_DW1   0x02F14
 282#define IXGBE_RIC_DW2   0x02F18
 283#define IXGBE_RIC_DW3   0x02F1C
 284#define IXGBE_RDPROBE   0x02F20
 285#define IXGBE_TDSTATCTL 0x07C20
 286#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
 287#define IXGBE_TDHMPN    0x07F08
 288#define IXGBE_TIC_DW0   0x07F10
 289#define IXGBE_TIC_DW1   0x07F14
 290#define IXGBE_TIC_DW2   0x07F18
 291#define IXGBE_TIC_DW3   0x07F1C
 292#define IXGBE_TDPROBE   0x07F20
 293#define IXGBE_TXBUFCTRL 0x0C600
 294#define IXGBE_TXBUFDATA0  0x0C610
 295#define IXGBE_TXBUFDATA1  0x0C614
 296#define IXGBE_TXBUFDATA2  0x0C618
 297#define IXGBE_TXBUFDATA3  0x0C61C
 298#define IXGBE_RXBUFCTRL   0x03600
 299#define IXGBE_RXBUFDATA0  0x03610
 300#define IXGBE_RXBUFDATA1  0x03614
 301#define IXGBE_RXBUFDATA2  0x03618
 302#define IXGBE_RXBUFDATA3  0x0361C
 303#define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
 304#define IXGBE_RFVAL     0x050A4
 305#define IXGBE_MDFTC1    0x042B8
 306#define IXGBE_MDFTC2    0x042C0
 307#define IXGBE_MDFTFIFO1 0x042C4
 308#define IXGBE_MDFTFIFO2 0x042C8
 309#define IXGBE_MDFTS     0x042CC
 310#define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
 311#define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
 312#define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
 313#define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
 314#define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
 315#define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
 316#define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
 317#define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
 318#define IXGBE_PCIEECCCTL 0x1106C
 319#define IXGBE_PBTXECC   0x0C300
 320#define IXGBE_PBRXECC   0x03300
 321#define IXGBE_GHECCR    0x110B0
 322
 323/* MAC Registers */
 324#define IXGBE_PCS1GCFIG 0x04200
 325#define IXGBE_PCS1GLCTL 0x04208
 326#define IXGBE_PCS1GLSTA 0x0420C
 327#define IXGBE_PCS1GDBG0 0x04210
 328#define IXGBE_PCS1GDBG1 0x04214
 329#define IXGBE_PCS1GANA  0x04218
 330#define IXGBE_PCS1GANLP 0x0421C
 331#define IXGBE_PCS1GANNP 0x04220
 332#define IXGBE_PCS1GANLPNP 0x04224
 333#define IXGBE_HLREG0    0x04240
 334#define IXGBE_HLREG1    0x04244
 335#define IXGBE_PAP       0x04248
 336#define IXGBE_MACA      0x0424C
 337#define IXGBE_APAE      0x04250
 338#define IXGBE_ARD       0x04254
 339#define IXGBE_AIS       0x04258
 340#define IXGBE_MSCA      0x0425C
 341#define IXGBE_MSRWD     0x04260
 342#define IXGBE_MLADD     0x04264
 343#define IXGBE_MHADD     0x04268
 344#define IXGBE_TREG      0x0426C
 345#define IXGBE_PCSS1     0x04288
 346#define IXGBE_PCSS2     0x0428C
 347#define IXGBE_XPCSS     0x04290
 348#define IXGBE_SERDESC   0x04298
 349#define IXGBE_MACS      0x0429C
 350#define IXGBE_AUTOC     0x042A0
 351#define IXGBE_LINKS     0x042A4
 352#define IXGBE_AUTOC2    0x042A8
 353#define IXGBE_AUTOC3    0x042AC
 354#define IXGBE_ANLP1     0x042B0
 355#define IXGBE_ANLP2     0x042B4
 356#define IXGBE_ATLASCTL  0x04800
 357
 358/* RSCCTL Bit Masks */
 359#define IXGBE_RSCCTL_RSCEN          0x01
 360#define IXGBE_RSCCTL_MAXDESC_1      0x00
 361#define IXGBE_RSCCTL_MAXDESC_4      0x04
 362#define IXGBE_RSCCTL_MAXDESC_8      0x08
 363#define IXGBE_RSCCTL_MAXDESC_16     0x0C
 364
 365/* CTRL Bit Masks */
 366#define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
 367#define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
 368#define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
 369
 370/* FACTPS */
 371#define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
 372
 373/* MHADD Bit Masks */
 374#define IXGBE_MHADD_MFS_MASK    0xFFFF0000
 375#define IXGBE_MHADD_MFS_SHIFT   16
 376
 377/* Extended Device Control */
 378#define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
 379#define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
 380#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
 381
 382/* Direct Cache Access (DCA) definitions */
 383#define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
 384#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
 385
 386#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
 387#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
 388
 389#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
 390#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
 391#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
 392#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
 393
 394#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
 395#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
 396#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
 397#define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
 398
 399/* MSCA Bit Masks */
 400#define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
 401#define IXGBE_MSCA_NP_ADDR_SHIFT     0
 402#define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
 403#define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
 404#define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
 405#define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
 406#define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
 407#define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
 408#define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
 409#define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
 410#define IXGBE_MSCA_READ              0x08000000 /* OP CODE 10 (read) */
 411#define IXGBE_MSCA_READ_AUTOINC      0x0C000000 /* OP CODE 11 (read, auto inc)*/
 412#define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
 413#define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
 414#define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
 415#define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
 416#define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
 417#define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
 418
 419/* MSRWD bit masks */
 420#define IXGBE_MSRWD_WRITE_DATA_MASK  0x0000FFFF
 421#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
 422#define IXGBE_MSRWD_READ_DATA_MASK   0xFFFF0000
 423#define IXGBE_MSRWD_READ_DATA_SHIFT  16
 424
 425/* Atlas registers */
 426#define IXGBE_ATLAS_PDN_LPBK    0x24
 427#define IXGBE_ATLAS_PDN_10G     0xB
 428#define IXGBE_ATLAS_PDN_1G      0xC
 429#define IXGBE_ATLAS_PDN_AN      0xD
 430
 431/* Atlas bit masks */
 432#define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
 433#define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
 434#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
 435#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
 436#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
 437
 438/* Device Type definitions for new protocol MDIO commands */
 439#define IXGBE_MDIO_PMA_PMD_DEV_TYPE               0x1
 440#define IXGBE_MDIO_PCS_DEV_TYPE                   0x3
 441#define IXGBE_MDIO_PHY_XS_DEV_TYPE                0x4
 442#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE              0x7
 443#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE     0x1E   /* Device 30 */
 444
 445#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */
 446#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */
 447#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
 448#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
 449#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
 450#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
 451
 452#define IXGBE_MDIO_AUTO_NEG_CONTROL    0x0 /* AUTO_NEG Control Reg */
 453#define IXGBE_MDIO_AUTO_NEG_STATUS     0x1 /* AUTO_NEG Status Reg */
 454#define IXGBE_MDIO_PHY_XS_CONTROL      0x0 /* PHY_XS Control Reg */
 455#define IXGBE_MDIO_PHY_XS_RESET        0x8000 /* PHY_XS Reset */
 456#define IXGBE_MDIO_PHY_ID_HIGH         0x2 /* PHY ID High Reg*/
 457#define IXGBE_MDIO_PHY_ID_LOW          0x3 /* PHY ID Low Reg*/
 458#define IXGBE_MDIO_PHY_SPEED_ABILITY   0x4 /* Speed Abilty Reg */
 459#define IXGBE_MDIO_PHY_SPEED_10G       0x0001 /* 10G capable */
 460#define IXGBE_MDIO_PHY_SPEED_1G        0x0010 /* 1G capable */
 461
 462#define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
 463#define IXGBE_MAX_PHY_ADDR             32
 464
 465/* PHY IDs*/
 466#define TN1010_PHY_ID    0x00A19410
 467#define QT2022_PHY_ID    0x0043A400
 468
 469/* General purpose Interrupt Enable */
 470#define IXGBE_GPIE_MSIX_MODE      0x00000010 /* MSI-X mode */
 471#define IXGBE_GPIE_OCD            0x00000020 /* Other Clear Disable */
 472#define IXGBE_GPIE_EIMEN          0x00000040 /* Immediate Interrupt Enable */
 473#define IXGBE_GPIE_EIAME          0x40000000
 474#define IXGBE_GPIE_PBA_SUPPORT    0x80000000
 475
 476/* Transmit Flow Control status */
 477#define IXGBE_TFCS_TXOFF         0x00000001
 478#define IXGBE_TFCS_TXOFF0        0x00000100
 479#define IXGBE_TFCS_TXOFF1        0x00000200
 480#define IXGBE_TFCS_TXOFF2        0x00000400
 481#define IXGBE_TFCS_TXOFF3        0x00000800
 482#define IXGBE_TFCS_TXOFF4        0x00001000
 483#define IXGBE_TFCS_TXOFF5        0x00002000
 484#define IXGBE_TFCS_TXOFF6        0x00004000
 485#define IXGBE_TFCS_TXOFF7        0x00008000
 486
 487/* TCP Timer */
 488#define IXGBE_TCPTIMER_KS            0x00000100
 489#define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
 490#define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
 491#define IXGBE_TCPTIMER_LOOP          0x00000800
 492#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
 493
 494/* HLREG0 Bit Masks */
 495#define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
 496#define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
 497#define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
 498#define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
 499#define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
 500#define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
 501#define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
 502#define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
 503#define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
 504#define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
 505#define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
 506#define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
 507#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
 508#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
 509#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
 510
 511/* VMD_CTL bitmasks */
 512#define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
 513#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
 514
 515/* RDHMPN and TDHMPN bitmasks */
 516#define IXGBE_RDHMPN_RDICADDR       0x007FF800
 517#define IXGBE_RDHMPN_RDICRDREQ      0x00800000
 518#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
 519#define IXGBE_TDHMPN_TDICADDR       0x003FF800
 520#define IXGBE_TDHMPN_TDICRDREQ      0x00800000
 521#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
 522
 523/* Receive Checksum Control */
 524#define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
 525#define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
 526
 527/* FCRTL Bit Masks */
 528#define IXGBE_FCRTL_XONE        0x80000000  /* bit 31, XON enable */
 529#define IXGBE_FCRTH_FCEN        0x80000000  /* Rx Flow control enable */
 530
 531/* PAP bit masks*/
 532#define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
 533
 534/* RMCS Bit Masks */
 535#define IXGBE_RMCS_RRM          0x00000002 /* Receive Recylce Mode enable */
 536/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
 537#define IXGBE_RMCS_RAC          0x00000004
 538#define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
 539#define IXGBE_RMCS_TFCE_802_3X  0x00000008 /* Tx Priority flow control ena */
 540#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
 541#define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
 542
 543/* Interrupt register bitmasks */
 544
 545/* Extended Interrupt Cause Read */
 546#define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
 547#define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
 548#define IXGBE_EICR_MNG          0x00400000 /* Managability Event Interrupt */
 549#define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
 550#define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
 551#define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
 552#define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 553
 554/* Extended Interrupt Cause Set */
 555#define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 556#define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */
 557#define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
 558#define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
 559#define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
 560#define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */
 561#define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 562#define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 563
 564/* Extended Interrupt Mask Set */
 565#define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 566#define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
 567#define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
 568#define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Error */
 569#define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
 570#define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 571#define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 572
 573/* Extended Interrupt Mask Clear */
 574#define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 575#define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
 576#define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
 577#define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Error */
 578#define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
 579#define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 580#define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 581
 582#define IXGBE_EIMS_ENABLE_MASK (\
 583                                IXGBE_EIMS_RTX_QUEUE       | \
 584                                IXGBE_EIMS_LSC             | \
 585                                IXGBE_EIMS_TCP_TIMER       | \
 586                                IXGBE_EIMS_OTHER)
 587
 588/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
 589#define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
 590#define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
 591#define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
 592#define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
 593#define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
 594#define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
 595#define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
 596#define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
 597#define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
 598#define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
 599
 600/* Interrupt clear mask */
 601#define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
 602
 603/* Interrupt Vector Allocation Registers */
 604#define IXGBE_IVAR_REG_NUM      25
 605#define IXGBE_IVAR_TXRX_ENTRY   96
 606#define IXGBE_IVAR_RX_ENTRY     64
 607#define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
 608#define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
 609#define IXGBE_IVAR_TX_ENTRY     32
 610
 611#define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
 612#define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
 613
 614#define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
 615
 616#define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
 617
 618/* VLAN Control Bit Masks */
 619#define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
 620#define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
 621#define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
 622#define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
 623#define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
 624
 625#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
 626
 627/* STATUS Bit Masks */
 628#define IXGBE_STATUS_LAN_ID     0x0000000C /* LAN ID */
 629#define IXGBE_STATUS_GIO        0x00080000 /* GIO Master Enable Status */
 630
 631#define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
 632#define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
 633
 634/* ESDP Bit Masks */
 635#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
 636#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
 637#define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
 638#define IXGBE_ESDP_SDP5_DIR     0x00000008 /* SDP5 IO direction */
 639
 640/* LEDCTL Bit Masks */
 641#define IXGBE_LED_IVRT_BASE      0x00000040
 642#define IXGBE_LED_BLINK_BASE     0x00000080
 643#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
 644#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
 645#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
 646#define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
 647#define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
 648#define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
 649
 650/* LED modes */
 651#define IXGBE_LED_LINK_UP       0x0
 652#define IXGBE_LED_LINK_10G      0x1
 653#define IXGBE_LED_MAC           0x2
 654#define IXGBE_LED_FILTER        0x3
 655#define IXGBE_LED_LINK_ACTIVE   0x4
 656#define IXGBE_LED_LINK_1G       0x5
 657#define IXGBE_LED_ON            0xE
 658#define IXGBE_LED_OFF           0xF
 659
 660/* AUTOC Bit Masks */
 661#define IXGBE_AUTOC_KX4_SUPP    0x80000000
 662#define IXGBE_AUTOC_KX_SUPP     0x40000000
 663#define IXGBE_AUTOC_PAUSE       0x30000000
 664#define IXGBE_AUTOC_RF          0x08000000
 665#define IXGBE_AUTOC_PD_TMR      0x06000000
 666#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
 667#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
 668#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
 669#define IXGBE_AUTOC_AN_RESTART  0x00001000
 670#define IXGBE_AUTOC_FLU         0x00000001
 671#define IXGBE_AUTOC_LMS_SHIFT   13
 672#define IXGBE_AUTOC_LMS_MASK   (0x7 << IXGBE_AUTOC_LMS_SHIFT)
 673#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN  (0x0 << IXGBE_AUTOC_LMS_SHIFT)
 674#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
 675#define IXGBE_AUTOC_LMS_1G_AN  (0x2 << IXGBE_AUTOC_LMS_SHIFT)
 676#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
 677#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN   (0x6 << IXGBE_AUTOC_LMS_SHIFT)
 678#define IXGBE_AUTOC_LMS_ATTACH_TYPE    (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 679
 680#define IXGBE_AUTOC_1G_PMA_PMD      0x00000200
 681#define IXGBE_AUTOC_10G_PMA_PMD     0x00000180
 682#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
 683#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
 684#define IXGBE_AUTOC_10G_XAUI   (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 685#define IXGBE_AUTOC_10G_KX4    (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 686#define IXGBE_AUTOC_10G_CX4    (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 687#define IXGBE_AUTOC_1G_BX      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 688#define IXGBE_AUTOC_1G_KX      (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 689
 690/* LINKS Bit Masks */
 691#define IXGBE_LINKS_KX_AN_COMP  0x80000000
 692#define IXGBE_LINKS_UP          0x40000000
 693#define IXGBE_LINKS_SPEED       0x20000000
 694#define IXGBE_LINKS_MODE        0x18000000
 695#define IXGBE_LINKS_RX_MODE     0x06000000
 696#define IXGBE_LINKS_TX_MODE     0x01800000
 697#define IXGBE_LINKS_XGXS_EN     0x00400000
 698#define IXGBE_LINKS_PCS_1G_EN   0x00200000
 699#define IXGBE_LINKS_1G_AN_EN    0x00100000
 700#define IXGBE_LINKS_KX_AN_IDLE  0x00080000
 701#define IXGBE_LINKS_1G_SYNC     0x00040000
 702#define IXGBE_LINKS_10G_ALIGN   0x00020000
 703#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
 704#define IXGBE_LINKS_TL_FAULT    0x00001000
 705#define IXGBE_LINKS_SIGNAL      0x00000F00
 706
 707#define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
 708
 709/* SW Semaphore Register bitmasks */
 710#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
 711#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
 712#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
 713
 714/* GSSR definitions */
 715#define IXGBE_GSSR_EEP_SM     0x0001
 716#define IXGBE_GSSR_PHY0_SM    0x0002
 717#define IXGBE_GSSR_PHY1_SM    0x0004
 718#define IXGBE_GSSR_MAC_CSR_SM 0x0008
 719#define IXGBE_GSSR_FLASH_SM   0x0010
 720
 721/* EEC Register */
 722#define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
 723#define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
 724#define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
 725#define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
 726#define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
 727#define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
 728#define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
 729#define IXGBE_EEC_FWE_SHIFT 4
 730#define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
 731#define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
 732#define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
 733#define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
 734/* EEPROM Addressing bits based on type (0-small, 1-large) */
 735#define IXGBE_EEC_ADDR_SIZE 0x00000400
 736#define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
 737
 738#define IXGBE_EEC_SIZE_SHIFT          11
 739#define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
 740#define IXGBE_EEPROM_OPCODE_BITS      8
 741
 742/* Checksum and EEPROM pointers */
 743#define IXGBE_EEPROM_CHECKSUM   0x3F
 744#define IXGBE_EEPROM_SUM        0xBABA
 745#define IXGBE_PCIE_ANALOG_PTR   0x03
 746#define IXGBE_ATLAS0_CONFIG_PTR 0x04
 747#define IXGBE_ATLAS1_CONFIG_PTR 0x05
 748#define IXGBE_PCIE_GENERAL_PTR  0x06
 749#define IXGBE_PCIE_CONFIG0_PTR  0x07
 750#define IXGBE_PCIE_CONFIG1_PTR  0x08
 751#define IXGBE_CORE0_PTR         0x09
 752#define IXGBE_CORE1_PTR         0x0A
 753#define IXGBE_MAC0_PTR          0x0B
 754#define IXGBE_MAC1_PTR          0x0C
 755#define IXGBE_CSR0_CONFIG_PTR   0x0D
 756#define IXGBE_CSR1_CONFIG_PTR   0x0E
 757#define IXGBE_FW_PTR            0x0F
 758#define IXGBE_PBANUM0_PTR       0x15
 759#define IXGBE_PBANUM1_PTR       0x16
 760
 761/* EEPROM Commands - SPI */
 762#define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
 763#define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
 764#define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
 765#define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
 766#define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
 767#define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
 768/* EEPROM reset Write Enbale latch */
 769#define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
 770#define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
 771#define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
 772#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
 773#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
 774#define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
 775
 776/* EEPROM Read Register */
 777#define IXGBE_EEPROM_READ_REG_DATA   16   /* data offset in EEPROM read reg */
 778#define IXGBE_EEPROM_READ_REG_DONE   2    /* Offset to READ done bit */
 779#define IXGBE_EEPROM_READ_REG_START  1    /* First bit to start operation */
 780#define IXGBE_EEPROM_READ_ADDR_SHIFT 2    /* Shift to the address bits */
 781
 782#define IXGBE_ETH_LENGTH_OF_ADDRESS   6
 783
 784#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
 785#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
 786#endif
 787
 788#ifndef IXGBE_EERD_ATTEMPTS
 789/* Number of 5 microseconds we wait for EERD read to complete */
 790#define IXGBE_EERD_ATTEMPTS 100000
 791#endif
 792
 793/* PCI Bus Info */
 794#define IXGBE_PCI_LINK_STATUS     0xB2
 795#define IXGBE_PCI_LINK_WIDTH      0x3F0
 796#define IXGBE_PCI_LINK_WIDTH_1    0x10
 797#define IXGBE_PCI_LINK_WIDTH_2    0x20
 798#define IXGBE_PCI_LINK_WIDTH_4    0x40
 799#define IXGBE_PCI_LINK_WIDTH_8    0x80
 800#define IXGBE_PCI_LINK_SPEED      0xF
 801#define IXGBE_PCI_LINK_SPEED_2500 0x1
 802#define IXGBE_PCI_LINK_SPEED_5000 0x2
 803
 804/* Number of 100 microseconds we wait for PCI Express master disable */
 805#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
 806
 807/* PHY Types */
 808#define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
 809
 810/* Check whether address is multicast.  This is little-endian specific check.*/
 811#define IXGBE_IS_MULTICAST(Address) \
 812                (bool)(((u8 *)(Address))[0] & ((u8)0x01))
 813
 814/* Check whether an address is broadcast. */
 815#define IXGBE_IS_BROADCAST(Address)                      \
 816                ((((u8 *)(Address))[0] == ((u8)0xff)) && \
 817                (((u8 *)(Address))[1] == ((u8)0xff)))
 818
 819/* RAH */
 820#define IXGBE_RAH_VIND_MASK     0x003C0000
 821#define IXGBE_RAH_VIND_SHIFT    18
 822#define IXGBE_RAH_AV            0x80000000
 823
 824/* Filters */
 825#define IXGBE_MC_TBL_SIZE       128  /* Multicast Filter Table (4096 bits) */
 826#define IXGBE_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 827
 828/* Header split receive */
 829#define IXGBE_RFCTL_ISCSI_DIS       0x00000001
 830#define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
 831#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
 832#define IXGBE_RFCTL_NFSW_DIS        0x00000040
 833#define IXGBE_RFCTL_NFSR_DIS        0x00000080
 834#define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
 835#define IXGBE_RFCTL_NFS_VER_SHIFT   8
 836#define IXGBE_RFCTL_NFS_VER_2       0
 837#define IXGBE_RFCTL_NFS_VER_3       1
 838#define IXGBE_RFCTL_NFS_VER_4       2
 839#define IXGBE_RFCTL_IPV6_DIS        0x00000400
 840#define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
 841#define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
 842#define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
 843#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
 844
 845/* Transmit Config masks */
 846#define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
 847#define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
 848/* Enable short packet padding to 64 bytes */
 849#define IXGBE_TX_PAD_ENABLE     0x00000400
 850#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
 851/* This allows for 16K packets + 4k for vlan */
 852#define IXGBE_MAX_FRAME_SZ      0x40040000
 853
 854#define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
 855#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq. # write-back enable */
 856
 857/* Receive Config masks */
 858#define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
 859#define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
 860#define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
 861
 862#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
 863#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
 864#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
 865#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
 866#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
 867#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
 868/* Receive Priority Flow Control Enbale */
 869#define IXGBE_FCTRL_RPFCE 0x00004000
 870#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
 871
 872/* Multiple Receive Queue Control */
 873#define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
 874#define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
 875#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
 876#define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
 877#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
 878#define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
 879#define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
 880#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
 881#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
 882#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
 883#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
 884
 885#define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 886#define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 887#define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
 888#define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 889#define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 890#define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
 891#define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 892#define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 893#define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 894
 895/* Receive Descriptor bit definitions */
 896#define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
 897#define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
 898#define IXGBE_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 899#define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 900#define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */
 901#define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
 902#define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 903#define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 904#define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
 905#define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
 906#define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
 907#define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 908#define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
 909#define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
 910#define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
 911#define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
 912#define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
 913#define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
 914#define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
 915#define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
 916#define IXGBE_RXDADV_HBO        0x00800000
 917#define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
 918#define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
 919#define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
 920#define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
 921#define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
 922#define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
 923#define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
 924#define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
 925#define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
 926#define IXGBE_RXD_PRI_SHIFT     13
 927#define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
 928#define IXGBE_RXD_CFI_SHIFT     12
 929
 930/* SRRCTL bit definitions */
 931#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10     /* so many KBs */
 932#define IXGBE_SRRCTL_BSIZEPKT_MASK  0x0000007F
 933#define IXGBE_SRRCTL_BSIZEHDR_MASK  0x00003F00
 934#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
 935#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
 936#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
 937#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 938#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
 939
 940#define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
 941#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
 942
 943#define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
 944#define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
 945#define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
 946#define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
 947#define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
 948#define IXGBE_RXDADV_SPH                0x8000
 949
 950/* RSS Hash results */
 951#define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
 952#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
 953#define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
 954#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
 955#define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
 956#define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
 957#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 958#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
 959#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
 960#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 961
 962/* RSS Packet Types as indicated in the receive descriptor. */
 963#define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
 964#define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
 965#define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
 966#define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
 967#define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
 968#define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
 969#define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
 970#define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
 971#define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
 972
 973/* Masks to determine if packets should be dropped due to frame errors */
 974#define IXGBE_RXD_ERR_FRAME_ERR_MASK (\
 975                                      IXGBE_RXD_ERR_CE | \
 976                                      IXGBE_RXD_ERR_LE | \
 977                                      IXGBE_RXD_ERR_PE | \
 978                                      IXGBE_RXD_ERR_OSE | \
 979                                      IXGBE_RXD_ERR_USE)
 980
 981#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK (\
 982                                      IXGBE_RXDADV_ERR_CE | \
 983                                      IXGBE_RXDADV_ERR_LE | \
 984                                      IXGBE_RXDADV_ERR_PE | \
 985                                      IXGBE_RXDADV_ERR_OSE | \
 986                                      IXGBE_RXDADV_ERR_USE)
 987
 988/* Multicast bit mask */
 989#define IXGBE_MCSTCTRL_MFE      0x4
 990
 991/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
 992#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
 993#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
 994#define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
 995
 996/* Vlan-specific macros */
 997#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
 998#define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
 999#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
1000#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT

1001
1002/* Transmit Descriptor - Legacy */
1003struct ixgbe_legacy_tx_desc {
1004        u64 buffer_addr;       /* Address of the descriptor's data buffer */
1005        union {
1006                u32 data;
1007                struct {
1008                        u16 length;    /* Data buffer length */
1009                        u8 cso; /* Checksum offset */
1010                        u8 cmd; /* Descriptor control */
1011                } flags;
1012        } lower;
1013        union {
1014                u32 data;
1015                struct {
1016                        u8 status;     /* Descriptor status */
1017                        u8 css; /* Checksum start */
1018                        u16 vlan;
1019                } fields;
1020        } upper;
1021};
1022
1023/* Transmit Descriptor - Advanced */
1024union ixgbe_adv_tx_desc {
1025        struct {
1026                u64 buffer_addr;       /* Address of descriptor's data buf */
1027                u32 cmd_type_len;
1028                u32 olinfo_status;
1029        } read;
1030        struct {
1031                u64 rsvd;       /* Reserved */
1032                u32 nxtseq_seed;
1033                u32 status;
1034        } wb;
1035};
1036
1037/* Receive Descriptor - Legacy */
1038struct ixgbe_legacy_rx_desc {
1039        u64 buffer_addr; /* Address of the descriptor's data buffer */
1040        u16 length;      /* Length of data DMAed into data buffer */
1041        u16 csum;        /* Packet checksum */
1042        u8 status;       /* Descriptor status */
1043        u8 errors;       /* Descriptor Errors */
1044        u16 vlan;
1045};
1046
1047/* Receive Descriptor - Advanced */
1048union ixgbe_adv_rx_desc {
1049        struct {
1050                u64 pkt_addr; /* Packet buffer address */
1051                u64 hdr_addr; /* Header buffer address */
1052        } read;
1053        struct {
1054                struct {
1055                        struct {
1056                                u16 pkt_info; /* RSS type, Packet type */
1057                                u16 hdr_info; /* Split Header, header len */
1058                        } lo_dword;
1059                        union {
1060                                u32 rss; /* RSS Hash */
1061                                struct {
1062                                        u16 ip_id; /* IP id */
1063                                        u16 csum; /* Packet Checksum */
1064                                } csum_ip;
1065                        } hi_dword;
1066                } lower;
1067                struct {
1068                        u32 status_error; /* ext status/error */
1069                        u16 length; /* Packet length */
1070                        u16 vlan; /* VLAN tag */
1071                } upper;
1072        } wb;  /* writeback */
1073};
1074
1075/* Context descriptors */
1076struct ixgbe_adv_tx_context_desc {
1077        u32 vlan_macip_lens;
1078        u32 seqnum_seed;
1079        u32 type_tucmd_mlhl;
1080        u32 mss_l4len_idx;
1081};
1082
1083/* Adv Transmit Descriptor Config Masks */
1084#define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buffer length(bytes) */
1085#define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
1086#define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
1087#define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
1088#define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
1089#define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
1090#define IXGBE_ADVTXD_DCMD_RDMA  0x04000000 /* RDMA */
1091#define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
1092#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000     /* DDP hdr type or iSCSI */
1093#define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1094#define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
1095#define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
1096#define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
1097#define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED present in WB */
1098#define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
1099#define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
1100#define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
1101#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1102                                IXGBE_ADVTXD_POPTS_SHIFT)
1103#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1104                                IXGBE_ADVTXD_POPTS_SHIFT)
1105#define IXGBE_ADVTXD_POPTS_EOM  0x00000400 /* Enable L bit-RDMA DDP hdr */
1106#define IXGBE_ADVTXD_POPTS_ISCO_1ST   0x00000000 /* 1st TSO of iSCSI PDU */
1107#define IXGBE_ADVTXD_POPTS_ISCO_MDL   0x00000800 /* Middle TSO of iSCSI PDU */
1108#define IXGBE_ADVTXD_POPTS_ISCO_LAST  0x00001000 /* Last TSO of iSCSI PDU */
1109#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
1110#define IXGBE_ADVTXD_POPTS_RSV  0x00002000 /* POPTS Reserved */
1111#define IXGBE_ADVTXD_PAYLEN_SHIFT  14 /* Adv desc PAYLEN shift */
1112#define IXGBE_ADVTXD_MACLEN_SHIFT  9  /* Adv ctxt desc mac len shift */
1113#define IXGBE_ADVTXD_VLAN_SHIFT    16  /* Adv ctxt vlan tag shift */
1114#define IXGBE_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
1115#define IXGBE_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
1116#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
1117#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
1118#define IXGBE_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
1119#define IXGBE_ADVTXD_L4LEN_SHIFT   8  /* Adv ctxt L4LEN shift */
1120#define IXGBE_ADVTXD_MSS_SHIFT     16  /* Adv ctxt MSS shift */
1121
1122/* Link speed */
1123#define IXGBE_LINK_SPEED_UNKNOWN   0
1124#define IXGBE_LINK_SPEED_100_FULL  0x0008
1125#define IXGBE_LINK_SPEED_1GB_FULL  0x0020
1126#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1127
1128
1129enum ixgbe_eeprom_type {
1130        ixgbe_eeprom_uninitialized = 0,
1131        ixgbe_eeprom_spi,
1132        ixgbe_eeprom_none /* No NVM support */
1133};
1134
1135enum ixgbe_mac_type {
1136        ixgbe_mac_unknown = 0,
1137        ixgbe_mac_82598EB,
1138        ixgbe_num_macs
1139};
1140
1141enum ixgbe_phy_type {
1142        ixgbe_phy_unknown = 0,
1143        ixgbe_phy_tn,
1144        ixgbe_phy_qt,
1145        ixgbe_phy_xaui
1146};
1147
1148enum ixgbe_media_type {
1149        ixgbe_media_type_unknown = 0,
1150        ixgbe_media_type_fiber,
1151        ixgbe_media_type_copper,
1152        ixgbe_media_type_backplane
1153};
1154
1155/* Flow Control Settings */
1156enum ixgbe_fc_type {
1157        ixgbe_fc_none = 0,
1158        ixgbe_fc_rx_pause,
1159        ixgbe_fc_tx_pause,
1160        ixgbe_fc_full,
1161        ixgbe_fc_default
1162};
1163
1164struct ixgbe_addr_filter_info {
1165        u32 num_mc_addrs;
1166        u32 rar_used_count;
1167        u32 mc_addr_in_rar_count;
1168        u32 mta_in_use;
1169};
1170
1171/* Flow control parameters */
1172struct ixgbe_fc_info {
1173        u32 high_water; /* Flow Control High-water */
1174        u32 low_water; /* Flow Control Low-water */
1175        u16 pause_time; /* Flow Control Pause timer */
1176        bool send_xon; /* Flow control send XON */
1177        bool strict_ieee; /* Strict IEEE mode */
1178        enum ixgbe_fc_type type; /* Type of flow control */
1179        enum ixgbe_fc_type original_type;
1180};
1181
1182/* Statistics counters collected by the MAC */
1183struct ixgbe_hw_stats {
1184        u64 crcerrs;
1185        u64 illerrc;
1186        u64 errbc;
1187        u64 mspdc;
1188        u64 mpctotal;
1189        u64 mpc[8];
1190        u64 mlfc;
1191        u64 mrfc;
1192        u64 rlec;
1193        u64 lxontxc;
1194        u64 lxonrxc;
1195        u64 lxofftxc;
1196        u64 lxoffrxc;
1197        u64 pxontxc[8];
1198        u64 pxonrxc[8];
1199        u64 pxofftxc[8];
1200        u64 pxoffrxc[8];
1201        u64 prc64;
1202        u64 prc127;
1203        u64 prc255;
1204        u64 prc511;
1205        u64 prc1023;
1206        u64 prc1522;
1207        u64 gprc;
1208        u64 bprc;
1209        u64 mprc;
1210        u64 gptc;
1211        u64 gorc;
1212        u64 gotc;
1213        u64 rnbc[8];
1214        u64 ruc;
1215        u64 rfc;
1216        u64 roc;
1217        u64 rjc;
1218        u64 mngprc;
1219        u64 mngpdc;
1220        u64 mngptc;
1221        u64 tor;
1222        u64 tpr;
1223        u64 tpt;
1224        u64 ptc64;
1225        u64 ptc127;
1226        u64 ptc255;
1227        u64 ptc511;
1228        u64 ptc1023;
1229        u64 ptc1522;
1230        u64 mptc;
1231        u64 bptc;
1232        u64 xec;
1233        u64 rqsmr[16];
1234        u64 tqsmr[8];
1235        u64 qprc[16];
1236        u64 qptc[16];
1237        u64 qbrc[16];
1238        u64 qbtc[16];
1239};
1240
1241/* forward declaration */
1242struct ixgbe_hw;
1243
1244struct ixgbe_mac_operations {
1245        s32 (*reset)(struct ixgbe_hw *);
1246        enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1247};
1248
1249struct ixgbe_phy_operations {
1250        s32 (*setup)(struct ixgbe_hw *);
1251        s32 (*check)(struct ixgbe_hw *, u32 *, bool *);
1252        s32 (*setup_speed)(struct ixgbe_hw *, u32, bool, bool);
1253        s32 (*get_settings)(struct ixgbe_hw *, u32 *, bool *);
1254};
1255
1256struct ixgbe_mac_info {
1257        struct ixgbe_mac_operations     ops;
1258        enum ixgbe_mac_type             type;
1259        u8                              addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1260        u8                              perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1261        s32                             mc_filter_type;
1262        u32                             num_rx_queues;
1263        u32                             num_tx_queues;
1264        u32                             num_rx_addrs;
1265        u32                             link_attach_type;
1266        u32                             link_mode_select;
1267        bool                            link_settings_loaded;
1268};
1269
1270
1271struct ixgbe_eeprom_info {
1272        enum ixgbe_eeprom_type          type;
1273        u16                             word_size;
1274        u16                             address_bits;
1275};
1276
1277struct ixgbe_phy_info {
1278        struct ixgbe_phy_operations     ops;
1279
1280        enum ixgbe_phy_type             type;
1281        u32                             addr;
1282        u32                             id;
1283        u32                             revision;
1284        enum ixgbe_media_type           media_type;
1285        u32                             autoneg_advertised;
1286        bool                            autoneg_wait_to_complete;
1287};
1288
1289struct ixgbe_info {
1290        enum ixgbe_mac_type             mac;
1291        s32                             (*get_invariants)(struct ixgbe_hw *);
1292        struct ixgbe_mac_operations     *mac_ops;
1293        struct ixgbe_phy_operations     *phy_ops;
1294};
1295
1296struct ixgbe_hw {
1297        u8 __iomem                      *hw_addr;
1298        void                            *back;
1299        struct ixgbe_mac_info           mac;
1300        struct ixgbe_addr_filter_info   addr_ctrl;
1301        struct ixgbe_fc_info            fc;
1302        struct ixgbe_phy_info           phy;
1303        struct ixgbe_eeprom_info        eeprom;
1304        u16                             device_id;
1305        u16                             vendor_id;
1306        u16                             subsystem_device_id;
1307        u16                             subsystem_vendor_id;
1308        u8                              revision_id;
1309        bool                            adapter_stopped;
1310};
1311
1312/* Error Codes */
1313#define IXGBE_ERR_EEPROM                        -1
1314#define IXGBE_ERR_EEPROM_CHECKSUM               -2
1315#define IXGBE_ERR_PHY                           -3
1316#define IXGBE_ERR_CONFIG                        -4
1317#define IXGBE_ERR_PARAM                         -5
1318#define IXGBE_ERR_MAC_TYPE                      -6
1319#define IXGBE_ERR_UNKNOWN_PHY                   -7
1320#define IXGBE_ERR_LINK_SETUP                    -8
1321#define IXGBE_ERR_ADAPTER_STOPPED               -9
1322#define IXGBE_ERR_INVALID_MAC_ADDR              -10
1323#define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
1324#define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
1325#define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
1326#define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
1327#define IXGBE_ERR_RESET_FAILED                  -15
1328#define IXGBE_ERR_SWFW_SYNC                     -16
1329#define IXGBE_ERR_PHY_ADDR_INVALID              -17
1330#define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
1331
1332#endif /* _IXGBE_TYPE_H_ */
1333