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39#ifndef __INC_SKDRV2ND_H
40#define __INC_SKDRV2ND_H
41
42#include "h/skqueue.h"
43#include "h/skgehwt.h"
44#include "h/sktimer.h"
45#include "h/ski2c.h"
46#include "h/skgepnmi.h"
47#include "h/skvpd.h"
48#include "h/skgehw.h"
49#include "h/skgeinit.h"
50#include "h/skaddr.h"
51#include "h/skgesirq.h"
52#include "h/skcsum.h"
53#include "h/skrlmt.h"
54#include "h/skgedrv.h"
55
56
57extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
58extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
59extern SK_U64 SkOsGetTime(SK_AC*);
60extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
61extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
62extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
63extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
64extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
65extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
66
67#ifdef SK_DIAG_SUPPORT
68extern int SkDrvEnterDiagMode(SK_AC *pAc);
69extern int SkDrvLeaveDiagMode(SK_AC *pAc);
70#endif
71
72struct s_DrvRlmtMbuf {
73 SK_MBUF *pNext;
74 SK_U8 *pData;
75 unsigned Size;
76 unsigned Length;
77 SK_U32 PortIdx;
78#ifdef SK_RLMT_MBUF_PRIVATE
79 SK_RLMT_MBUF Rlmt;
80#endif
81 struct sk_buff *pOs;
82};
83
84
85
86
87
88#if SK_TICKS_PER_SEC == 100
89#define SK_PNMI_HUNDREDS_SEC(t) (t)
90#else
91#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
92 (SK_TICKS_PER_SEC))
93#endif
94
95
96
97
98#define SkOsGetTimeCurrent(pAC, pUsec) {\
99 struct timeval t;\
100 do_gettimeofday(&t);\
101 *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
102}
103
104
105
106
107
108#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
109#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
110#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
111#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
112#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
113#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
114
115typedef struct s_IOCTL SK_GE_IOCTL;
116
117struct s_IOCTL {
118 char __user * pData;
119 unsigned int Len;
120};
121
122
123
124
125
126
127#define TX_RING_SIZE (8*1024)
128#define RX_RING_SIZE (24*1024)
129
130
131
132
133#define ETH_BUF_SIZE 1540
134#define ETH_MAX_MTU 1514
135#define ETH_MIN_MTU 60
136#define ETH_MULTICAST_BIT 0x01
137#define SK_JUMBO_MTU 9000
138
139
140
141
142#define TX_PRIO_LOW 0
143#define TX_PRIO_HIGH 1
144
145
146
147
148#define DESCR_ALIGN 64
149
150
151
152
153#define SK_DRIVER_RESET(pAC, IoC) 0
154#define SK_DRIVER_SENDEVENT(pAC, IoC) 0
155#define SK_DRIVER_SELFTEST(pAC, IoC) 0
156
157#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0
158#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
159#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
160
161
162
163
164
165#define SK_DRV_TIMER 11
166#define SK_DRV_MODERATION_TIMER 1
167#define SK_DRV_MODERATION_TIMER_LENGTH 1000000
168#define SK_DRV_RX_CLEANUP_TIMER 2
169#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000
170
171
172
173
174
175#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
176#define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
177#define C_LEN_ETHERMAC_HEADER_LENTYPE 2
178#define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \
179 (C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \
180 (C_LEN_ETHERMAC_HEADER_LENTYPE) )
181
182#define C_LEN_ETHERMTU_MINSIZE 46
183#define C_LEN_ETHERMTU_MAXSIZE_STD 1500
184#define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000
185
186#define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \
187 (C_LEN_ETHERMTU_MINSIZE) )
188
189#define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER
190#define C_OFFSET_IPHEADER_IPPROTO 9
191#define C_OFFSET_TCPHEADER_TCPCS 16
192#define C_OFFSET_UDPHEADER_UDPCS 6
193
194#define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \
195 (C_OFFSET_IPHEADER_IPPROTO) )
196
197#define C_PROTO_ID_UDP 17
198#define C_PROTO_ID_TCP 6
199
200
201
202typedef struct s_RxD RXD;
203
204struct s_RxD {
205 volatile SK_U32 RBControl;
206 SK_U32 VNextRxd;
207 SK_U32 VDataLow;
208 SK_U32 VDataHigh;
209 SK_U32 FrameStat;
210 SK_U32 TimeStamp;
211 SK_U32 TcpSums;
212 SK_U32 TcpSumStarts;
213 RXD *pNextRxd;
214 struct sk_buff *pMBuf;
215};
216
217typedef struct s_TxD TXD;
218
219struct s_TxD {
220 volatile SK_U32 TBControl;
221 SK_U32 VNextTxd;
222 SK_U32 VDataLow;
223 SK_U32 VDataHigh;
224 SK_U32 FrameStat;
225 SK_U32 TcpSumOfs;
226 SK_U16 TcpSumSt;
227 SK_U16 TcpSumWr;
228 SK_U32 TcpReserved;
229 TXD *pNextTxd;
230 struct sk_buff *pMBuf;
231};
232
233
234
235#define DRIVER_IRQS ((IS_IRQ_SW) | \
236 (IS_R1_F) |(IS_R2_F) | \
237 (IS_XS1_F) |(IS_XA1_F) | \
238 (IS_XS2_F) |(IS_XA2_F))
239
240#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
241 (IS_EXT_REG) |(IS_TIMINT) | \
242 (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
243 (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
244 (IS_MAC1) |(IS_LNK_SYNC_M1)| \
245 (IS_MAC2) |(IS_LNK_SYNC_M2)| \
246 (IS_R1_C) |(IS_R2_C) | \
247 (IS_XS1_C) |(IS_XA1_C) | \
248 (IS_XS2_C) |(IS_XA2_C))
249
250#define IRQ_MASK ((IS_IRQ_SW) | \
251 (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
252 (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
253 (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
254 (IS_HW_ERR) |(IS_I2C_READY)| \
255 (IS_EXT_REG) |(IS_TIMINT) | \
256 (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
257 (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
258 (IS_MAC1) |(IS_MAC2) | \
259 (IS_R1_C) |(IS_R2_C) | \
260 (IS_XS1_C) |(IS_XA1_C) | \
261 (IS_XS2_C) |(IS_XA2_C))
262
263#define IRQ_HWE_MASK (IS_ERR_MSK)
264
265typedef struct s_DevNet DEV_NET;
266
267struct s_DevNet {
268 int PortNr;
269 int NetNr;
270 SK_AC *pAC;
271};
272
273typedef struct s_TxPort TX_PORT;
274
275struct s_TxPort {
276
277 caddr_t pTxDescrRing;
278 SK_U64 VTxDescrRing;
279 TXD *pTxdRingHead;
280 TXD *pTxdRingTail;
281 TXD *pTxdRingPrev;
282 int TxdRingFree;
283 spinlock_t TxDesRingLock;
284 SK_IOC HwAddr;
285 int PortIndex;
286};
287
288typedef struct s_RxPort RX_PORT;
289
290struct s_RxPort {
291
292 caddr_t pRxDescrRing;
293 SK_U64 VRxDescrRing;
294 RXD *pRxdRingHead;
295 RXD *pRxdRingTail;
296 RXD *pRxdRingPrev;
297 int RxdRingFree;
298 int RxCsum;
299 spinlock_t RxDesRingLock;
300 int RxFillLimit;
301 SK_IOC HwAddr;
302 int PortIndex;
303};
304
305
306
307#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
308#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
309#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))
310#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F))
311#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS)
312#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
313#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
314#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
315#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
316
317#define C_INT_MOD_NONE 1
318#define C_INT_MOD_STATIC 2
319#define C_INT_MOD_DYNAMIC 4
320
321#define C_CLK_FREQ_GENESIS 53215000
322#define C_CLK_FREQ_YUKON 78215000
323
324#define C_INTS_PER_SEC_DEFAULT 2000
325#define C_INT_MOD_ENABLE_PERCENTAGE 50
326#define C_INT_MOD_DISABLE_PERCENTAGE 50
327#define C_INT_MOD_IPS_LOWER_RANGE 30
328#define C_INT_MOD_IPS_UPPER_RANGE 40000
329
330
331typedef struct s_DynIrqModInfo DIM_INFO;
332struct s_DynIrqModInfo {
333 unsigned long PrevTimeVal;
334 unsigned int PrevSysLoad;
335 unsigned int PrevUsedTime;
336 unsigned int PrevTotalTime;
337 int PrevUsedDescrRatio;
338 int NbrProcessedDescr;
339 SK_U64 PrevPort0RxIntrCts;
340 SK_U64 PrevPort1RxIntrCts;
341 SK_U64 PrevPort0TxIntrCts;
342 SK_U64 PrevPort1TxIntrCts;
343 SK_BOOL ModJustEnabled;
344
345 int MaxModIntsPerSec;
346 int MaxModIntsPerSecUpperLimit;
347 int MaxModIntsPerSecLowerLimit;
348
349 long MaskIrqModeration;
350 SK_BOOL DisplayStats;
351 SK_BOOL AutoSizing;
352 int IntModTypeSelect;
353
354 SK_TIMER ModTimer;
355};
356
357typedef struct s_PerStrm PER_STRM;
358
359#define SK_ALLOC_IRQ 0x00000001
360
361#ifdef SK_DIAG_SUPPORT
362#define DIAG_ACTIVE 1
363#define DIAG_NOTACTIVE 0
364#endif
365
366
367
368
369
370
371struct s_AC {
372 SK_GEINIT GIni;
373 SK_PNMI Pnmi;
374 SK_VPD vpd;
375 SK_QUEUE Event;
376 SK_HWT Hwt;
377 SK_TIMCTRL Tim;
378 SK_I2C I2c;
379 SK_ADDR Addr;
380 SK_CSUM Csum;
381 SK_RLMT Rlmt;
382 spinlock_t SlowPathLock;
383 struct timer_list BlinkTimer;
384 int LedsOn;
385 SK_PNMI_STRUCT_DATA PnmiStruct;
386 int RlmtMode;
387 int RlmtNets;
388
389 SK_IOC IoBase;
390 int BoardLevel;
391
392 SK_U32 AllocFlag;
393 struct pci_dev *PciDev;
394 struct SK_NET_DEVICE *dev[2];
395
396 int RxBufSize;
397 struct net_device_stats stats;
398 int Index;
399
400
401 int RxQueueSize;
402 int TxSQueueSize;
403 int TxAQueueSize;
404
405 int PromiscCount;
406 int AllMultiCount;
407 int MulticCount;
408
409
410
411 int HWRevision;
412 int ActivePort;
413 int MaxPorts;
414 int TxDescrPerRing;
415 int RxDescrPerRing;
416
417 caddr_t pDescrMem;
418 dma_addr_t pDescrMemDMA;
419
420
421 TX_PORT TxPort[SK_MAX_MACS][2];
422 RX_PORT RxPort[SK_MAX_MACS];
423
424 SK_BOOL CheckQueue;
425 SK_TIMER DrvCleanupTimer;
426 DIM_INFO DynIrqModInfo;
427
428
429 int PortDown;
430 int ChipsetType;
431
432
433
434#ifdef SK_DIAG_SUPPORT
435 SK_U32 DiagModeActive;
436 SK_BOOL DiagFlowCtrl;
437 SK_PNMI_STRUCT_DATA PnmiBackup;
438 SK_BOOL WasIfUp[SK_MAX_MACS];
439
440
441#endif
442
443};
444
445
446#endif
447
448