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16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/in.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/ethtool.h>
28#include <linux/mii.h>
29#include <linux/crc32.h>
30#include <linux/random.h>
31#include <linux/errno.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/mm.h>
36#include <linux/bitops.h>
37
38#include <asm/system.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
43#ifdef CONFIG_SPARC
44#include <asm/idprom.h>
45#include <asm/sbus.h>
46#include <asm/openprom.h>
47#include <asm/oplib.h>
48#include <asm/prom.h>
49#include <asm/auxio.h>
50#endif
51#include <asm/uaccess.h>
52
53#include <asm/pgtable.h>
54#include <asm/irq.h>
55
56#ifdef CONFIG_PCI
57#include <linux/pci.h>
58#endif
59
60#include "sunhme.h"
61
62#define DRV_NAME "sunhme"
63#define DRV_VERSION "3.00"
64#define DRV_RELDATE "June 23, 2006"
65#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
66
67static char version[] =
68 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
69
70MODULE_VERSION(DRV_VERSION);
71MODULE_AUTHOR(DRV_AUTHOR);
72MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
73MODULE_LICENSE("GPL");
74
75static int macaddr[6];
76
77
78module_param_array(macaddr, int, NULL, 0);
79MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
80
81#ifdef CONFIG_SBUS
82static struct quattro *qfe_sbus_list;
83#endif
84
85#ifdef CONFIG_PCI
86static struct quattro *qfe_pci_list;
87#endif
88
89#undef HMEDEBUG
90#undef SXDEBUG
91#undef RXDEBUG
92#undef TXDEBUG
93#undef TXLOGGING
94
95#ifdef TXLOGGING
96struct hme_tx_logent {
97 unsigned int tstamp;
98 int tx_new, tx_old;
99 unsigned int action;
100#define TXLOG_ACTION_IRQ 0x01
101#define TXLOG_ACTION_TXMIT 0x02
102#define TXLOG_ACTION_TBUSY 0x04
103#define TXLOG_ACTION_NBUFS 0x08
104 unsigned int status;
105};
106#define TX_LOG_LEN 128
107static struct hme_tx_logent tx_log[TX_LOG_LEN];
108static int txlog_cur_entry;
109static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
110{
111 struct hme_tx_logent *tlp;
112 unsigned long flags;
113
114 save_and_cli(flags);
115 tlp = &tx_log[txlog_cur_entry];
116 tlp->tstamp = (unsigned int)jiffies;
117 tlp->tx_new = hp->tx_new;
118 tlp->tx_old = hp->tx_old;
119 tlp->action = a;
120 tlp->status = s;
121 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
122 restore_flags(flags);
123}
124static __inline__ void tx_dump_log(void)
125{
126 int i, this;
127
128 this = txlog_cur_entry;
129 for (i = 0; i < TX_LOG_LEN; i++) {
130 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
131 tx_log[this].tstamp,
132 tx_log[this].tx_new, tx_log[this].tx_old,
133 tx_log[this].action, tx_log[this].status);
134 this = (this + 1) & (TX_LOG_LEN - 1);
135 }
136}
137static __inline__ void tx_dump_ring(struct happy_meal *hp)
138{
139 struct hmeal_init_block *hb = hp->happy_block;
140 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
141 int i;
142
143 for (i = 0; i < TX_RING_SIZE; i+=4) {
144 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
145 i, i + 4,
146 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
147 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
148 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
149 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
150 }
151}
152#else
153#define tx_add_log(hp, a, s) do { } while(0)
154#define tx_dump_log() do { } while(0)
155#define tx_dump_ring(hp) do { } while(0)
156#endif
157
158#ifdef HMEDEBUG
159#define HMD(x) printk x
160#else
161#define HMD(x)
162#endif
163
164
165
166#ifdef AUTO_SWITCH_DEBUG
167#define ASD(x) printk x
168#else
169#define ASD(x)
170#endif
171
172#define DEFAULT_IPG0 16
173#define DEFAULT_IPG1 8
174#define DEFAULT_IPG2 4
175#define DEFAULT_JAMSIZE 4
176
177
178
179
180
181
182
183
184#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
185static void sbus_hme_write32(void __iomem *reg, u32 val)
186{
187 sbus_writel(val, reg);
188}
189
190static u32 sbus_hme_read32(void __iomem *reg)
191{
192 return sbus_readl(reg);
193}
194
195static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
196{
197 rxd->rx_addr = addr;
198 wmb();
199 rxd->rx_flags = flags;
200}
201
202static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
203{
204 txd->tx_addr = addr;
205 wmb();
206 txd->tx_flags = flags;
207}
208
209static u32 sbus_hme_read_desc32(u32 *p)
210{
211 return *p;
212}
213
214static void pci_hme_write32(void __iomem *reg, u32 val)
215{
216 writel(val, reg);
217}
218
219static u32 pci_hme_read32(void __iomem *reg)
220{
221 return readl(reg);
222}
223
224static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
225{
226 rxd->rx_addr = cpu_to_le32(addr);
227 wmb();
228 rxd->rx_flags = cpu_to_le32(flags);
229}
230
231static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
232{
233 txd->tx_addr = cpu_to_le32(addr);
234 wmb();
235 txd->tx_flags = cpu_to_le32(flags);
236}
237
238static u32 pci_hme_read_desc32(u32 *p)
239{
240 return cpu_to_le32p(p);
241}
242
243#define hme_write32(__hp, __reg, __val) \
244 ((__hp)->write32((__reg), (__val)))
245#define hme_read32(__hp, __reg) \
246 ((__hp)->read32(__reg))
247#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
248 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
249#define hme_write_txd(__hp, __txd, __flags, __addr) \
250 ((__hp)->write_txd((__txd), (__flags), (__addr)))
251#define hme_read_desc32(__hp, __p) \
252 ((__hp)->read_desc32(__p))
253#define hme_dma_map(__hp, __ptr, __size, __dir) \
254 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
255#define hme_dma_unmap(__hp, __addr, __size, __dir) \
256 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
257#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
259#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
261#else
262#ifdef CONFIG_SBUS
263
264#define hme_write32(__hp, __reg, __val) \
265 sbus_writel((__val), (__reg))
266#define hme_read32(__hp, __reg) \
267 sbus_readl(__reg)
268#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
269do { (__rxd)->rx_addr = (__addr); \
270 wmb(); \
271 (__rxd)->rx_flags = (__flags); \
272} while(0)
273#define hme_write_txd(__hp, __txd, __flags, __addr) \
274do { (__txd)->tx_addr = (__addr); \
275 wmb(); \
276 (__txd)->tx_flags = (__flags); \
277} while(0)
278#define hme_read_desc32(__hp, __p) (*(__p))
279#define hme_dma_map(__hp, __ptr, __size, __dir) \
280 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
281#define hme_dma_unmap(__hp, __addr, __size, __dir) \
282 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
283#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
284 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
285#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
286 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
287#else
288
289#define hme_write32(__hp, __reg, __val) \
290 writel((__val), (__reg))
291#define hme_read32(__hp, __reg) \
292 readl(__reg)
293#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
294do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
295 wmb(); \
296 (__rxd)->rx_flags = cpu_to_le32(__flags); \
297} while(0)
298#define hme_write_txd(__hp, __txd, __flags, __addr) \
299do { (__txd)->tx_addr = cpu_to_le32(__addr); \
300 wmb(); \
301 (__txd)->tx_flags = cpu_to_le32(__flags); \
302} while(0)
303#define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
304#define hme_dma_map(__hp, __ptr, __size, __dir) \
305 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
306#define hme_dma_unmap(__hp, __addr, __size, __dir) \
307 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
308#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
309 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
310#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
311 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
312#endif
313#endif
314
315
316#ifdef SBUS_DMA_BIDIRECTIONAL
317# define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
318#else
319# define DMA_BIDIRECTIONAL 0
320#endif
321
322#ifdef SBUS_DMA_FROMDEVICE
323# define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
324#else
325# define DMA_TODEVICE 1
326#endif
327
328#ifdef SBUS_DMA_TODEVICE
329# define DMA_TODEVICE SBUS_DMA_TODEVICE
330#else
331# define DMA_FROMDEVICE 2
332#endif
333
334
335
336static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
337{
338 hme_write32(hp, tregs + TCVR_BBDATA, bit);
339 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
340 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
341}
342
343#if 0
344static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
345{
346 u32 ret;
347
348 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
350 ret = hme_read32(hp, tregs + TCVR_CFG);
351 if (internal)
352 ret &= TCV_CFG_MDIO0;
353 else
354 ret &= TCV_CFG_MDIO1;
355
356 return ret;
357}
358#endif
359
360static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
361{
362 u32 retval;
363
364 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
365 udelay(1);
366 retval = hme_read32(hp, tregs + TCVR_CFG);
367 if (internal)
368 retval &= TCV_CFG_MDIO0;
369 else
370 retval &= TCV_CFG_MDIO1;
371 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
372
373 return retval;
374}
375
376#define TCVR_FAILURE 0x80000000
377
378static int happy_meal_bb_read(struct happy_meal *hp,
379 void __iomem *tregs, int reg)
380{
381 u32 tmp;
382 int retval = 0;
383 int i;
384
385 ASD(("happy_meal_bb_read: reg=%d ", reg));
386
387
388 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
389
390
391 for (i = 0; i < 32; i++)
392 BB_PUT_BIT(hp, tregs, 1);
393
394
395 BB_PUT_BIT(hp, tregs, 0);
396 BB_PUT_BIT(hp, tregs, 1);
397 BB_PUT_BIT(hp, tregs, 1);
398 BB_PUT_BIT(hp, tregs, 0);
399
400
401 tmp = hp->paddr & 0xff;
402 for (i = 4; i >= 0; i--)
403 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
404
405
406 tmp = (reg & 0xff);
407 for (i = 4; i >= 0; i--)
408 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
409
410
411 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
412
413
414 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
415 for (i = 15; i >= 0; i--)
416 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
417 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
418 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
419 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
420 ASD(("value=%x\n", retval));
421 return retval;
422}
423
424static void happy_meal_bb_write(struct happy_meal *hp,
425 void __iomem *tregs, int reg,
426 unsigned short value)
427{
428 u32 tmp;
429 int i;
430
431 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
432
433
434 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
435
436
437 for (i = 0; i < 32; i++)
438 BB_PUT_BIT(hp, tregs, 1);
439
440
441 BB_PUT_BIT(hp, tregs, 0);
442 BB_PUT_BIT(hp, tregs, 1);
443 BB_PUT_BIT(hp, tregs, 0);
444 BB_PUT_BIT(hp, tregs, 1);
445
446
447 tmp = (hp->paddr & 0xff);
448 for (i = 4; i >= 0; i--)
449 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
450
451
452 tmp = (reg & 0xff);
453 for (i = 4; i >= 0; i--)
454 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
455
456
457 BB_PUT_BIT(hp, tregs, 1);
458 BB_PUT_BIT(hp, tregs, 0);
459
460 for (i = 15; i >= 0; i--)
461 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
462
463
464 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
465}
466
467#define TCVR_READ_TRIES 16
468
469static int happy_meal_tcvr_read(struct happy_meal *hp,
470 void __iomem *tregs, int reg)
471{
472 int tries = TCVR_READ_TRIES;
473 int retval;
474
475 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
476 if (hp->tcvr_type == none) {
477 ASD(("no transceiver, value=TCVR_FAILURE\n"));
478 return TCVR_FAILURE;
479 }
480
481 if (!(hp->happy_flags & HFLAG_FENABLE)) {
482 ASD(("doing bit bang\n"));
483 return happy_meal_bb_read(hp, tregs, reg);
484 }
485
486 hme_write32(hp, tregs + TCVR_FRAME,
487 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
488 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
489 udelay(20);
490 if (!tries) {
491 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
492 return TCVR_FAILURE;
493 }
494 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
495 ASD(("value=%04x\n", retval));
496 return retval;
497}
498
499#define TCVR_WRITE_TRIES 16
500
501static void happy_meal_tcvr_write(struct happy_meal *hp,
502 void __iomem *tregs, int reg,
503 unsigned short value)
504{
505 int tries = TCVR_WRITE_TRIES;
506
507 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
508
509
510 if (!(hp->happy_flags & HFLAG_FENABLE)) {
511 happy_meal_bb_write(hp, tregs, reg, value);
512 return;
513 }
514
515
516 hme_write32(hp, tregs + TCVR_FRAME,
517 (FRAME_WRITE | (hp->paddr << 23) |
518 ((reg & 0xff) << 18) | (value & 0xffff)));
519 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
520 udelay(20);
521
522
523 if (!tries)
524 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
525
526
527}
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560
561static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
562{
563 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
564
565
566
567
568 if (hp->sw_bmcr & BMCR_FULLDPLX) {
569 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
570 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
571 return 0;
572 }
573
574
575 if (hp->sw_bmcr & BMCR_SPEED100) {
576 hp->sw_bmcr &= ~(BMCR_SPEED100);
577 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
578 return 0;
579 }
580
581
582 return -1;
583}
584
585static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
586{
587 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
588 if (hp->tcvr_type == external)
589 printk("external ");
590 else
591 printk("internal ");
592 printk("transceiver at ");
593 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
594 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
595 if (hp->sw_lpa & LPA_100FULL)
596 printk("100Mb/s, Full Duplex.\n");
597 else
598 printk("100Mb/s, Half Duplex.\n");
599 } else {
600 if (hp->sw_lpa & LPA_10FULL)
601 printk("10Mb/s, Full Duplex.\n");
602 else
603 printk("10Mb/s, Half Duplex.\n");
604 }
605}
606
607static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
608{
609 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
610 if (hp->tcvr_type == external)
611 printk("external ");
612 else
613 printk("internal ");
614 printk("transceiver at ");
615 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
616 if (hp->sw_bmcr & BMCR_SPEED100)
617 printk("100Mb/s, ");
618 else
619 printk("10Mb/s, ");
620 if (hp->sw_bmcr & BMCR_FULLDPLX)
621 printk("Full Duplex.\n");
622 else
623 printk("Half Duplex.\n");
624}
625
626static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
627{
628 int full;
629
630
631
632
633 if (hp->timer_state == arbwait) {
634 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
635 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
636 goto no_response;
637 if (hp->sw_lpa & LPA_100FULL)
638 full = 1;
639 else if (hp->sw_lpa & LPA_100HALF)
640 full = 0;
641 else if (hp->sw_lpa & LPA_10FULL)
642 full = 1;
643 else
644 full = 0;
645 } else {
646
647 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
648 if (hp->sw_bmcr & BMCR_FULLDPLX)
649 full = 1;
650 else
651 full = 0;
652 }
653
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657
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661
662 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
663 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
664 ~(BIGMAC_TXCFG_ENABLE));
665 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
666 barrier();
667 if (full) {
668 hp->happy_flags |= HFLAG_FULL;
669 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
670 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
671 BIGMAC_TXCFG_FULLDPLX);
672 } else {
673 hp->happy_flags &= ~(HFLAG_FULL);
674 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
675 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
676 ~(BIGMAC_TXCFG_FULLDPLX));
677 }
678 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
679 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
680 BIGMAC_TXCFG_ENABLE);
681 return 0;
682no_response:
683 return 1;
684}
685
686static int happy_meal_init(struct happy_meal *hp);
687
688static int is_lucent_phy(struct happy_meal *hp)
689{
690 void __iomem *tregs = hp->tcvregs;
691 unsigned short mr2, mr3;
692 int ret = 0;
693
694 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
695 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
696 if ((mr2 & 0xffff) == 0x0180 &&
697 ((mr3 & 0xffff) >> 10) == 0x1d)
698 ret = 1;
699
700 return ret;
701}
702
703static void happy_meal_timer(unsigned long data)
704{
705 struct happy_meal *hp = (struct happy_meal *) data;
706 void __iomem *tregs = hp->tcvregs;
707 int restart_timer = 0;
708
709 spin_lock_irq(&hp->happy_lock);
710
711 hp->timer_ticks++;
712 switch(hp->timer_state) {
713 case arbwait:
714
715
716
717 if (hp->timer_ticks >= 10) {
718
719 do_force_mode:
720 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
721 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
722 hp->dev->name);
723 hp->sw_bmcr = BMCR_SPEED100;
724 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
725
726 if (!is_lucent_phy(hp)) {
727
728
729
730
731 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
732 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
733 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
734 }
735 hp->timer_state = ltrywait;
736 hp->timer_ticks = 0;
737 restart_timer = 1;
738 } else {
739
740 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
741 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
742 int ret;
743
744
745 ret = set_happy_link_modes(hp, tregs);
746 if (ret) {
747
748
749
750
751
752
753 goto do_force_mode;
754 }
755
756
757 hp->timer_state = lupwait;
758 restart_timer = 1;
759 } else {
760 restart_timer = 1;
761 }
762 }
763 break;
764
765 case lupwait:
766
767
768
769
770
771 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
772 if (hp->sw_bmsr & BMSR_LSTATUS) {
773
774
775
776 display_link_mode(hp, tregs);
777 hp->timer_state = asleep;
778 restart_timer = 0;
779 } else {
780 if (hp->timer_ticks >= 10) {
781 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
782 "not completely up.\n", hp->dev->name);
783 hp->timer_ticks = 0;
784 restart_timer = 1;
785 } else {
786 restart_timer = 1;
787 }
788 }
789 break;
790
791 case ltrywait:
792
793
794
795
796
797 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
798 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
799 if (hp->timer_ticks == 1) {
800 if (!is_lucent_phy(hp)) {
801
802
803
804 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
805 happy_meal_tcvr_write(hp, tregs,
806 DP83840_CSCONFIG, hp->sw_csconfig);
807 }
808 restart_timer = 1;
809 break;
810 }
811 if (hp->timer_ticks == 2) {
812 if (!is_lucent_phy(hp)) {
813 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
814 happy_meal_tcvr_write(hp, tregs,
815 DP83840_CSCONFIG, hp->sw_csconfig);
816 }
817 restart_timer = 1;
818 break;
819 }
820 if (hp->sw_bmsr & BMSR_LSTATUS) {
821
822 display_forced_link_mode(hp, tregs);
823 set_happy_link_modes(hp, tregs);
824 hp->timer_state = asleep;
825 restart_timer = 0;
826 } else {
827 if (hp->timer_ticks >= 4) {
828 int ret;
829
830 ret = try_next_permutation(hp, tregs);
831 if (ret == -1) {
832
833
834
835
836
837 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
838 hp->dev->name);
839
840 ret = happy_meal_init(hp);
841 if (ret) {
842
843 printk(KERN_ERR "%s: Error, cannot re-init the "
844 "Happy Meal.\n", hp->dev->name);
845 }
846 goto out;
847 }
848 if (!is_lucent_phy(hp)) {
849 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
850 DP83840_CSCONFIG);
851 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
852 happy_meal_tcvr_write(hp, tregs,
853 DP83840_CSCONFIG, hp->sw_csconfig);
854 }
855 hp->timer_ticks = 0;
856 restart_timer = 1;
857 } else {
858 restart_timer = 1;
859 }
860 }
861 break;
862
863 case asleep:
864 default:
865
866 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
867 hp->dev->name);
868 restart_timer = 0;
869 hp->timer_ticks = 0;
870 hp->timer_state = asleep;
871 break;
872 };
873
874 if (restart_timer) {
875 hp->happy_timer.expires = jiffies + ((12 * HZ)/10);
876 add_timer(&hp->happy_timer);
877 }
878
879out:
880 spin_unlock_irq(&hp->happy_lock);
881}
882
883#define TX_RESET_TRIES 32
884#define RX_RESET_TRIES 32
885
886
887static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
888{
889 int tries = TX_RESET_TRIES;
890
891 HMD(("happy_meal_tx_reset: reset, "));
892
893
894 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
895 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
896 udelay(20);
897
898
899 if (!tries)
900 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
901
902
903 HMD(("done\n"));
904}
905
906
907static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
908{
909 int tries = RX_RESET_TRIES;
910
911 HMD(("happy_meal_rx_reset: reset, "));
912
913
914 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
915 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
916 udelay(20);
917
918
919 if (!tries)
920 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
921
922
923 HMD(("done\n"));
924}
925
926#define STOP_TRIES 16
927
928
929static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
930{
931 int tries = STOP_TRIES;
932
933 HMD(("happy_meal_stop: reset, "));
934
935
936 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
937 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
938 udelay(20);
939
940
941 if (!tries)
942 printk(KERN_ERR "happy meal: Fry guys.");
943
944
945 HMD(("done\n"));
946}
947
948
949static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
950{
951 struct net_device_stats *stats = &hp->net_stats;
952
953 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
954 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
955
956 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
957 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
958
959 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
960 hme_write32(hp, bregs + BMAC_GLECTR, 0);
961
962 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
963
964 stats->collisions +=
965 (hme_read32(hp, bregs + BMAC_EXCTR) +
966 hme_read32(hp, bregs + BMAC_LTCTR));
967 hme_write32(hp, bregs + BMAC_EXCTR, 0);
968 hme_write32(hp, bregs + BMAC_LTCTR, 0);
969}
970
971
972static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
973{
974 ASD(("happy_meal_poll_stop: "));
975
976
977 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
978 (HFLAG_POLLENABLE | HFLAG_POLL)) {
979 HMD(("not polling, return\n"));
980 return;
981 }
982
983
984 ASD(("were polling, mif ints off, "));
985 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
986
987
988 ASD(("polling off, "));
989 hme_write32(hp, tregs + TCVR_CFG,
990 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
991
992
993 hp->happy_flags &= ~(HFLAG_POLL);
994
995
996 udelay(200);
997 ASD(("done\n"));
998}
999
1000
1001
1002
1003#define TCVR_RESET_TRIES 16
1004#define TCVR_UNISOLATE_TRIES 32
1005
1006
1007static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1008{
1009 u32 tconfig;
1010 int result, tries = TCVR_RESET_TRIES;
1011
1012 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1013 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1014 if (hp->tcvr_type == external) {
1015 ASD(("external<"));
1016 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1017 hp->tcvr_type = internal;
1018 hp->paddr = TCV_PADDR_ITX;
1019 ASD(("ISOLATE,"));
1020 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1021 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1022 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1023 if (result == TCVR_FAILURE) {
1024 ASD(("phyread_fail>\n"));
1025 return -1;
1026 }
1027 ASD(("phyread_ok,PSELECT>"));
1028 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1029 hp->tcvr_type = external;
1030 hp->paddr = TCV_PADDR_ETX;
1031 } else {
1032 if (tconfig & TCV_CFG_MDIO1) {
1033 ASD(("internal<PSELECT,"));
1034 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1035 ASD(("ISOLATE,"));
1036 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1037 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1038 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1039 if (result == TCVR_FAILURE) {
1040 ASD(("phyread_fail>\n"));
1041 return -1;
1042 }
1043 ASD(("phyread_ok,~PSELECT>"));
1044 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1045 hp->tcvr_type = internal;
1046 hp->paddr = TCV_PADDR_ITX;
1047 }
1048 }
1049
1050 ASD(("BMCR_RESET "));
1051 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1052
1053 while (--tries) {
1054 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1055 if (result == TCVR_FAILURE)
1056 return -1;
1057 hp->sw_bmcr = result;
1058 if (!(result & BMCR_RESET))
1059 break;
1060 udelay(20);
1061 }
1062 if (!tries) {
1063 ASD(("BMCR RESET FAILED!\n"));
1064 return -1;
1065 }
1066 ASD(("RESET_OK\n"));
1067
1068
1069 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1070 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1071 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1072 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1073
1074 ASD(("UNISOLATE"));
1075 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1076 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1077
1078 tries = TCVR_UNISOLATE_TRIES;
1079 while (--tries) {
1080 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1081 if (result == TCVR_FAILURE)
1082 return -1;
1083 if (!(result & BMCR_ISOLATE))
1084 break;
1085 udelay(20);
1086 }
1087 if (!tries) {
1088 ASD((" FAILED!\n"));
1089 return -1;
1090 }
1091 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1092 if (!is_lucent_phy(hp)) {
1093 result = happy_meal_tcvr_read(hp, tregs,
1094 DP83840_CSCONFIG);
1095 happy_meal_tcvr_write(hp, tregs,
1096 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1097 }
1098 return 0;
1099}
1100
1101
1102
1103
1104
1105static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1106{
1107 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1108
1109 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1110 if (hp->happy_flags & HFLAG_POLL) {
1111
1112 ASD(("<polling> "));
1113 if (hp->tcvr_type == internal) {
1114 if (tconfig & TCV_CFG_MDIO1) {
1115 ASD(("<internal> <poll stop> "));
1116 happy_meal_poll_stop(hp, tregs);
1117 hp->paddr = TCV_PADDR_ETX;
1118 hp->tcvr_type = external;
1119 ASD(("<external>\n"));
1120 tconfig &= ~(TCV_CFG_PENABLE);
1121 tconfig |= TCV_CFG_PSELECT;
1122 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1123 }
1124 } else {
1125 if (hp->tcvr_type == external) {
1126 ASD(("<external> "));
1127 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1128 ASD(("<poll stop> "));
1129 happy_meal_poll_stop(hp, tregs);
1130 hp->paddr = TCV_PADDR_ITX;
1131 hp->tcvr_type = internal;
1132 ASD(("<internal>\n"));
1133 hme_write32(hp, tregs + TCVR_CFG,
1134 hme_read32(hp, tregs + TCVR_CFG) &
1135 ~(TCV_CFG_PSELECT));
1136 }
1137 ASD(("\n"));
1138 } else {
1139 ASD(("<none>\n"));
1140 }
1141 }
1142 } else {
1143 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1144
1145
1146 ASD(("<not polling> "));
1147 if (reread & TCV_CFG_MDIO1) {
1148 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1149 hp->paddr = TCV_PADDR_ETX;
1150 hp->tcvr_type = external;
1151 ASD(("<external>\n"));
1152 } else {
1153 if (reread & TCV_CFG_MDIO0) {
1154 hme_write32(hp, tregs + TCVR_CFG,
1155 tconfig & ~(TCV_CFG_PSELECT));
1156 hp->paddr = TCV_PADDR_ITX;
1157 hp->tcvr_type = internal;
1158 ASD(("<internal>\n"));
1159 } else {
1160 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1161 hp->tcvr_type = none;
1162 ASD(("<none>\n"));
1163 }
1164 }
1165 }
1166}
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212static void happy_meal_clean_rings(struct happy_meal *hp)
1213{
1214 int i;
1215
1216 for (i = 0; i < RX_RING_SIZE; i++) {
1217 if (hp->rx_skbs[i] != NULL) {
1218 struct sk_buff *skb = hp->rx_skbs[i];
1219 struct happy_meal_rxd *rxd;
1220 u32 dma_addr;
1221
1222 rxd = &hp->happy_block->happy_meal_rxd[i];
1223 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1224 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1225 dev_kfree_skb_any(skb);
1226 hp->rx_skbs[i] = NULL;
1227 }
1228 }
1229
1230 for (i = 0; i < TX_RING_SIZE; i++) {
1231 if (hp->tx_skbs[i] != NULL) {
1232 struct sk_buff *skb = hp->tx_skbs[i];
1233 struct happy_meal_txd *txd;
1234 u32 dma_addr;
1235 int frag;
1236
1237 hp->tx_skbs[i] = NULL;
1238
1239 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1240 txd = &hp->happy_block->happy_meal_txd[i];
1241 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1242 hme_dma_unmap(hp, dma_addr,
1243 (hme_read_desc32(hp, &txd->tx_flags)
1244 & TXFLAG_SIZE),
1245 DMA_TODEVICE);
1246
1247 if (frag != skb_shinfo(skb)->nr_frags)
1248 i++;
1249 }
1250
1251 dev_kfree_skb_any(skb);
1252 }
1253 }
1254}
1255
1256
1257static void happy_meal_init_rings(struct happy_meal *hp)
1258{
1259 struct hmeal_init_block *hb = hp->happy_block;
1260 struct net_device *dev = hp->dev;
1261 int i;
1262
1263 HMD(("happy_meal_init_rings: counters to zero, "));
1264 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1265
1266
1267 HMD(("clean, "));
1268 happy_meal_clean_rings(hp);
1269
1270
1271 HMD(("init rxring, "));
1272 for (i = 0; i < RX_RING_SIZE; i++) {
1273 struct sk_buff *skb;
1274
1275 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1276 if (!skb) {
1277 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1278 continue;
1279 }
1280 hp->rx_skbs[i] = skb;
1281 skb->dev = dev;
1282
1283
1284 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1285 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1286 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1287 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1288 skb_reserve(skb, RX_OFFSET);
1289 }
1290
1291 HMD(("init txring, "));
1292 for (i = 0; i < TX_RING_SIZE; i++)
1293 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1294
1295 HMD(("done\n"));
1296}
1297
1298
1299static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1300 void __iomem *tregs,
1301 struct ethtool_cmd *ep)
1302{
1303 int timeout;
1304
1305
1306 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1307 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1308 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1309 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1310
1311
1312
1313 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1314 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1315
1316 if (hp->sw_bmsr & BMSR_10HALF)
1317 hp->sw_advertise |= (ADVERTISE_10HALF);
1318 else
1319 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1320
1321 if (hp->sw_bmsr & BMSR_10FULL)
1322 hp->sw_advertise |= (ADVERTISE_10FULL);
1323 else
1324 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1325 if (hp->sw_bmsr & BMSR_100HALF)
1326 hp->sw_advertise |= (ADVERTISE_100HALF);
1327 else
1328 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1329 if (hp->sw_bmsr & BMSR_100FULL)
1330 hp->sw_advertise |= (ADVERTISE_100FULL);
1331 else
1332 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1333 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1334
1335
1336
1337
1338
1339
1340
1341#ifdef AUTO_SWITCH_DEBUG
1342 ASD(("%s: Advertising [ ", hp->dev->name));
1343 if (hp->sw_advertise & ADVERTISE_10HALF)
1344 ASD(("10H "));
1345 if (hp->sw_advertise & ADVERTISE_10FULL)
1346 ASD(("10F "));
1347 if (hp->sw_advertise & ADVERTISE_100HALF)
1348 ASD(("100H "));
1349 if (hp->sw_advertise & ADVERTISE_100FULL)
1350 ASD(("100F "));
1351#endif
1352
1353
1354 hp->sw_bmcr |= BMCR_ANENABLE;
1355 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1356
1357
1358 hp->sw_bmcr |= BMCR_ANRESTART;
1359 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1360
1361
1362
1363 timeout = 64;
1364 while (--timeout) {
1365 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1366 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1367 break;
1368 udelay(10);
1369 }
1370 if (!timeout) {
1371 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1372 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1373 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1374 hp->dev->name);
1375 goto force_link;
1376 } else {
1377 hp->timer_state = arbwait;
1378 }
1379 } else {
1380force_link:
1381
1382
1383
1384
1385
1386
1387
1388
1389 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1390 hp->sw_bmcr = BMCR_SPEED100;
1391 } else {
1392 if (ep->speed == SPEED_100)
1393 hp->sw_bmcr = BMCR_SPEED100;
1394 else
1395 hp->sw_bmcr = 0;
1396 if (ep->duplex == DUPLEX_FULL)
1397 hp->sw_bmcr |= BMCR_FULLDPLX;
1398 }
1399 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1400
1401 if (!is_lucent_phy(hp)) {
1402
1403
1404
1405
1406 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1407 DP83840_CSCONFIG);
1408 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1409 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1410 hp->sw_csconfig);
1411 }
1412 hp->timer_state = ltrywait;
1413 }
1414
1415 hp->timer_ticks = 0;
1416 hp->happy_timer.expires = jiffies + (12 * HZ)/10;
1417 hp->happy_timer.data = (unsigned long) hp;
1418 hp->happy_timer.function = &happy_meal_timer;
1419 add_timer(&hp->happy_timer);
1420}
1421
1422
1423static int happy_meal_init(struct happy_meal *hp)
1424{
1425 void __iomem *gregs = hp->gregs;
1426 void __iomem *etxregs = hp->etxregs;
1427 void __iomem *erxregs = hp->erxregs;
1428 void __iomem *bregs = hp->bigmacregs;
1429 void __iomem *tregs = hp->tcvregs;
1430 u32 regtmp, rxcfg;
1431 unsigned char *e = &hp->dev->dev_addr[0];
1432
1433
1434 del_timer(&hp->happy_timer);
1435
1436 HMD(("happy_meal_init: happy_flags[%08x] ",
1437 hp->happy_flags));
1438 if (!(hp->happy_flags & HFLAG_INIT)) {
1439 HMD(("set HFLAG_INIT, "));
1440 hp->happy_flags |= HFLAG_INIT;
1441 happy_meal_get_counters(hp, bregs);
1442 }
1443
1444
1445 HMD(("to happy_meal_poll_stop\n"));
1446 happy_meal_poll_stop(hp, tregs);
1447
1448
1449 HMD(("happy_meal_init: to happy_meal_stop\n"));
1450 happy_meal_stop(hp, gregs);
1451
1452
1453 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1454 happy_meal_init_rings(hp);
1455
1456
1457 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1458 hme_read32(hp, tregs + TCVR_IMASK)));
1459 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1460
1461
1462 if (hp->happy_flags & HFLAG_FENABLE) {
1463 HMD(("use frame old[%08x], ",
1464 hme_read32(hp, tregs + TCVR_CFG)));
1465 hme_write32(hp, tregs + TCVR_CFG,
1466 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1467 } else {
1468 HMD(("use bitbang old[%08x], ",
1469 hme_read32(hp, tregs + TCVR_CFG)));
1470 hme_write32(hp, tregs + TCVR_CFG,
1471 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1472 }
1473
1474
1475 HMD(("to happy_meal_transceiver_check\n"));
1476 happy_meal_transceiver_check(hp, tregs);
1477
1478
1479 HMD(("happy_meal_init: "));
1480 switch(hp->tcvr_type) {
1481 case none:
1482
1483 HMD(("AAIEEE no transceiver type, EAGAIN"));
1484 return -EAGAIN;
1485
1486 case internal:
1487
1488 HMD(("internal, using MII, "));
1489 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1490 break;
1491
1492 case external:
1493
1494 HMD(("external, disable MII, "));
1495 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1496 break;
1497 };
1498
1499 if (happy_meal_tcvr_reset(hp, tregs))
1500 return -EAGAIN;
1501
1502
1503 HMD(("tx/rx reset, "));
1504 happy_meal_tx_reset(hp, bregs);
1505 happy_meal_rx_reset(hp, bregs);
1506
1507
1508 HMD(("jsize/ipg1/ipg2, "));
1509 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1510 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1511 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1512
1513
1514 HMD(("rseed/macaddr, "));
1515
1516
1517 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1518
1519 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1520 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1521 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1522
1523 HMD(("htable, "));
1524 if ((hp->dev->flags & IFF_ALLMULTI) ||
1525 (hp->dev->mc_count > 64)) {
1526 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1527 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1528 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1529 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1530 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1531 u16 hash_table[4];
1532 struct dev_mc_list *dmi = hp->dev->mc_list;
1533 char *addrs;
1534 int i;
1535 u32 crc;
1536
1537 for (i = 0; i < 4; i++)
1538 hash_table[i] = 0;
1539
1540 for (i = 0; i < hp->dev->mc_count; i++) {
1541 addrs = dmi->dmi_addr;
1542 dmi = dmi->next;
1543
1544 if (!(*addrs & 1))
1545 continue;
1546
1547 crc = ether_crc_le(6, addrs);
1548 crc >>= 26;
1549 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1550 }
1551 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1552 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1553 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1554 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1555 } else {
1556 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1557 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1558 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1559 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1560 }
1561
1562
1563 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1564 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1565 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1566 hme_write32(hp, erxregs + ERX_RING,
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1568 hme_write32(hp, etxregs + ETX_RING,
1569 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1570
1571
1572
1573
1574
1575
1576 if (hme_read32(hp, erxregs + ERX_RING) !=
1577 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1578 hme_write32(hp, erxregs + ERX_RING,
1579 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1580 | 0x4);
1581
1582
1583 HMD(("happy_meal_init: old[%08x] bursts<",
1584 hme_read32(hp, gregs + GREG_CFG)));
1585
1586#ifndef CONFIG_SPARC
1587
1588 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1589#else
1590 if ((hp->happy_bursts & DMA_BURST64) &&
1591 ((hp->happy_flags & HFLAG_PCI) != 0
1592#ifdef CONFIG_SBUS
1593 || sbus_can_burst64(hp->happy_dev)
1594#endif
1595 || 0)) {
1596 u32 gcfg = GREG_CFG_BURST64;
1597
1598
1599
1600
1601
1602#ifdef CONFIG_SBUS
1603 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1604 sbus_can_dma_64bit(hp->happy_dev)) {
1605 sbus_set_sbus64(hp->happy_dev,
1606 hp->happy_bursts);
1607 gcfg |= GREG_CFG_64BIT;
1608 }
1609#endif
1610
1611 HMD(("64>"));
1612 hme_write32(hp, gregs + GREG_CFG, gcfg);
1613 } else if (hp->happy_bursts & DMA_BURST32) {
1614 HMD(("32>"));
1615 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1616 } else if (hp->happy_bursts & DMA_BURST16) {
1617 HMD(("16>"));
1618 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1619 } else {
1620 HMD(("XXX>"));
1621 hme_write32(hp, gregs + GREG_CFG, 0);
1622 }
1623#endif
1624
1625
1626 HMD((", enable global interrupts, "));
1627 hme_write32(hp, gregs + GREG_IMASK,
1628 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1629 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1630
1631
1632 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1633 hme_read32(hp, etxregs + ETX_RSIZE)));
1634 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1635
1636
1637 HMD(("tx dma enable old[%08x], ",
1638 hme_read32(hp, etxregs + ETX_CFG)));
1639 hme_write32(hp, etxregs + ETX_CFG,
1640 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1641
1642
1643
1644
1645
1646
1647 HMD(("erx regs bug old[%08x]\n",
1648 hme_read32(hp, erxregs + ERX_CFG)));
1649 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1650 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1651 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1652 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1653 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1654 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1655 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1656
1657 }
1658
1659
1660 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1661 hme_read32(hp, bregs + BMAC_RXCFG)));
1662 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1663 if (hp->dev->flags & IFF_PROMISC)
1664 rxcfg |= BIGMAC_RXCFG_PMISC;
1665 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1666
1667
1668 udelay(10);
1669
1670
1671 HMD(("BIGMAC init, "));
1672 regtmp = 0;
1673 if (hp->happy_flags & HFLAG_FULL)
1674 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1675
1676
1677
1678
1679 hme_write32(hp, bregs + BMAC_TXCFG, regtmp );
1680
1681
1682 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1683
1684
1685 regtmp = BIGMAC_XCFG_ODENABLE;
1686
1687
1688 if (hp->happy_flags & HFLAG_LANCE)
1689 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1690
1691
1692 if (hp->tcvr_type == external)
1693 regtmp |= BIGMAC_XCFG_MIIDISAB;
1694
1695 HMD(("XIF config old[%08x], ",
1696 hme_read32(hp, bregs + BMAC_XIFCFG)));
1697 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1698
1699
1700 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1701 hme_read32(hp, bregs + BMAC_TXCFG),
1702 hme_read32(hp, bregs + BMAC_RXCFG)));
1703
1704
1705 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1706 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1707
1708 hme_write32(hp, bregs + BMAC_TXCFG,
1709 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1710 hme_write32(hp, bregs + BMAC_RXCFG,
1711 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1712
1713
1714 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1715
1716
1717 return 0;
1718}
1719
1720
1721static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1722{
1723 void __iomem *tregs = hp->tcvregs;
1724 void __iomem *bregs = hp->bigmacregs;
1725 void __iomem *gregs = hp->gregs;
1726
1727 happy_meal_stop(hp, gregs);
1728 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1729 if (hp->happy_flags & HFLAG_FENABLE)
1730 hme_write32(hp, tregs + TCVR_CFG,
1731 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1732 else
1733 hme_write32(hp, tregs + TCVR_CFG,
1734 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1735 happy_meal_transceiver_check(hp, tregs);
1736 switch(hp->tcvr_type) {
1737 case none:
1738 return;
1739 case internal:
1740 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1741 break;
1742 case external:
1743 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1744 break;
1745 };
1746 if (happy_meal_tcvr_reset(hp, tregs))
1747 return;
1748
1749
1750 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1751 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1752
1753
1754 if (hp->sw_bmsr & BMSR_10HALF)
1755 hp->sw_advertise |= (ADVERTISE_10HALF);
1756 else
1757 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1758
1759 if (hp->sw_bmsr & BMSR_10FULL)
1760 hp->sw_advertise |= (ADVERTISE_10FULL);
1761 else
1762 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1763 if (hp->sw_bmsr & BMSR_100HALF)
1764 hp->sw_advertise |= (ADVERTISE_100HALF);
1765 else
1766 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1767 if (hp->sw_bmsr & BMSR_100FULL)
1768 hp->sw_advertise |= (ADVERTISE_100FULL);
1769 else
1770 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1771
1772
1773 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1774}
1775
1776
1777
1778
1779
1780
1781static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1782{
1783 int reset = 0;
1784
1785
1786 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1787 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1788 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1789 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1790 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1791 GREG_STAT_SLVPERR))
1792 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1793 hp->dev->name, status);
1794
1795 if (status & GREG_STAT_RFIFOVF) {
1796
1797
1798 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1799 }
1800
1801 if (status & GREG_STAT_STSTERR) {
1802
1803 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1804 reset = 1;
1805 }
1806
1807 if (status & GREG_STAT_TFIFO_UND) {
1808
1809 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1810 hp->dev->name);
1811 reset = 1;
1812 }
1813
1814 if (status & GREG_STAT_MAXPKTERR) {
1815
1816
1817
1818 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1819 reset = 1;
1820 }
1821
1822 if (status & GREG_STAT_NORXD) {
1823
1824
1825
1826
1827
1828 printk(KERN_INFO "%s: Happy Meal out of receive "
1829 "descriptors, packet dropped.\n",
1830 hp->dev->name);
1831 }
1832
1833 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1834
1835 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1836 if (status & GREG_STAT_RXERR)
1837 printk("GenericError ");
1838 if (status & GREG_STAT_RXPERR)
1839 printk("ParityError ");
1840 if (status & GREG_STAT_RXTERR)
1841 printk("RxTagBotch ");
1842 printk("]\n");
1843 reset = 1;
1844 }
1845
1846 if (status & GREG_STAT_EOPERR) {
1847
1848
1849
1850 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1851 hp->dev->name);
1852 reset = 1;
1853 }
1854
1855 if (status & GREG_STAT_MIFIRQ) {
1856
1857 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1858 }
1859
1860 if (status &
1861 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1862
1863 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1864 if (status & GREG_STAT_TXEACK)
1865 printk("GenericError ");
1866 if (status & GREG_STAT_TXLERR)
1867 printk("LateError ");
1868 if (status & GREG_STAT_TXPERR)
1869 printk("ParityErro ");
1870 if (status & GREG_STAT_TXTERR)
1871 printk("TagBotch ");
1872 printk("]\n");
1873 reset = 1;
1874 }
1875
1876 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1877
1878
1879
1880 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1881 hp->dev->name,
1882 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1883 reset = 1;
1884 }
1885
1886 if (reset) {
1887 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1888 happy_meal_init(hp);
1889 return 1;
1890 }
1891 return 0;
1892}
1893
1894
1895static void happy_meal_mif_interrupt(struct happy_meal *hp)
1896{
1897 void __iomem *tregs = hp->tcvregs;
1898
1899 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1900 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1901 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1902
1903
1904 if (hp->sw_lpa & LPA_100FULL) {
1905 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1906 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1907 } else if (hp->sw_lpa & LPA_100HALF) {
1908 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1909 hp->sw_bmcr |= BMCR_SPEED100;
1910 } else if (hp->sw_lpa & LPA_10FULL) {
1911 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1912 hp->sw_bmcr |= BMCR_FULLDPLX;
1913 } else {
1914 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1915 }
1916 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1917
1918
1919 happy_meal_poll_stop(hp, tregs);
1920}
1921
1922#ifdef TXDEBUG
1923#define TXD(x) printk x
1924#else
1925#define TXD(x)
1926#endif
1927
1928
1929static void happy_meal_tx(struct happy_meal *hp)
1930{
1931 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1932 struct happy_meal_txd *this;
1933 struct net_device *dev = hp->dev;
1934 int elem;
1935
1936 elem = hp->tx_old;
1937 TXD(("TX<"));
1938 while (elem != hp->tx_new) {
1939 struct sk_buff *skb;
1940 u32 flags, dma_addr, dma_len;
1941 int frag;
1942
1943 TXD(("[%d]", elem));
1944 this = &txbase[elem];
1945 flags = hme_read_desc32(hp, &this->tx_flags);
1946 if (flags & TXFLAG_OWN)
1947 break;
1948 skb = hp->tx_skbs[elem];
1949 if (skb_shinfo(skb)->nr_frags) {
1950 int last;
1951
1952 last = elem + skb_shinfo(skb)->nr_frags;
1953 last &= (TX_RING_SIZE - 1);
1954 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1955 if (flags & TXFLAG_OWN)
1956 break;
1957 }
1958 hp->tx_skbs[elem] = NULL;
1959 hp->net_stats.tx_bytes += skb->len;
1960
1961 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1962 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1963 dma_len = hme_read_desc32(hp, &this->tx_flags);
1964
1965 dma_len &= TXFLAG_SIZE;
1966 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1967
1968 elem = NEXT_TX(elem);
1969 this = &txbase[elem];
1970 }
1971
1972 dev_kfree_skb_irq(skb);
1973 hp->net_stats.tx_packets++;
1974 }
1975 hp->tx_old = elem;
1976 TXD((">"));
1977
1978 if (netif_queue_stopped(dev) &&
1979 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1980 netif_wake_queue(dev);
1981}
1982
1983#ifdef RXDEBUG
1984#define RXD(x) printk x
1985#else
1986#define RXD(x)
1987#endif
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1999{
2000 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2001 struct happy_meal_rxd *this;
2002 int elem = hp->rx_new, drops = 0;
2003 u32 flags;
2004
2005 RXD(("RX<"));
2006 this = &rxbase[elem];
2007 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2008 struct sk_buff *skb;
2009 int len = flags >> 16;
2010 u16 csum = flags & RXFLAG_CSUM;
2011 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2012
2013 RXD(("[%d ", elem));
2014
2015
2016 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2017 RXD(("ERR(%08x)]", flags));
2018 hp->net_stats.rx_errors++;
2019 if (len < ETH_ZLEN)
2020 hp->net_stats.rx_length_errors++;
2021 if (len & (RXFLAG_OVERFLOW >> 16)) {
2022 hp->net_stats.rx_over_errors++;
2023 hp->net_stats.rx_fifo_errors++;
2024 }
2025
2026
2027 drop_it:
2028 hp->net_stats.rx_dropped++;
2029 hme_write_rxd(hp, this,
2030 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2031 dma_addr);
2032 goto next;
2033 }
2034 skb = hp->rx_skbs[elem];
2035 if (len > RX_COPY_THRESHOLD) {
2036 struct sk_buff *new_skb;
2037
2038
2039 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2040 if (new_skb == NULL) {
2041 drops++;
2042 goto drop_it;
2043 }
2044 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2045 hp->rx_skbs[elem] = new_skb;
2046 new_skb->dev = dev;
2047 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2048 hme_write_rxd(hp, this,
2049 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2050 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2051 skb_reserve(new_skb, RX_OFFSET);
2052
2053
2054 skb_trim(skb, len);
2055 } else {
2056 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2057
2058 if (copy_skb == NULL) {
2059 drops++;
2060 goto drop_it;
2061 }
2062
2063 skb_reserve(copy_skb, 2);
2064 skb_put(copy_skb, len);
2065 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
2066 skb_copy_from_linear_data(skb, copy_skb->data, len);
2067 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2068
2069
2070 hme_write_rxd(hp, this,
2071 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2072 dma_addr);
2073
2074 skb = copy_skb;
2075 }
2076
2077
2078 skb->csum = ntohs(csum ^ 0xffff);
2079 skb->ip_summed = CHECKSUM_COMPLETE;
2080
2081 RXD(("len=%d csum=%4x]", len, csum));
2082 skb->protocol = eth_type_trans(skb, dev);
2083 netif_rx(skb);
2084
2085 dev->last_rx = jiffies;
2086 hp->net_stats.rx_packets++;
2087 hp->net_stats.rx_bytes += len;
2088 next:
2089 elem = NEXT_RX(elem);
2090 this = &rxbase[elem];
2091 }
2092 hp->rx_new = elem;
2093 if (drops)
2094 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2095 RXD((">"));
2096}
2097
2098static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2099{
2100 struct net_device *dev = dev_id;
2101 struct happy_meal *hp = netdev_priv(dev);
2102 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2103
2104 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2105
2106 spin_lock(&hp->happy_lock);
2107
2108 if (happy_status & GREG_STAT_ERRORS) {
2109 HMD(("ERRORS "));
2110 if (happy_meal_is_not_so_happy(hp, happy_status))
2111 goto out;
2112 }
2113
2114 if (happy_status & GREG_STAT_MIFIRQ) {
2115 HMD(("MIFIRQ "));
2116 happy_meal_mif_interrupt(hp);
2117 }
2118
2119 if (happy_status & GREG_STAT_TXALL) {
2120 HMD(("TXALL "));
2121 happy_meal_tx(hp);
2122 }
2123
2124 if (happy_status & GREG_STAT_RXTOHOST) {
2125 HMD(("RXTOHOST "));
2126 happy_meal_rx(hp, dev);
2127 }
2128
2129 HMD(("done\n"));
2130out:
2131 spin_unlock(&hp->happy_lock);
2132
2133 return IRQ_HANDLED;
2134}
2135
2136#ifdef CONFIG_SBUS
2137static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2138{
2139 struct quattro *qp = (struct quattro *) cookie;
2140 int i;
2141
2142 for (i = 0; i < 4; i++) {
2143 struct net_device *dev = qp->happy_meals[i];
2144 struct happy_meal *hp = dev->priv;
2145 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2146
2147 HMD(("quattro_interrupt: status=%08x ", happy_status));
2148
2149 if (!(happy_status & (GREG_STAT_ERRORS |
2150 GREG_STAT_MIFIRQ |
2151 GREG_STAT_TXALL |
2152 GREG_STAT_RXTOHOST)))
2153 continue;
2154
2155 spin_lock(&hp->happy_lock);
2156
2157 if (happy_status & GREG_STAT_ERRORS) {
2158 HMD(("ERRORS "));
2159 if (happy_meal_is_not_so_happy(hp, happy_status))
2160 goto next;
2161 }
2162
2163 if (happy_status & GREG_STAT_MIFIRQ) {
2164 HMD(("MIFIRQ "));
2165 happy_meal_mif_interrupt(hp);
2166 }
2167
2168 if (happy_status & GREG_STAT_TXALL) {
2169 HMD(("TXALL "));
2170 happy_meal_tx(hp);
2171 }
2172
2173 if (happy_status & GREG_STAT_RXTOHOST) {
2174 HMD(("RXTOHOST "));
2175 happy_meal_rx(hp, dev);
2176 }
2177
2178 next:
2179 spin_unlock(&hp->happy_lock);
2180 }
2181 HMD(("done\n"));
2182
2183 return IRQ_HANDLED;
2184}
2185#endif
2186
2187static int happy_meal_open(struct net_device *dev)
2188{
2189 struct happy_meal *hp = dev->priv;
2190 int res;
2191
2192 HMD(("happy_meal_open: "));
2193
2194
2195
2196
2197 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2198 if (request_irq(dev->irq, &happy_meal_interrupt,
2199 IRQF_SHARED, dev->name, (void *)dev)) {
2200 HMD(("EAGAIN\n"));
2201 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2202 dev->irq);
2203
2204 return -EAGAIN;
2205 }
2206 }
2207
2208 HMD(("to happy_meal_init\n"));
2209
2210 spin_lock_irq(&hp->happy_lock);
2211 res = happy_meal_init(hp);
2212 spin_unlock_irq(&hp->happy_lock);
2213
2214 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2215 free_irq(dev->irq, dev);
2216 return res;
2217}
2218
2219static int happy_meal_close(struct net_device *dev)
2220{
2221 struct happy_meal *hp = dev->priv;
2222
2223 spin_lock_irq(&hp->happy_lock);
2224 happy_meal_stop(hp, hp->gregs);
2225 happy_meal_clean_rings(hp);
2226
2227
2228 del_timer(&hp->happy_timer);
2229
2230 spin_unlock_irq(&hp->happy_lock);
2231
2232
2233
2234
2235
2236 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2237 free_irq(dev->irq, dev);
2238
2239 return 0;
2240}
2241
2242#ifdef SXDEBUG
2243#define SXD(x) printk x
2244#else
2245#define SXD(x)
2246#endif
2247
2248static void happy_meal_tx_timeout(struct net_device *dev)
2249{
2250 struct happy_meal *hp = dev->priv;
2251
2252 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2253 tx_dump_log();
2254 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2255 hme_read32(hp, hp->gregs + GREG_STAT),
2256 hme_read32(hp, hp->etxregs + ETX_CFG),
2257 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2258
2259 spin_lock_irq(&hp->happy_lock);
2260 happy_meal_init(hp);
2261 spin_unlock_irq(&hp->happy_lock);
2262
2263 netif_wake_queue(dev);
2264}
2265
2266static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2267{
2268 struct happy_meal *hp = dev->priv;
2269 int entry;
2270 u32 tx_flags;
2271
2272 tx_flags = TXFLAG_OWN;
2273 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2274 const u32 csum_start_off = skb_transport_offset(skb);
2275 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2276
2277 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2278 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2279 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2280 }
2281
2282 spin_lock_irq(&hp->happy_lock);
2283
2284 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2285 netif_stop_queue(dev);
2286 spin_unlock_irq(&hp->happy_lock);
2287 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2288 dev->name);
2289 return 1;
2290 }
2291
2292 entry = hp->tx_new;
2293 SXD(("SX<l[%d]e[%d]>", len, entry));
2294 hp->tx_skbs[entry] = skb;
2295
2296 if (skb_shinfo(skb)->nr_frags == 0) {
2297 u32 mapping, len;
2298
2299 len = skb->len;
2300 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2301 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2302 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2303 (tx_flags | (len & TXFLAG_SIZE)),
2304 mapping);
2305 entry = NEXT_TX(entry);
2306 } else {
2307 u32 first_len, first_mapping;
2308 int frag, first_entry = entry;
2309
2310
2311
2312
2313 first_len = skb_headlen(skb);
2314 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2315 entry = NEXT_TX(entry);
2316
2317 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2318 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2319 u32 len, mapping, this_txflags;
2320
2321 len = this_frag->size;
2322 mapping = hme_dma_map(hp,
2323 ((void *) page_address(this_frag->page) +
2324 this_frag->page_offset),
2325 len, DMA_TODEVICE);
2326 this_txflags = tx_flags;
2327 if (frag == skb_shinfo(skb)->nr_frags - 1)
2328 this_txflags |= TXFLAG_EOP;
2329 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2330 (this_txflags | (len & TXFLAG_SIZE)),
2331 mapping);
2332 entry = NEXT_TX(entry);
2333 }
2334 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2335 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2336 first_mapping);
2337 }
2338
2339 hp->tx_new = entry;
2340
2341 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2342 netif_stop_queue(dev);
2343
2344
2345 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2346
2347 spin_unlock_irq(&hp->happy_lock);
2348
2349 dev->trans_start = jiffies;
2350
2351 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2352 return 0;
2353}
2354
2355static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2356{
2357 struct happy_meal *hp = dev->priv;
2358
2359 spin_lock_irq(&hp->happy_lock);
2360 happy_meal_get_counters(hp, hp->bigmacregs);
2361 spin_unlock_irq(&hp->happy_lock);
2362
2363 return &hp->net_stats;
2364}
2365
2366static void happy_meal_set_multicast(struct net_device *dev)
2367{
2368 struct happy_meal *hp = dev->priv;
2369 void __iomem *bregs = hp->bigmacregs;
2370 struct dev_mc_list *dmi = dev->mc_list;
2371 char *addrs;
2372 int i;
2373 u32 crc;
2374
2375 spin_lock_irq(&hp->happy_lock);
2376
2377 netif_stop_queue(dev);
2378
2379 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2380 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2381 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2382 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2383 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2384 } else if (dev->flags & IFF_PROMISC) {
2385 hme_write32(hp, bregs + BMAC_RXCFG,
2386 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2387 } else {
2388 u16 hash_table[4];
2389
2390 for (i = 0; i < 4; i++)
2391 hash_table[i] = 0;
2392
2393 for (i = 0; i < dev->mc_count; i++) {
2394 addrs = dmi->dmi_addr;
2395 dmi = dmi->next;
2396
2397 if (!(*addrs & 1))
2398 continue;
2399
2400 crc = ether_crc_le(6, addrs);
2401 crc >>= 26;
2402 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2403 }
2404 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2405 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2406 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2407 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2408 }
2409
2410 netif_wake_queue(dev);
2411
2412 spin_unlock_irq(&hp->happy_lock);
2413}
2414
2415
2416static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2417{
2418 struct happy_meal *hp = dev->priv;
2419
2420 cmd->supported =
2421 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2422 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2423 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2424
2425
2426 cmd->port = PORT_TP;
2427 cmd->transceiver = XCVR_INTERNAL;
2428 cmd->phy_address = 0;
2429
2430
2431 spin_lock_irq(&hp->happy_lock);
2432 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2433 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2434 spin_unlock_irq(&hp->happy_lock);
2435
2436 if (hp->sw_bmcr & BMCR_ANENABLE) {
2437 cmd->autoneg = AUTONEG_ENABLE;
2438 cmd->speed =
2439 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2440 SPEED_100 : SPEED_10;
2441 if (cmd->speed == SPEED_100)
2442 cmd->duplex =
2443 (hp->sw_lpa & (LPA_100FULL)) ?
2444 DUPLEX_FULL : DUPLEX_HALF;
2445 else
2446 cmd->duplex =
2447 (hp->sw_lpa & (LPA_10FULL)) ?
2448 DUPLEX_FULL : DUPLEX_HALF;
2449 } else {
2450 cmd->autoneg = AUTONEG_DISABLE;
2451 cmd->speed =
2452 (hp->sw_bmcr & BMCR_SPEED100) ?
2453 SPEED_100 : SPEED_10;
2454 cmd->duplex =
2455 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2456 DUPLEX_FULL : DUPLEX_HALF;
2457 }
2458 return 0;
2459}
2460
2461static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2462{
2463 struct happy_meal *hp = dev->priv;
2464
2465
2466 if (cmd->autoneg != AUTONEG_ENABLE &&
2467 cmd->autoneg != AUTONEG_DISABLE)
2468 return -EINVAL;
2469 if (cmd->autoneg == AUTONEG_DISABLE &&
2470 ((cmd->speed != SPEED_100 &&
2471 cmd->speed != SPEED_10) ||
2472 (cmd->duplex != DUPLEX_HALF &&
2473 cmd->duplex != DUPLEX_FULL)))
2474 return -EINVAL;
2475
2476
2477 spin_lock_irq(&hp->happy_lock);
2478 del_timer(&hp->happy_timer);
2479 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2480 spin_unlock_irq(&hp->happy_lock);
2481
2482 return 0;
2483}
2484
2485static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2486{
2487 struct happy_meal *hp = dev->priv;
2488
2489 strcpy(info->driver, "sunhme");
2490 strcpy(info->version, "2.02");
2491 if (hp->happy_flags & HFLAG_PCI) {
2492 struct pci_dev *pdev = hp->happy_dev;
2493 strcpy(info->bus_info, pci_name(pdev));
2494 }
2495#ifdef CONFIG_SBUS
2496 else {
2497 struct sbus_dev *sdev = hp->happy_dev;
2498 sprintf(info->bus_info, "SBUS:%d",
2499 sdev->slot);
2500 }
2501#endif
2502}
2503
2504static u32 hme_get_link(struct net_device *dev)
2505{
2506 struct happy_meal *hp = dev->priv;
2507
2508 spin_lock_irq(&hp->happy_lock);
2509 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2510 spin_unlock_irq(&hp->happy_lock);
2511
2512 return (hp->sw_bmsr & BMSR_LSTATUS);
2513}
2514
2515static const struct ethtool_ops hme_ethtool_ops = {
2516 .get_settings = hme_get_settings,
2517 .set_settings = hme_set_settings,
2518 .get_drvinfo = hme_get_drvinfo,
2519 .get_link = hme_get_link,
2520};
2521
2522static int hme_version_printed;
2523
2524#ifdef CONFIG_SBUS
2525void __devinit quattro_get_ranges(struct quattro *qp)
2526{
2527 struct sbus_dev *sdev = qp->quattro_dev;
2528 int err;
2529
2530 err = prom_getproperty(sdev->prom_node,
2531 "ranges",
2532 (char *)&qp->ranges[0],
2533 sizeof(qp->ranges));
2534 if (err == 0 || err == -1) {
2535 qp->nranges = 0;
2536 return;
2537 }
2538 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2539}
2540
2541static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2542{
2543 struct sbus_dev *sdev = hp->happy_dev;
2544 int rng;
2545
2546 for (rng = 0; rng < qp->nranges; rng++) {
2547 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2548 int reg;
2549
2550 for (reg = 0; reg < 5; reg++) {
2551 if (sdev->reg_addrs[reg].which_io ==
2552 rngp->ot_child_space)
2553 break;
2554 }
2555 if (reg == 5)
2556 continue;
2557
2558 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2559 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2560 }
2561}
2562
2563
2564
2565
2566
2567
2568static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
2569{
2570 struct sbus_dev *sdev;
2571 struct quattro *qp;
2572 int i;
2573
2574 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2575 for (i = 0, sdev = qp->quattro_dev;
2576 (sdev != NULL) && (i < 4);
2577 sdev = sdev->next, i++) {
2578 if (sdev == goal_sdev)
2579 return qp;
2580 }
2581 }
2582
2583 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2584 if (qp != NULL) {
2585 int i;
2586
2587 for (i = 0; i < 4; i++)
2588 qp->happy_meals[i] = NULL;
2589
2590 qp->quattro_dev = goal_sdev;
2591 qp->next = qfe_sbus_list;
2592 qfe_sbus_list = qp;
2593 quattro_get_ranges(qp);
2594 }
2595 return qp;
2596}
2597
2598
2599
2600
2601static void __init quattro_sbus_register_irqs(void)
2602{
2603 struct quattro *qp;
2604
2605 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2606 struct sbus_dev *sdev = qp->quattro_dev;
2607 int err;
2608
2609 err = request_irq(sdev->irqs[0],
2610 quattro_sbus_interrupt,
2611 IRQF_SHARED, "Quattro",
2612 qp);
2613 if (err != 0) {
2614 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2615 panic("QFE request irq");
2616 }
2617 }
2618}
2619
2620static void quattro_sbus_free_irqs(void)
2621{
2622 struct quattro *qp;
2623
2624 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2625 struct sbus_dev *sdev = qp->quattro_dev;
2626
2627 free_irq(sdev->irqs[0], qp);
2628 }
2629}
2630#endif
2631
2632#ifdef CONFIG_PCI
2633static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
2634{
2635 struct pci_dev *bdev = pdev->bus->self;
2636 struct quattro *qp;
2637
2638 if (!bdev) return NULL;
2639 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2640 struct pci_dev *qpdev = qp->quattro_dev;
2641
2642 if (qpdev == bdev)
2643 return qp;
2644 }
2645 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2646 if (qp != NULL) {
2647 int i;
2648
2649 for (i = 0; i < 4; i++)
2650 qp->happy_meals[i] = NULL;
2651
2652 qp->quattro_dev = bdev;
2653 qp->next = qfe_pci_list;
2654 qfe_pci_list = qp;
2655
2656
2657 qp->nranges = 0;
2658 }
2659 return qp;
2660}
2661#endif
2662
2663#ifdef CONFIG_SBUS
2664static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
2665{
2666 struct device_node *dp = sdev->ofdev.node;
2667 struct quattro *qp = NULL;
2668 struct happy_meal *hp;
2669 struct net_device *dev;
2670 int i, qfe_slot = -1;
2671 int err = -ENODEV;
2672 DECLARE_MAC_BUF(mac);
2673
2674 if (is_qfe) {
2675 qp = quattro_sbus_find(sdev);
2676 if (qp == NULL)
2677 goto err_out;
2678 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2679 if (qp->happy_meals[qfe_slot] == NULL)
2680 break;
2681 if (qfe_slot == 4)
2682 goto err_out;
2683 }
2684
2685 err = -ENOMEM;
2686 dev = alloc_etherdev(sizeof(struct happy_meal));
2687 if (!dev)
2688 goto err_out;
2689 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
2690
2691 if (hme_version_printed++ == 0)
2692 printk(KERN_INFO "%s", version);
2693
2694
2695
2696
2697 for (i = 0; i < 6; i++) {
2698 if (macaddr[i] != 0)
2699 break;
2700 }
2701 if (i < 6) {
2702 for (i = 0; i < 6; i++)
2703 dev->dev_addr[i] = macaddr[i];
2704 macaddr[5]++;
2705 } else {
2706 const unsigned char *addr;
2707 int len;
2708
2709 addr = of_get_property(dp, "local-mac-address", &len);
2710
2711 if (qfe_slot != -1 && addr && len == 6)
2712 memcpy(dev->dev_addr, addr, 6);
2713 else
2714 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2715 }
2716
2717 hp = dev->priv;
2718
2719 hp->happy_dev = sdev;
2720
2721 spin_lock_init(&hp->happy_lock);
2722
2723 err = -ENODEV;
2724 if (sdev->num_registers != 5) {
2725 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
2726 sdev->num_registers);
2727 goto err_out_free_netdev;
2728 }
2729
2730 if (qp != NULL) {
2731 hp->qfe_parent = qp;
2732 hp->qfe_ent = qfe_slot;
2733 qp->happy_meals[qfe_slot] = dev;
2734 quattro_apply_ranges(qp, hp);
2735 }
2736
2737 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2738 GREG_REG_SIZE, "HME Global Regs");
2739 if (!hp->gregs) {
2740 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2741 goto err_out_free_netdev;
2742 }
2743
2744 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2745 ETX_REG_SIZE, "HME TX Regs");
2746 if (!hp->etxregs) {
2747 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2748 goto err_out_iounmap;
2749 }
2750
2751 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2752 ERX_REG_SIZE, "HME RX Regs");
2753 if (!hp->erxregs) {
2754 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2755 goto err_out_iounmap;
2756 }
2757
2758 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2759 BMAC_REG_SIZE, "HME BIGMAC Regs");
2760 if (!hp->bigmacregs) {
2761 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2762 goto err_out_iounmap;
2763 }
2764
2765 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2766 TCVR_REG_SIZE, "HME Tranceiver Regs");
2767 if (!hp->tcvregs) {
2768 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2769 goto err_out_iounmap;
2770 }
2771
2772 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2773 if (hp->hm_revision == 0xff)
2774 hp->hm_revision = 0xa0;
2775
2776
2777 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2778 hp->happy_flags = HFLAG_20_21;
2779 else if (hp->hm_revision != 0xa0)
2780 hp->happy_flags = HFLAG_NOT_A0;
2781
2782 if (qp != NULL)
2783 hp->happy_flags |= HFLAG_QUATTRO;
2784
2785
2786 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
2787 "burst-sizes", 0x00);
2788
2789 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2790 PAGE_SIZE,
2791 &hp->hblock_dvma);
2792 err = -ENOMEM;
2793 if (!hp->happy_block) {
2794 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2795 goto err_out_iounmap;
2796 }
2797
2798
2799 hp->linkcheck = 0;
2800
2801
2802 hp->timer_state = asleep;
2803 hp->timer_ticks = 0;
2804
2805 init_timer(&hp->happy_timer);
2806
2807 hp->dev = dev;
2808 dev->open = &happy_meal_open;
2809 dev->stop = &happy_meal_close;
2810 dev->hard_start_xmit = &happy_meal_start_xmit;
2811 dev->get_stats = &happy_meal_get_stats;
2812 dev->set_multicast_list = &happy_meal_set_multicast;
2813 dev->tx_timeout = &happy_meal_tx_timeout;
2814 dev->watchdog_timeo = 5*HZ;
2815 dev->ethtool_ops = &hme_ethtool_ops;
2816
2817
2818 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2819
2820 dev->irq = sdev->irqs[0];
2821
2822#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2823
2824 hp->read_desc32 = sbus_hme_read_desc32;
2825 hp->write_txd = sbus_hme_write_txd;
2826 hp->write_rxd = sbus_hme_write_rxd;
2827 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2828 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2829 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2830 sbus_dma_sync_single_for_cpu;
2831 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2832 sbus_dma_sync_single_for_device;
2833 hp->read32 = sbus_hme_read32;
2834 hp->write32 = sbus_hme_write32;
2835#endif
2836
2837
2838
2839
2840 spin_lock_irq(&hp->happy_lock);
2841 happy_meal_set_initial_advertisement(hp);
2842 spin_unlock_irq(&hp->happy_lock);
2843
2844 if (register_netdev(hp->dev)) {
2845 printk(KERN_ERR "happymeal: Cannot register net device, "
2846 "aborting.\n");
2847 goto err_out_free_consistent;
2848 }
2849
2850 dev_set_drvdata(&sdev->ofdev.dev, hp);
2851
2852 if (qfe_slot != -1)
2853 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2854 dev->name, qfe_slot);
2855 else
2856 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2857 dev->name);
2858
2859 printk("%s\n", print_mac(mac, dev->dev_addr));
2860
2861 return 0;
2862
2863err_out_free_consistent:
2864 sbus_free_consistent(hp->happy_dev,
2865 PAGE_SIZE,
2866 hp->happy_block,
2867 hp->hblock_dvma);
2868
2869err_out_iounmap:
2870 if (hp->gregs)
2871 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2872 if (hp->etxregs)
2873 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2874 if (hp->erxregs)
2875 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2876 if (hp->bigmacregs)
2877 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2878 if (hp->tcvregs)
2879 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2880
2881err_out_free_netdev:
2882 free_netdev(dev);
2883
2884err_out:
2885 return err;
2886}
2887#endif
2888
2889#ifdef CONFIG_PCI
2890#ifndef CONFIG_SPARC
2891static int is_quattro_p(struct pci_dev *pdev)
2892{
2893 struct pci_dev *busdev = pdev->bus->self;
2894 struct list_head *tmp;
2895 int n_hmes;
2896
2897 if (busdev == NULL ||
2898 busdev->vendor != PCI_VENDOR_ID_DEC ||
2899 busdev->device != PCI_DEVICE_ID_DEC_21153)
2900 return 0;
2901
2902 n_hmes = 0;
2903 tmp = pdev->bus->devices.next;
2904 while (tmp != &pdev->bus->devices) {
2905 struct pci_dev *this_pdev = pci_dev_b(tmp);
2906
2907 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2908 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2909 n_hmes++;
2910
2911 tmp = tmp->next;
2912 }
2913
2914 if (n_hmes != 4)
2915 return 0;
2916
2917 return 1;
2918}
2919
2920
2921static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2922{
2923 int this_offset;
2924
2925 for (this_offset = 0x20; this_offset < len; this_offset++) {
2926 void __iomem *p = rom_base + this_offset;
2927
2928 if (readb(p + 0) != 0x90 ||
2929 readb(p + 1) != 0x00 ||
2930 readb(p + 2) != 0x09 ||
2931 readb(p + 3) != 0x4e ||
2932 readb(p + 4) != 0x41 ||
2933 readb(p + 5) != 0x06)
2934 continue;
2935
2936 this_offset += 6;
2937 p += 6;
2938
2939 if (index == 0) {
2940 int i;
2941
2942 for (i = 0; i < 6; i++)
2943 dev_addr[i] = readb(p + i);
2944 return 1;
2945 }
2946 index--;
2947 }
2948 return 0;
2949}
2950
2951static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2952{
2953 size_t size;
2954 void __iomem *p = pci_map_rom(pdev, &size);
2955
2956 if (p) {
2957 int index = 0;
2958 int found;
2959
2960 if (is_quattro_p(pdev))
2961 index = PCI_SLOT(pdev->devfn);
2962
2963 found = readb(p) == 0x55 &&
2964 readb(p + 1) == 0xaa &&
2965 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2966 pci_unmap_rom(pdev, p);
2967 if (found)
2968 return;
2969 }
2970
2971
2972 dev_addr[0] = 0x08;
2973 dev_addr[1] = 0x00;
2974 dev_addr[2] = 0x20;
2975 get_random_bytes(&dev_addr[3], 3);
2976 return;
2977}
2978#endif
2979
2980static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2981 const struct pci_device_id *ent)
2982{
2983 struct quattro *qp = NULL;
2984#ifdef CONFIG_SPARC
2985 struct device_node *dp;
2986#endif
2987 struct happy_meal *hp;
2988 struct net_device *dev;
2989 void __iomem *hpreg_base;
2990 unsigned long hpreg_res;
2991 int i, qfe_slot = -1;
2992 char prom_name[64];
2993 int err;
2994 DECLARE_MAC_BUF(mac);
2995
2996
2997#ifdef CONFIG_SPARC
2998 dp = pci_device_to_OF_node(pdev);
2999 strcpy(prom_name, dp->name);
3000#else
3001 if (is_quattro_p(pdev))
3002 strcpy(prom_name, "SUNW,qfe");
3003 else
3004 strcpy(prom_name, "SUNW,hme");
3005#endif
3006
3007 err = -ENODEV;
3008
3009 if (pci_enable_device(pdev))
3010 goto err_out;
3011 pci_set_master(pdev);
3012
3013 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3014 qp = quattro_pci_find(pdev);
3015 if (qp == NULL)
3016 goto err_out;
3017 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3018 if (qp->happy_meals[qfe_slot] == NULL)
3019 break;
3020 if (qfe_slot == 4)
3021 goto err_out;
3022 }
3023
3024 dev = alloc_etherdev(sizeof(struct happy_meal));
3025 err = -ENOMEM;
3026 if (!dev)
3027 goto err_out;
3028 SET_NETDEV_DEV(dev, &pdev->dev);
3029
3030 if (hme_version_printed++ == 0)
3031 printk(KERN_INFO "%s", version);
3032
3033 dev->base_addr = (long) pdev;
3034
3035 hp = (struct happy_meal *)dev->priv;
3036 memset(hp, 0, sizeof(*hp));
3037
3038 hp->happy_dev = pdev;
3039
3040 spin_lock_init(&hp->happy_lock);
3041
3042 if (qp != NULL) {
3043 hp->qfe_parent = qp;
3044 hp->qfe_ent = qfe_slot;
3045 qp->happy_meals[qfe_slot] = dev;
3046 }
3047
3048 hpreg_res = pci_resource_start(pdev, 0);
3049 err = -ENODEV;
3050 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3051 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3052 goto err_out_clear_quattro;
3053 }
3054 if (pci_request_regions(pdev, DRV_NAME)) {
3055 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3056 "aborting.\n");
3057 goto err_out_clear_quattro;
3058 }
3059
3060 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3061 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3062 goto err_out_free_res;
3063 }
3064
3065 for (i = 0; i < 6; i++) {
3066 if (macaddr[i] != 0)
3067 break;
3068 }
3069 if (i < 6) {
3070 for (i = 0; i < 6; i++)
3071 dev->dev_addr[i] = macaddr[i];
3072 macaddr[5]++;
3073 } else {
3074#ifdef CONFIG_SPARC
3075 const unsigned char *addr;
3076 int len;
3077
3078 if (qfe_slot != -1 &&
3079 (addr = of_get_property(dp,
3080 "local-mac-address", &len)) != NULL
3081 && len == 6) {
3082 memcpy(dev->dev_addr, addr, 6);
3083 } else {
3084 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3085 }
3086#else
3087 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3088#endif
3089 }
3090
3091
3092 hp->gregs = (hpreg_base + 0x0000UL);
3093 hp->etxregs = (hpreg_base + 0x2000UL);
3094 hp->erxregs = (hpreg_base + 0x4000UL);
3095 hp->bigmacregs = (hpreg_base + 0x6000UL);
3096 hp->tcvregs = (hpreg_base + 0x7000UL);
3097
3098#ifdef CONFIG_SPARC
3099 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3100 if (hp->hm_revision == 0xff)
3101 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3102#else
3103
3104 hp->hm_revision = 0x20;
3105#endif
3106
3107
3108 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3109 hp->happy_flags = HFLAG_20_21;
3110 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3111 hp->happy_flags = HFLAG_NOT_A0;
3112
3113 if (qp != NULL)
3114 hp->happy_flags |= HFLAG_QUATTRO;
3115
3116
3117 hp->happy_flags |= HFLAG_PCI;
3118
3119#ifdef CONFIG_SPARC
3120
3121 hp->happy_bursts = DMA_BURSTBITS;
3122#endif
3123
3124 hp->happy_block = (struct hmeal_init_block *)
3125 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3126
3127 err = -ENODEV;
3128 if (!hp->happy_block) {
3129 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3130 goto err_out_iounmap;
3131 }
3132
3133 hp->linkcheck = 0;
3134 hp->timer_state = asleep;
3135 hp->timer_ticks = 0;
3136
3137 init_timer(&hp->happy_timer);
3138
3139 hp->dev = dev;
3140 dev->open = &happy_meal_open;
3141 dev->stop = &happy_meal_close;
3142 dev->hard_start_xmit = &happy_meal_start_xmit;
3143 dev->get_stats = &happy_meal_get_stats;
3144 dev->set_multicast_list = &happy_meal_set_multicast;
3145 dev->tx_timeout = &happy_meal_tx_timeout;
3146 dev->watchdog_timeo = 5*HZ;
3147 dev->ethtool_ops = &hme_ethtool_ops;
3148 dev->irq = pdev->irq;
3149 dev->dma = 0;
3150
3151
3152 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3153
3154#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3155
3156 hp->read_desc32 = pci_hme_read_desc32;
3157 hp->write_txd = pci_hme_write_txd;
3158 hp->write_rxd = pci_hme_write_rxd;
3159 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3160 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3161 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3162 pci_dma_sync_single_for_cpu;
3163 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3164 pci_dma_sync_single_for_device;
3165 hp->read32 = pci_hme_read32;
3166 hp->write32 = pci_hme_write32;
3167#endif
3168
3169
3170
3171
3172 spin_lock_irq(&hp->happy_lock);
3173 happy_meal_set_initial_advertisement(hp);
3174 spin_unlock_irq(&hp->happy_lock);
3175
3176 if (register_netdev(hp->dev)) {
3177 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3178 "aborting.\n");
3179 goto err_out_iounmap;
3180 }
3181
3182 dev_set_drvdata(&pdev->dev, hp);
3183
3184 if (!qfe_slot) {
3185 struct pci_dev *qpdev = qp->quattro_dev;
3186
3187 prom_name[0] = 0;
3188 if (!strncmp(dev->name, "eth", 3)) {
3189 int i = simple_strtoul(dev->name + 3, NULL, 10);
3190 sprintf(prom_name, "-%d", i + 3);
3191 }
3192 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3193 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3194 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3195 printk("DEC 21153 PCI Bridge\n");
3196 else
3197 printk("unknown bridge %04x.%04x\n",
3198 qpdev->vendor, qpdev->device);
3199 }
3200
3201 if (qfe_slot != -1)
3202 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3203 dev->name, qfe_slot);
3204 else
3205 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3206 dev->name);
3207
3208 printk("%s\n", print_mac(mac, dev->dev_addr));
3209
3210 return 0;
3211
3212err_out_iounmap:
3213 iounmap(hp->gregs);
3214
3215err_out_free_res:
3216 pci_release_regions(pdev);
3217
3218err_out_clear_quattro:
3219 if (qp != NULL)
3220 qp->happy_meals[qfe_slot] = NULL;
3221
3222 free_netdev(dev);
3223
3224err_out:
3225 return err;
3226}
3227
3228static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3229{
3230 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3231 struct net_device *net_dev = hp->dev;
3232
3233 unregister_netdev(net_dev);
3234
3235 pci_free_consistent(hp->happy_dev,
3236 PAGE_SIZE,
3237 hp->happy_block,
3238 hp->hblock_dvma);
3239 iounmap(hp->gregs);
3240 pci_release_regions(hp->happy_dev);
3241
3242 free_netdev(net_dev);
3243
3244 dev_set_drvdata(&pdev->dev, NULL);
3245}
3246
3247static struct pci_device_id happymeal_pci_ids[] = {
3248 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3249 { }
3250};
3251
3252MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3253
3254static struct pci_driver hme_pci_driver = {
3255 .name = "hme",
3256 .id_table = happymeal_pci_ids,
3257 .probe = happy_meal_pci_probe,
3258 .remove = __devexit_p(happy_meal_pci_remove),
3259};
3260
3261static int __init happy_meal_pci_init(void)
3262{
3263 return pci_register_driver(&hme_pci_driver);
3264}
3265
3266static void happy_meal_pci_exit(void)
3267{
3268 pci_unregister_driver(&hme_pci_driver);
3269
3270 while (qfe_pci_list) {
3271 struct quattro *qfe = qfe_pci_list;
3272 struct quattro *next = qfe->next;
3273
3274 kfree(qfe);
3275
3276 qfe_pci_list = next;
3277 }
3278}
3279
3280#endif
3281
3282#ifdef CONFIG_SBUS
3283static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
3284{
3285 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
3286 struct device_node *dp = dev->node;
3287 const char *model = of_get_property(dp, "model", NULL);
3288 int is_qfe = (match->data != NULL);
3289
3290 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3291 is_qfe = 1;
3292
3293 return happy_meal_sbus_probe_one(sdev, is_qfe);
3294}
3295
3296static int __devexit hme_sbus_remove(struct of_device *dev)
3297{
3298 struct happy_meal *hp = dev_get_drvdata(&dev->dev);
3299 struct net_device *net_dev = hp->dev;
3300
3301 unregister_netdev(net_dev);
3302
3303
3304
3305 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3306 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3307 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3308 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3309 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3310 sbus_free_consistent(hp->happy_dev,
3311 PAGE_SIZE,
3312 hp->happy_block,
3313 hp->hblock_dvma);
3314
3315 free_netdev(net_dev);
3316
3317 dev_set_drvdata(&dev->dev, NULL);
3318
3319 return 0;
3320}
3321
3322static struct of_device_id hme_sbus_match[] = {
3323 {
3324 .name = "SUNW,hme",
3325 },
3326 {
3327 .name = "SUNW,qfe",
3328 .data = (void *) 1,
3329 },
3330 {
3331 .name = "qfe",
3332 .data = (void *) 1,
3333 },
3334 {},
3335};
3336
3337MODULE_DEVICE_TABLE(of, hme_sbus_match);
3338
3339static struct of_platform_driver hme_sbus_driver = {
3340 .name = "hme",
3341 .match_table = hme_sbus_match,
3342 .probe = hme_sbus_probe,
3343 .remove = __devexit_p(hme_sbus_remove),
3344};
3345
3346static int __init happy_meal_sbus_init(void)
3347{
3348 int err;
3349
3350 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
3351 if (!err)
3352 quattro_sbus_register_irqs();
3353
3354 return err;
3355}
3356
3357static void happy_meal_sbus_exit(void)
3358{
3359 of_unregister_driver(&hme_sbus_driver);
3360 quattro_sbus_free_irqs();
3361
3362 while (qfe_sbus_list) {
3363 struct quattro *qfe = qfe_sbus_list;
3364 struct quattro *next = qfe->next;
3365
3366 kfree(qfe);
3367
3368 qfe_sbus_list = next;
3369 }
3370}
3371#endif
3372
3373static int __init happy_meal_probe(void)
3374{
3375 int err = 0;
3376
3377#ifdef CONFIG_SBUS
3378 err = happy_meal_sbus_init();
3379#endif
3380#ifdef CONFIG_PCI
3381 if (!err) {
3382 err = happy_meal_pci_init();
3383#ifdef CONFIG_SBUS
3384 if (err)
3385 happy_meal_sbus_exit();
3386#endif
3387 }
3388#endif
3389
3390 return err;
3391}
3392
3393
3394static void __exit happy_meal_exit(void)
3395{
3396#ifdef CONFIG_SBUS
3397 happy_meal_sbus_exit();
3398#endif
3399#ifdef CONFIG_PCI
3400 happy_meal_pci_exit();
3401#endif
3402}
3403
3404module_init(happy_meal_probe);
3405module_exit(happy_meal_exit);
3406