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169#include <linux/module.h>
170#include <linux/init.h>
171#include <linux/ioport.h>
172#include <linux/eisa.h>
173#include <linux/pci.h>
174#include <linux/dma-mapping.h>
175#include <linux/netdevice.h>
176#include <linux/etherdevice.h>
177#include <linux/delay.h>
178#include <linux/spinlock.h>
179#include <linux/workqueue.h>
180#include <linux/mii.h>
181
182#include "tlan.h"
183
184typedef u32 (TLanIntVectorFunc)( struct net_device *, u16 );
185
186
187
188static struct net_device *TLan_Eisa_Devices;
189
190static int TLanDevicesInstalled;
191
192
193static int aui[MAX_TLAN_BOARDS];
194static int duplex[MAX_TLAN_BOARDS];
195static int speed[MAX_TLAN_BOARDS];
196static int boards_found;
197module_param_array(aui, int, NULL, 0);
198module_param_array(duplex, int, NULL, 0);
199module_param_array(speed, int, NULL, 0);
200MODULE_PARM_DESC(aui, "ThunderLAN use AUI port(s) (0-1)");
201MODULE_PARM_DESC(duplex, "ThunderLAN duplex setting(s) (0-default, 1-half, 2-full)");
202MODULE_PARM_DESC(speed, "ThunderLAN port speen setting(s) (0,10,100)");
203
204MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>");
205MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters");
206MODULE_LICENSE("GPL");
207
208
209
210#undef MONITOR
211
212
213static int debug;
214module_param(debug, int, 0);
215MODULE_PARM_DESC(debug, "ThunderLAN debug mask");
216
217static int bbuf;
218module_param(bbuf, int, 0);
219MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)");
220
221static u8 *TLanPadBuffer;
222static dma_addr_t TLanPadBufferDMA;
223static char TLanSignature[] = "TLAN";
224static const char tlan_banner[] = "ThunderLAN driver v1.15\n";
225static int tlan_have_pci;
226static int tlan_have_eisa;
227
228static const char *media[] = {
229 "10BaseT-HD ", "10BaseT-FD ","100baseTx-HD ",
230 "100baseTx-FD", "100baseT4", NULL
231};
232
233static struct board {
234 const char *deviceLabel;
235 u32 flags;
236 u16 addrOfs;
237} board_info[] = {
238 { "Compaq Netelligent 10 T PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
239 { "Compaq Netelligent 10/100 TX PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
240 { "Compaq Integrated NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
241 { "Compaq NetFlex-3/P", TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
242 { "Compaq NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
243 { "Compaq Netelligent Integrated 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
244 { "Compaq Netelligent Dual 10/100 TX PCI UTP", TLAN_ADAPTER_NONE, 0x83 },
245 { "Compaq Netelligent 10/100 TX Embedded UTP", TLAN_ADAPTER_NONE, 0x83 },
246 { "Olicom OC-2183/2185", TLAN_ADAPTER_USE_INTERN_10, 0x83 },
247 { "Olicom OC-2325", TLAN_ADAPTER_UNMANAGED_PHY, 0xF8 },
248 { "Olicom OC-2326", TLAN_ADAPTER_USE_INTERN_10, 0xF8 },
249 { "Compaq Netelligent 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
250 { "Compaq Netelligent 10 T/2 PCI UTP/Coax", TLAN_ADAPTER_NONE, 0x83 },
251 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED |
252 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
253 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
254};
255
256static struct pci_device_id tlan_pci_tbl[] = {
257 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL10,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
259 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
261 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3I,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
263 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_THUNDER,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
265 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3B,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
267 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100PI,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
269 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100D,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
271 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100I,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
273 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2183,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
275 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2325,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
277 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2326,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
279 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
281 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_T2,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
283 { 0,}
284};
285MODULE_DEVICE_TABLE(pci, tlan_pci_tbl);
286
287static void TLan_EisaProbe( void );
288static void TLan_Eisa_Cleanup( void );
289static int TLan_Init( struct net_device * );
290static int TLan_Open( struct net_device *dev );
291static int TLan_StartTx( struct sk_buff *, struct net_device *);
292static irqreturn_t TLan_HandleInterrupt( int, void *);
293static int TLan_Close( struct net_device *);
294static struct net_device_stats *TLan_GetStats( struct net_device *);
295static void TLan_SetMulticastList( struct net_device *);
296static int TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd);
297static int TLan_probe1( struct pci_dev *pdev, long ioaddr, int irq, int rev, const struct pci_device_id *ent);
298static void TLan_tx_timeout( struct net_device *dev);
299static void TLan_tx_timeout_work(struct work_struct *work);
300static int tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent);
301
302static u32 TLan_HandleInvalid( struct net_device *, u16 );
303static u32 TLan_HandleTxEOF( struct net_device *, u16 );
304static u32 TLan_HandleStatOverflow( struct net_device *, u16 );
305static u32 TLan_HandleRxEOF( struct net_device *, u16 );
306static u32 TLan_HandleDummy( struct net_device *, u16 );
307static u32 TLan_HandleTxEOC( struct net_device *, u16 );
308static u32 TLan_HandleStatusCheck( struct net_device *, u16 );
309static u32 TLan_HandleRxEOC( struct net_device *, u16 );
310
311static void TLan_Timer( unsigned long );
312
313static void TLan_ResetLists( struct net_device * );
314static void TLan_FreeLists( struct net_device * );
315static void TLan_PrintDio( u16 );
316static void TLan_PrintList( TLanList *, char *, int );
317static void TLan_ReadAndClearStats( struct net_device *, int );
318static void TLan_ResetAdapter( struct net_device * );
319static void TLan_FinishReset( struct net_device * );
320static void TLan_SetMac( struct net_device *, int areg, char *mac );
321
322static void TLan_PhyPrint( struct net_device * );
323static void TLan_PhyDetect( struct net_device * );
324static void TLan_PhyPowerDown( struct net_device * );
325static void TLan_PhyPowerUp( struct net_device * );
326static void TLan_PhyReset( struct net_device * );
327static void TLan_PhyStartLink( struct net_device * );
328static void TLan_PhyFinishAutoNeg( struct net_device * );
329#ifdef MONITOR
330static void TLan_PhyMonitor( struct net_device * );
331#endif
332
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339
340static int TLan_MiiReadReg( struct net_device *, u16, u16, u16 * );
341static void TLan_MiiSendData( u16, u32, unsigned );
342static void TLan_MiiSync( u16 );
343static void TLan_MiiWriteReg( struct net_device *, u16, u16, u16 );
344
345static void TLan_EeSendStart( u16 );
346static int TLan_EeSendByte( u16, u8, int );
347static void TLan_EeReceiveByte( u16, u8 *, int );
348static int TLan_EeReadByte( struct net_device *, u8, u8 * );
349
350
351static void
352TLan_StoreSKB( struct tlan_list_tag *tag, struct sk_buff *skb)
353{
354 unsigned long addr = (unsigned long)skb;
355 tag->buffer[9].address = (u32)addr;
356 addr >>= 31;
357 addr >>= 1;
358 tag->buffer[8].address = (u32)addr;
359}
360
361static struct sk_buff *
362TLan_GetSKB( struct tlan_list_tag *tag)
363{
364 unsigned long addr = tag->buffer[8].address;
365 addr <<= 31;
366 addr <<= 1;
367 addr |= tag->buffer[9].address;
368 return (struct sk_buff *) addr;
369}
370
371
372static TLanIntVectorFunc *TLanIntVector[TLAN_INT_NUMBER_OF_INTS] = {
373 TLan_HandleInvalid,
374 TLan_HandleTxEOF,
375 TLan_HandleStatOverflow,
376 TLan_HandleRxEOF,
377 TLan_HandleDummy,
378 TLan_HandleTxEOC,
379 TLan_HandleStatusCheck,
380 TLan_HandleRxEOC
381};
382
383static inline void
384TLan_SetTimer( struct net_device *dev, u32 ticks, u32 type )
385{
386 TLanPrivateInfo *priv = netdev_priv(dev);
387 unsigned long flags = 0;
388
389 if (!in_irq())
390 spin_lock_irqsave(&priv->lock, flags);
391 if ( priv->timer.function != NULL &&
392 priv->timerType != TLAN_TIMER_ACTIVITY ) {
393 if (!in_irq())
394 spin_unlock_irqrestore(&priv->lock, flags);
395 return;
396 }
397 priv->timer.function = &TLan_Timer;
398 if (!in_irq())
399 spin_unlock_irqrestore(&priv->lock, flags);
400
401 priv->timer.data = (unsigned long) dev;
402 priv->timerSetAt = jiffies;
403 priv->timerType = type;
404 mod_timer(&priv->timer, jiffies + ticks);
405
406}
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439static void __devexit tlan_remove_one( struct pci_dev *pdev)
440{
441 struct net_device *dev = pci_get_drvdata( pdev );
442 TLanPrivateInfo *priv = netdev_priv(dev);
443
444 unregister_netdev( dev );
445
446 if ( priv->dmaStorage ) {
447 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA );
448 }
449
450#ifdef CONFIG_PCI
451 pci_release_regions(pdev);
452#endif
453
454 free_netdev( dev );
455
456 pci_set_drvdata( pdev, NULL );
457}
458
459static struct pci_driver tlan_driver = {
460 .name = "tlan",
461 .id_table = tlan_pci_tbl,
462 .probe = tlan_init_one,
463 .remove = __devexit_p(tlan_remove_one),
464};
465
466static int __init tlan_probe(void)
467{
468 static int pad_allocated;
469
470 printk(KERN_INFO "%s", tlan_banner);
471
472 TLanPadBuffer = (u8 *) pci_alloc_consistent(NULL, TLAN_MIN_FRAME_SIZE, &TLanPadBufferDMA);
473
474 if (TLanPadBuffer == NULL) {
475 printk(KERN_ERR "TLAN: Could not allocate memory for pad buffer.\n");
476 return -ENOMEM;
477 }
478
479 memset(TLanPadBuffer, 0, TLAN_MIN_FRAME_SIZE);
480 pad_allocated = 1;
481
482 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting PCI Probe....\n");
483
484
485
486 pci_register_driver(&tlan_driver);
487
488 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting EISA Probe....\n");
489 TLan_EisaProbe();
490
491 printk(KERN_INFO "TLAN: %d device%s installed, PCI: %d EISA: %d\n",
492 TLanDevicesInstalled, TLanDevicesInstalled == 1 ? "" : "s",
493 tlan_have_pci, tlan_have_eisa);
494
495 if (TLanDevicesInstalled == 0) {
496 pci_unregister_driver(&tlan_driver);
497 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
498 return -ENODEV;
499 }
500 return 0;
501}
502
503
504static int __devinit tlan_init_one( struct pci_dev *pdev,
505 const struct pci_device_id *ent)
506{
507 return TLan_probe1( pdev, -1, -1, 0, ent);
508}
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530static int __devinit TLan_probe1(struct pci_dev *pdev,
531 long ioaddr, int irq, int rev, const struct pci_device_id *ent )
532{
533
534 struct net_device *dev;
535 TLanPrivateInfo *priv;
536 u16 device_id;
537 int reg, rc = -ENODEV;
538
539#ifdef CONFIG_PCI
540 if (pdev) {
541 rc = pci_enable_device(pdev);
542 if (rc)
543 return rc;
544
545 rc = pci_request_regions(pdev, TLanSignature);
546 if (rc) {
547 printk(KERN_ERR "TLAN: Could not reserve IO regions\n");
548 goto err_out;
549 }
550 }
551#endif
552
553 dev = alloc_etherdev(sizeof(TLanPrivateInfo));
554 if (dev == NULL) {
555 printk(KERN_ERR "TLAN: Could not allocate memory for device.\n");
556 rc = -ENOMEM;
557 goto err_out_regions;
558 }
559 SET_NETDEV_DEV(dev, &pdev->dev);
560
561 priv = netdev_priv(dev);
562
563 priv->pciDev = pdev;
564 priv->dev = dev;
565
566
567 if (pdev) {
568 u32 pci_io_base = 0;
569
570 priv->adapter = &board_info[ent->driver_data];
571
572 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
573 if (rc) {
574 printk(KERN_ERR "TLAN: No suitable PCI mapping available.\n");
575 goto err_out_free_dev;
576 }
577
578 for ( reg= 0; reg <= 5; reg ++ ) {
579 if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) {
580 pci_io_base = pci_resource_start(pdev, reg);
581 TLAN_DBG( TLAN_DEBUG_GNRL, "IO mapping is available at %x.\n",
582 pci_io_base);
583 break;
584 }
585 }
586 if (!pci_io_base) {
587 printk(KERN_ERR "TLAN: No IO mappings available\n");
588 rc = -EIO;
589 goto err_out_free_dev;
590 }
591
592 dev->base_addr = pci_io_base;
593 dev->irq = pdev->irq;
594 priv->adapterRev = pdev->revision;
595 pci_set_master(pdev);
596 pci_set_drvdata(pdev, dev);
597
598 } else {
599
600
601 device_id = inw(ioaddr + EISA_ID2);
602 priv->is_eisa = 1;
603 if (device_id == 0x20F1) {
604 priv->adapter = &board_info[13];
605 priv->adapterRev = 23;
606 } else {
607 priv->adapter = &board_info[14];
608 priv->adapterRev = 10;
609 }
610 dev->base_addr = ioaddr;
611 dev->irq = irq;
612 }
613
614
615 if (dev->mem_start) {
616 priv->aui = dev->mem_start & 0x01;
617 priv->duplex = ((dev->mem_start & 0x06) == 0x06) ? 0 : (dev->mem_start & 0x06) >> 1;
618 priv->speed = ((dev->mem_start & 0x18) == 0x18) ? 0 : (dev->mem_start & 0x18) >> 3;
619
620 if (priv->speed == 0x1) {
621 priv->speed = TLAN_SPEED_10;
622 } else if (priv->speed == 0x2) {
623 priv->speed = TLAN_SPEED_100;
624 }
625 debug = priv->debug = dev->mem_end;
626 } else {
627 priv->aui = aui[boards_found];
628 priv->speed = speed[boards_found];
629 priv->duplex = duplex[boards_found];
630 priv->debug = debug;
631 }
632
633
634
635 INIT_WORK(&priv->tlan_tqueue, TLan_tx_timeout_work);
636
637 spin_lock_init(&priv->lock);
638
639 rc = TLan_Init(dev);
640 if (rc) {
641 printk(KERN_ERR "TLAN: Could not set up device.\n");
642 goto err_out_free_dev;
643 }
644
645 rc = register_netdev(dev);
646 if (rc) {
647 printk(KERN_ERR "TLAN: Could not register device.\n");
648 goto err_out_uninit;
649 }
650
651
652 TLanDevicesInstalled++;
653 boards_found++;
654
655
656 if (pdev)
657 tlan_have_pci++;
658 else {
659 priv->nextDevice = TLan_Eisa_Devices;
660 TLan_Eisa_Devices = dev;
661 tlan_have_eisa++;
662 }
663
664 printk(KERN_INFO "TLAN: %s irq=%2d, io=%04x, %s, Rev. %d\n",
665 dev->name,
666 (int) dev->irq,
667 (int) dev->base_addr,
668 priv->adapter->deviceLabel,
669 priv->adapterRev);
670 return 0;
671
672err_out_uninit:
673 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage,
674 priv->dmaStorageDMA );
675err_out_free_dev:
676 free_netdev(dev);
677err_out_regions:
678#ifdef CONFIG_PCI
679 if (pdev)
680 pci_release_regions(pdev);
681#endif
682err_out:
683 if (pdev)
684 pci_disable_device(pdev);
685 return rc;
686}
687
688
689static void TLan_Eisa_Cleanup(void)
690{
691 struct net_device *dev;
692 TLanPrivateInfo *priv;
693
694 while( tlan_have_eisa ) {
695 dev = TLan_Eisa_Devices;
696 priv = netdev_priv(dev);
697 if (priv->dmaStorage) {
698 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA );
699 }
700 release_region( dev->base_addr, 0x10);
701 unregister_netdev( dev );
702 TLan_Eisa_Devices = priv->nextDevice;
703 free_netdev( dev );
704 tlan_have_eisa--;
705 }
706}
707
708
709static void __exit tlan_exit(void)
710{
711 pci_unregister_driver(&tlan_driver);
712
713 if (tlan_have_eisa)
714 TLan_Eisa_Cleanup();
715
716 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
717
718}
719
720
721
722module_init(tlan_probe);
723module_exit(tlan_exit);
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740static void __init TLan_EisaProbe (void)
741{
742 long ioaddr;
743 int rc = -ENODEV;
744 int irq;
745 u16 device_id;
746
747 if (!EISA_bus) {
748 TLAN_DBG(TLAN_DEBUG_PROBE, "No EISA bus present\n");
749 return;
750 }
751
752
753 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
754
755 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID));
756 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2));
757
758
759 TLAN_DBG(TLAN_DEBUG_PROBE, "Probing for EISA adapter at IO: 0x%4x : ",
760 (int) ioaddr);
761 if (request_region(ioaddr, 0x10, TLanSignature) == NULL)
762 goto out;
763
764 if (inw(ioaddr + EISA_ID) != 0x110E) {
765 release_region(ioaddr, 0x10);
766 goto out;
767 }
768
769 device_id = inw(ioaddr + EISA_ID2);
770 if (device_id != 0x20F1 && device_id != 0x40F1) {
771 release_region (ioaddr, 0x10);
772 goto out;
773 }
774
775 if (inb(ioaddr + EISA_CR) != 0x1) {
776 release_region (ioaddr, 0x10);
777 goto out2;
778 }
779
780 if (debug == 0x10)
781 printk("Found one\n");
782
783
784
785 switch (inb(ioaddr + 0xCC0)) {
786 case(0x10):
787 irq=5;
788 break;
789 case(0x20):
790 irq=9;
791 break;
792 case(0x40):
793 irq=10;
794 break;
795 case(0x80):
796 irq=11;
797 break;
798 default:
799 goto out;
800 }
801
802
803
804 rc = TLan_probe1( NULL, ioaddr, irq,
805 12, NULL);
806 continue;
807
808 out:
809 if (debug == 0x10)
810 printk("None found\n");
811 continue;
812
813 out2: if (debug == 0x10)
814 printk("Card found but it is not enabled, skipping\n");
815 continue;
816
817 }
818
819}
820
821#ifdef CONFIG_NET_POLL_CONTROLLER
822static void TLan_Poll(struct net_device *dev)
823{
824 disable_irq(dev->irq);
825 TLan_HandleInterrupt(dev->irq, dev);
826 enable_irq(dev->irq);
827}
828#endif
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850static int TLan_Init( struct net_device *dev )
851{
852 int dma_size;
853 int err;
854 int i;
855 TLanPrivateInfo *priv;
856
857 priv = netdev_priv(dev);
858
859 if ( bbuf ) {
860 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
861 * ( sizeof(TLanList) + TLAN_MAX_FRAME_SIZE );
862 } else {
863 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
864 * ( sizeof(TLanList) );
865 }
866 priv->dmaStorage = pci_alloc_consistent(priv->pciDev, dma_size, &priv->dmaStorageDMA);
867 priv->dmaSize = dma_size;
868
869 if ( priv->dmaStorage == NULL ) {
870 printk(KERN_ERR "TLAN: Could not allocate lists and buffers for %s.\n",
871 dev->name );
872 return -ENOMEM;
873 }
874 memset( priv->dmaStorage, 0, dma_size );
875 priv->rxList = (TLanList *)
876 ( ( ( (u32) priv->dmaStorage ) + 7 ) & 0xFFFFFFF8 );
877 priv->rxListDMA = ( ( ( (u32) priv->dmaStorageDMA ) + 7 ) & 0xFFFFFFF8 );
878 priv->txList = priv->rxList + TLAN_NUM_RX_LISTS;
879 priv->txListDMA = priv->rxListDMA + sizeof(TLanList) * TLAN_NUM_RX_LISTS;
880 if ( bbuf ) {
881 priv->rxBuffer = (u8 *) ( priv->txList + TLAN_NUM_TX_LISTS );
882 priv->rxBufferDMA =priv->txListDMA + sizeof(TLanList) * TLAN_NUM_TX_LISTS;
883 priv->txBuffer = priv->rxBuffer + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
884 priv->txBufferDMA = priv->rxBufferDMA + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
885 }
886
887 err = 0;
888 for ( i = 0; i < 6 ; i++ )
889 err |= TLan_EeReadByte( dev,
890 (u8) priv->adapter->addrOfs + i,
891 (u8 *) &dev->dev_addr[i] );
892 if ( err ) {
893 printk(KERN_ERR "TLAN: %s: Error reading MAC from eeprom: %d\n",
894 dev->name,
895 err );
896 }
897 dev->addr_len = 6;
898
899 netif_carrier_off(dev);
900
901
902 dev->open = &TLan_Open;
903 dev->hard_start_xmit = &TLan_StartTx;
904 dev->stop = &TLan_Close;
905 dev->get_stats = &TLan_GetStats;
906 dev->set_multicast_list = &TLan_SetMulticastList;
907 dev->do_ioctl = &TLan_ioctl;
908#ifdef CONFIG_NET_POLL_CONTROLLER
909 dev->poll_controller = &TLan_Poll;
910#endif
911 dev->tx_timeout = &TLan_tx_timeout;
912 dev->watchdog_timeo = TX_TIMEOUT;
913
914 return 0;
915
916}
917
918
919
920
921
922
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936
937
938static int TLan_Open( struct net_device *dev )
939{
940 TLanPrivateInfo *priv = netdev_priv(dev);
941 int err;
942
943 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION );
944 err = request_irq( dev->irq, TLan_HandleInterrupt, IRQF_SHARED, TLanSignature, dev );
945
946 if ( err ) {
947 printk(KERN_ERR "TLAN: Cannot open %s because IRQ %d is already in use.\n", dev->name, dev->irq );
948 return err;
949 }
950
951 init_timer(&priv->timer);
952 netif_start_queue(dev);
953
954
955
956
957 TLan_ResetLists( dev );
958 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
959 TLan_ResetAdapter( dev );
960
961 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Opened. TLAN Chip Rev: %x\n", dev->name, priv->tlanRev );
962
963 return 0;
964
965}
966
967
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970
971
972
973
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975
976
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978
979
980
981
982
983
984static int TLan_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
985{
986 TLanPrivateInfo *priv = netdev_priv(dev);
987 struct mii_ioctl_data *data = if_mii(rq);
988 u32 phy = priv->phy[priv->phyNum];
989
990 if (!priv->phyOnline)
991 return -EAGAIN;
992
993 switch(cmd) {
994 case SIOCGMIIPHY:
995 data->phy_id = phy;
996
997
998 case SIOCGMIIREG:
999 TLan_MiiReadReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, &data->val_out);
1000 return 0;
1001
1002
1003 case SIOCSMIIREG:
1004 if (!capable(CAP_NET_ADMIN))
1005 return -EPERM;
1006 TLan_MiiWriteReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1007 return 0;
1008 default:
1009 return -EOPNOTSUPP;
1010 }
1011}
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025static void TLan_tx_timeout(struct net_device *dev)
1026{
1027
1028 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Transmit timed out.\n", dev->name);
1029
1030
1031 TLan_FreeLists( dev );
1032 TLan_ResetLists( dev );
1033 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
1034 TLan_ResetAdapter( dev );
1035 dev->trans_start = jiffies;
1036 netif_wake_queue( dev );
1037
1038}
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051static void TLan_tx_timeout_work(struct work_struct *work)
1052{
1053 TLanPrivateInfo *priv =
1054 container_of(work, TLanPrivateInfo, tlan_tqueue);
1055
1056 TLan_tx_timeout(priv->dev);
1057}
1058
1059
1060
1061
1062
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1080
1081
1082static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1083{
1084 TLanPrivateInfo *priv = netdev_priv(dev);
1085 TLanList *tail_list;
1086 dma_addr_t tail_list_phys;
1087 u8 *tail_buffer;
1088 int pad;
1089 unsigned long flags;
1090
1091 if ( ! priv->phyOnline ) {
1092 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n", dev->name );
1093 dev_kfree_skb_any(skb);
1094 return 0;
1095 }
1096
1097 tail_list = priv->txList + priv->txTail;
1098 tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail;
1099
1100 if ( tail_list->cStat != TLAN_CSTAT_UNUSED ) {
1101 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s is busy (Head=%d Tail=%d)\n", dev->name, priv->txHead, priv->txTail );
1102 netif_stop_queue(dev);
1103 priv->txBusyCount++;
1104 return 1;
1105 }
1106
1107 tail_list->forward = 0;
1108
1109 if ( bbuf ) {
1110 tail_buffer = priv->txBuffer + ( priv->txTail * TLAN_MAX_FRAME_SIZE );
1111 skb_copy_from_linear_data(skb, tail_buffer, skb->len);
1112 } else {
1113 tail_list->buffer[0].address = pci_map_single(priv->pciDev, skb->data, skb->len, PCI_DMA_TODEVICE);
1114 TLan_StoreSKB(tail_list, skb);
1115 }
1116
1117 pad = TLAN_MIN_FRAME_SIZE - skb->len;
1118
1119 if ( pad > 0 ) {
1120 tail_list->frameSize = (u16) skb->len + pad;
1121 tail_list->buffer[0].count = (u32) skb->len;
1122 tail_list->buffer[1].count = TLAN_LAST_BUFFER | (u32) pad;
1123 tail_list->buffer[1].address = TLanPadBufferDMA;
1124 } else {
1125 tail_list->frameSize = (u16) skb->len;
1126 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) skb->len;
1127 tail_list->buffer[1].count = 0;
1128 tail_list->buffer[1].address = 0;
1129 }
1130
1131 spin_lock_irqsave(&priv->lock, flags);
1132 tail_list->cStat = TLAN_CSTAT_READY;
1133 if ( ! priv->txInProgress ) {
1134 priv->txInProgress = 1;
1135 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Starting TX on buffer %d\n", priv->txTail );
1136 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM );
1137 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD );
1138 } else {
1139 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Adding buffer %d to TX channel\n", priv->txTail );
1140 if ( priv->txTail == 0 ) {
1141 ( priv->txList + ( TLAN_NUM_TX_LISTS - 1 ) )->forward = tail_list_phys;
1142 } else {
1143 ( priv->txList + ( priv->txTail - 1 ) )->forward = tail_list_phys;
1144 }
1145 }
1146 spin_unlock_irqrestore(&priv->lock, flags);
1147
1148 CIRC_INC( priv->txTail, TLAN_NUM_TX_LISTS );
1149
1150 if ( bbuf )
1151 dev_kfree_skb_any(skb);
1152
1153 dev->trans_start = jiffies;
1154 return 0;
1155
1156}
1157
1158
1159
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1177
1178
1179
1180
1181static irqreturn_t TLan_HandleInterrupt(int irq, void *dev_id)
1182{
1183 u32 ack;
1184 struct net_device *dev;
1185 u32 host_cmd;
1186 u16 host_int;
1187 int type;
1188 TLanPrivateInfo *priv;
1189
1190 dev = dev_id;
1191 priv = netdev_priv(dev);
1192
1193 spin_lock(&priv->lock);
1194
1195 host_int = inw( dev->base_addr + TLAN_HOST_INT );
1196 outw( host_int, dev->base_addr + TLAN_HOST_INT );
1197
1198 type = ( host_int & TLAN_HI_IT_MASK ) >> 2;
1199
1200 ack = TLanIntVector[type]( dev, host_int );
1201
1202 if ( ack ) {
1203 host_cmd = TLAN_HC_ACK | ack | ( type << 18 );
1204 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD );
1205 }
1206
1207 spin_unlock(&priv->lock);
1208
1209 return IRQ_HANDLED;
1210}
1211
1212
1213
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1217
1218
1219
1220
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1226
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1228
1229
1230static int TLan_Close(struct net_device *dev)
1231{
1232 TLanPrivateInfo *priv = netdev_priv(dev);
1233
1234 netif_stop_queue(dev);
1235 priv->neg_be_verbose = 0;
1236
1237 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1238 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1239 if ( priv->timer.function != NULL ) {
1240 del_timer_sync( &priv->timer );
1241 priv->timer.function = NULL;
1242 }
1243
1244 free_irq( dev->irq, dev );
1245 TLan_FreeLists( dev );
1246 TLAN_DBG( TLAN_DEBUG_GNRL, "Device %s closed.\n", dev->name );
1247
1248 return 0;
1249
1250}
1251
1252
1253
1254
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1264
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1268
1269
1270static struct net_device_stats *TLan_GetStats( struct net_device *dev )
1271{
1272 TLanPrivateInfo *priv = netdev_priv(dev);
1273 int i;
1274
1275
1276 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1277
1278 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: %s EOC count = %d\n", dev->name, priv->rxEocCount );
1279 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s Busy count = %d\n", dev->name, priv->txBusyCount );
1280 if ( debug & TLAN_DEBUG_GNRL ) {
1281 TLan_PrintDio( dev->base_addr );
1282 TLan_PhyPrint( dev );
1283 }
1284 if ( debug & TLAN_DEBUG_LIST ) {
1285 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ )
1286 TLan_PrintList( priv->rxList + i, "RX", i );
1287 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ )
1288 TLan_PrintList( priv->txList + i, "TX", i );
1289 }
1290
1291 return ( &( (TLanPrivateInfo *) netdev_priv(dev) )->stats );
1292
1293}
1294
1295
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1316
1317
1318static void TLan_SetMulticastList( struct net_device *dev )
1319{
1320 struct dev_mc_list *dmi = dev->mc_list;
1321 u32 hash1 = 0;
1322 u32 hash2 = 0;
1323 int i;
1324 u32 offset;
1325 u8 tmp;
1326
1327 if ( dev->flags & IFF_PROMISC ) {
1328 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1329 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF );
1330 } else {
1331 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1332 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF );
1333 if ( dev->flags & IFF_ALLMULTI ) {
1334 for ( i = 0; i < 3; i++ )
1335 TLan_SetMac( dev, i + 1, NULL );
1336 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, 0xFFFFFFFF );
1337 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, 0xFFFFFFFF );
1338 } else {
1339 for ( i = 0; i < dev->mc_count; i++ ) {
1340 if ( i < 3 ) {
1341 TLan_SetMac( dev, i + 1, (char *) &dmi->dmi_addr );
1342 } else {
1343 offset = TLan_HashFunc( (u8 *) &dmi->dmi_addr );
1344 if ( offset < 32 )
1345 hash1 |= ( 1 << offset );
1346 else
1347 hash2 |= ( 1 << ( offset - 32 ) );
1348 }
1349 dmi = dmi->next;
1350 }
1351 for ( ; i < 3; i++ )
1352 TLan_SetMac( dev, i + 1, NULL );
1353 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, hash1 );
1354 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, hash2 );
1355 }
1356 }
1357
1358}
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
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1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int )
1393{
1394
1395 return 0;
1396
1397}
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
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1422
1423
1424u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1425{
1426 TLanPrivateInfo *priv = netdev_priv(dev);
1427 int eoc = 0;
1428 TLanList *head_list;
1429 dma_addr_t head_list_phys;
1430 u32 ack = 0;
1431 u16 tmpCStat;
1432
1433 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOF (Head=%d Tail=%d)\n", priv->txHead, priv->txTail );
1434 head_list = priv->txList + priv->txHead;
1435
1436 while (((tmpCStat = head_list->cStat ) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1437 ack++;
1438 if ( ! bbuf ) {
1439 struct sk_buff *skb = TLan_GetSKB(head_list);
1440 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, skb->len, PCI_DMA_TODEVICE);
1441 dev_kfree_skb_any(skb);
1442 head_list->buffer[8].address = 0;
1443 head_list->buffer[9].address = 0;
1444 }
1445
1446 if ( tmpCStat & TLAN_CSTAT_EOC )
1447 eoc = 1;
1448
1449 priv->stats.tx_bytes += head_list->frameSize;
1450
1451 head_list->cStat = TLAN_CSTAT_UNUSED;
1452 netif_start_queue(dev);
1453 CIRC_INC( priv->txHead, TLAN_NUM_TX_LISTS );
1454 head_list = priv->txList + priv->txHead;
1455 }
1456
1457 if (!ack)
1458 printk(KERN_INFO "TLAN: Received interrupt for uncompleted TX frame.\n");
1459
1460 if ( eoc ) {
1461 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d)\n", priv->txHead, priv->txTail );
1462 head_list = priv->txList + priv->txHead;
1463 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1464 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1465 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1466 ack |= TLAN_HC_GO;
1467 } else {
1468 priv->txInProgress = 0;
1469 }
1470 }
1471
1472 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1473 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1474 if ( priv->timer.function == NULL ) {
1475 priv->timer.function = &TLan_Timer;
1476 priv->timer.data = (unsigned long) dev;
1477 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1478 priv->timerSetAt = jiffies;
1479 priv->timerType = TLAN_TIMER_ACTIVITY;
1480 add_timer(&priv->timer);
1481 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1482 priv->timerSetAt = jiffies;
1483 }
1484 }
1485
1486 return ack;
1487
1488}
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int )
1511{
1512 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1513
1514 return 1;
1515
1516}
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
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1532
1533
1534
1535
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1538
1539
1540
1541
1542
1543
1544
1545
1546u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1547{
1548 TLanPrivateInfo *priv = netdev_priv(dev);
1549 u32 ack = 0;
1550 int eoc = 0;
1551 u8 *head_buffer;
1552 TLanList *head_list;
1553 struct sk_buff *skb;
1554 TLanList *tail_list;
1555 void *t;
1556 u32 frameSize;
1557 u16 tmpCStat;
1558 dma_addr_t head_list_phys;
1559
1560 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOF (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail );
1561 head_list = priv->rxList + priv->rxHead;
1562 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1563
1564 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1565 frameSize = head_list->frameSize;
1566 ack++;
1567 if (tmpCStat & TLAN_CSTAT_EOC)
1568 eoc = 1;
1569
1570 if (bbuf) {
1571 skb = dev_alloc_skb(frameSize + 7);
1572 if (skb == NULL)
1573 printk(KERN_INFO "TLAN: Couldn't allocate memory for received data.\n");
1574 else {
1575 head_buffer = priv->rxBuffer + (priv->rxHead * TLAN_MAX_FRAME_SIZE);
1576 skb_reserve(skb, 2);
1577 t = (void *) skb_put(skb, frameSize);
1578
1579 priv->stats.rx_bytes += head_list->frameSize;
1580
1581 memcpy( t, head_buffer, frameSize );
1582 skb->protocol = eth_type_trans( skb, dev );
1583 netif_rx( skb );
1584 }
1585 } else {
1586 struct sk_buff *new_skb;
1587
1588
1589
1590
1591
1592
1593
1594 new_skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 );
1595
1596 if ( new_skb != NULL ) {
1597 skb = TLan_GetSKB(head_list);
1598 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1599 skb_trim( skb, frameSize );
1600
1601 priv->stats.rx_bytes += frameSize;
1602
1603 skb->protocol = eth_type_trans( skb, dev );
1604 netif_rx( skb );
1605
1606 skb_reserve( new_skb, 2 );
1607 t = (void *) skb_put( new_skb, TLAN_MAX_FRAME_SIZE );
1608 head_list->buffer[0].address = pci_map_single(priv->pciDev, new_skb->data, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1609 head_list->buffer[8].address = (u32) t;
1610 TLan_StoreSKB(head_list, new_skb);
1611 } else
1612 printk(KERN_WARNING "TLAN: Couldn't allocate memory for received data.\n" );
1613 }
1614
1615 head_list->forward = 0;
1616 head_list->cStat = 0;
1617 tail_list = priv->rxList + priv->rxTail;
1618 tail_list->forward = head_list_phys;
1619
1620 CIRC_INC( priv->rxHead, TLAN_NUM_RX_LISTS );
1621 CIRC_INC( priv->rxTail, TLAN_NUM_RX_LISTS );
1622 head_list = priv->rxList + priv->rxHead;
1623 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1624 }
1625
1626 if (!ack)
1627 printk(KERN_INFO "TLAN: Received interrupt for uncompleted RX frame.\n");
1628
1629
1630
1631
1632 if ( eoc ) {
1633 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail );
1634 head_list = priv->rxList + priv->rxHead;
1635 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1636 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1637 ack |= TLAN_HC_GO | TLAN_HC_RT;
1638 priv->rxEocCount++;
1639 }
1640
1641 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1642 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1643 if ( priv->timer.function == NULL ) {
1644 priv->timer.function = &TLan_Timer;
1645 priv->timer.data = (unsigned long) dev;
1646 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1647 priv->timerSetAt = jiffies;
1648 priv->timerType = TLAN_TIMER_ACTIVITY;
1649 add_timer(&priv->timer);
1650 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1651 priv->timerSetAt = jiffies;
1652 }
1653 }
1654
1655 dev->last_rx = jiffies;
1656
1657 return ack;
1658
1659}
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681u32 TLan_HandleDummy( struct net_device *dev, u16 host_int )
1682{
1683 printk( "TLAN: Test interrupt on %s.\n", dev->name );
1684 return 1;
1685
1686}
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int )
1712{
1713 TLanPrivateInfo *priv = netdev_priv(dev);
1714 TLanList *head_list;
1715 dma_addr_t head_list_phys;
1716 u32 ack = 1;
1717
1718 host_int = 0;
1719 if ( priv->tlanRev < 0x30 ) {
1720 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d) -- IRQ\n", priv->txHead, priv->txTail );
1721 head_list = priv->txList + priv->txHead;
1722 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1723 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1724 netif_stop_queue(dev);
1725 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1726 ack |= TLAN_HC_GO;
1727 } else {
1728 priv->txInProgress = 0;
1729 }
1730 }
1731
1732 return ack;
1733
1734}
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int )
1760{
1761 TLanPrivateInfo *priv = netdev_priv(dev);
1762 u32 ack;
1763 u32 error;
1764 u8 net_sts;
1765 u32 phy;
1766 u16 tlphy_ctl;
1767 u16 tlphy_sts;
1768
1769 ack = 1;
1770 if ( host_int & TLAN_HI_IV_MASK ) {
1771 netif_stop_queue( dev );
1772 error = inl( dev->base_addr + TLAN_CH_PARM );
1773 printk( "TLAN: %s: Adaptor Error = 0x%x\n", dev->name, error );
1774 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1775 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1776
1777 schedule_work(&priv->tlan_tqueue);
1778
1779 netif_wake_queue(dev);
1780 ack = 0;
1781 } else {
1782 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Status Check\n", dev->name );
1783 phy = priv->phy[priv->phyNum];
1784
1785 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS );
1786 if ( net_sts ) {
1787 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts );
1788 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Net_Sts = %x\n", dev->name, (unsigned) net_sts );
1789 }
1790 if ( ( net_sts & TLAN_NET_STS_MIRQ ) && ( priv->phyNum == 0 ) ) {
1791 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
1792 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
1793 if ( ! ( tlphy_sts & TLAN_TS_POLOK ) && ! ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1794 tlphy_ctl |= TLAN_TC_SWAPOL;
1795 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1796 } else if ( ( tlphy_sts & TLAN_TS_POLOK ) && ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1797 tlphy_ctl &= ~TLAN_TC_SWAPOL;
1798 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1799 }
1800
1801 if (debug) {
1802 TLan_PhyPrint( dev );
1803 }
1804 }
1805 }
1806
1807 return ack;
1808
1809}
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int )
1835{
1836 TLanPrivateInfo *priv = netdev_priv(dev);
1837 dma_addr_t head_list_phys;
1838 u32 ack = 1;
1839
1840 if ( priv->tlanRev < 0x30 ) {
1841 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d) -- IRQ\n", priv->rxHead, priv->rxTail );
1842 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1843 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1844 ack |= TLAN_HC_GO | TLAN_HC_RT;
1845 priv->rxEocCount++;
1846 }
1847
1848 return ack;
1849
1850}
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
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1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894void TLan_Timer( unsigned long data )
1895{
1896 struct net_device *dev = (struct net_device *) data;
1897 TLanPrivateInfo *priv = netdev_priv(dev);
1898 u32 elapsed;
1899 unsigned long flags = 0;
1900
1901 priv->timer.function = NULL;
1902
1903 switch ( priv->timerType ) {
1904#ifdef MONITOR
1905 case TLAN_TIMER_LINK_BEAT:
1906 TLan_PhyMonitor( dev );
1907 break;
1908#endif
1909 case TLAN_TIMER_PHY_PDOWN:
1910 TLan_PhyPowerDown( dev );
1911 break;
1912 case TLAN_TIMER_PHY_PUP:
1913 TLan_PhyPowerUp( dev );
1914 break;
1915 case TLAN_TIMER_PHY_RESET:
1916 TLan_PhyReset( dev );
1917 break;
1918 case TLAN_TIMER_PHY_START_LINK:
1919 TLan_PhyStartLink( dev );
1920 break;
1921 case TLAN_TIMER_PHY_FINISH_AN:
1922 TLan_PhyFinishAutoNeg( dev );
1923 break;
1924 case TLAN_TIMER_FINISH_RESET:
1925 TLan_FinishReset( dev );
1926 break;
1927 case TLAN_TIMER_ACTIVITY:
1928 spin_lock_irqsave(&priv->lock, flags);
1929 if ( priv->timer.function == NULL ) {
1930 elapsed = jiffies - priv->timerSetAt;
1931 if ( elapsed >= TLAN_TIMER_ACT_DELAY ) {
1932 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
1933 } else {
1934 priv->timer.function = &TLan_Timer;
1935 priv->timer.expires = priv->timerSetAt + TLAN_TIMER_ACT_DELAY;
1936 spin_unlock_irqrestore(&priv->lock, flags);
1937 add_timer( &priv->timer );
1938 break;
1939 }
1940 }
1941 spin_unlock_irqrestore(&priv->lock, flags);
1942 break;
1943 default:
1944 break;
1945 }
1946
1947}
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975void TLan_ResetLists( struct net_device *dev )
1976{
1977 TLanPrivateInfo *priv = netdev_priv(dev);
1978 int i;
1979 TLanList *list;
1980 dma_addr_t list_phys;
1981 struct sk_buff *skb;
1982 void *t = NULL;
1983
1984 priv->txHead = 0;
1985 priv->txTail = 0;
1986 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
1987 list = priv->txList + i;
1988 list->cStat = TLAN_CSTAT_UNUSED;
1989 if ( bbuf ) {
1990 list->buffer[0].address = priv->txBufferDMA + ( i * TLAN_MAX_FRAME_SIZE );
1991 } else {
1992 list->buffer[0].address = 0;
1993 }
1994 list->buffer[2].count = 0;
1995 list->buffer[2].address = 0;
1996 list->buffer[8].address = 0;
1997 list->buffer[9].address = 0;
1998 }
1999
2000 priv->rxHead = 0;
2001 priv->rxTail = TLAN_NUM_RX_LISTS - 1;
2002 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
2003 list = priv->rxList + i;
2004 list_phys = priv->rxListDMA + sizeof(TLanList) * i;
2005 list->cStat = TLAN_CSTAT_READY;
2006 list->frameSize = TLAN_MAX_FRAME_SIZE;
2007 list->buffer[0].count = TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
2008 if ( bbuf ) {
2009 list->buffer[0].address = priv->rxBufferDMA + ( i * TLAN_MAX_FRAME_SIZE );
2010 } else {
2011 skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 );
2012 if ( skb == NULL ) {
2013 printk( "TLAN: Couldn't allocate memory for received data.\n" );
2014
2015 } else {
2016 skb->dev = dev;
2017 skb_reserve( skb, 2 );
2018 t = (void *) skb_put( skb, TLAN_MAX_FRAME_SIZE );
2019 }
2020 list->buffer[0].address = pci_map_single(priv->pciDev, t, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
2021 list->buffer[8].address = (u32) t;
2022 TLan_StoreSKB(list, skb);
2023 }
2024 list->buffer[1].count = 0;
2025 list->buffer[1].address = 0;
2026 if ( i < TLAN_NUM_RX_LISTS - 1 )
2027 list->forward = list_phys + sizeof(TLanList);
2028 else
2029 list->forward = 0;
2030 }
2031
2032}
2033
2034
2035void TLan_FreeLists( struct net_device *dev )
2036{
2037 TLanPrivateInfo *priv = netdev_priv(dev);
2038 int i;
2039 TLanList *list;
2040 struct sk_buff *skb;
2041
2042 if ( ! bbuf ) {
2043 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
2044 list = priv->txList + i;
2045 skb = TLan_GetSKB(list);
2046 if ( skb ) {
2047 pci_unmap_single(priv->pciDev, list->buffer[0].address, skb->len, PCI_DMA_TODEVICE);
2048 dev_kfree_skb_any( skb );
2049 list->buffer[8].address = 0;
2050 list->buffer[9].address = 0;
2051 }
2052 }
2053
2054 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
2055 list = priv->rxList + i;
2056 skb = TLan_GetSKB(list);
2057 if ( skb ) {
2058 pci_unmap_single(priv->pciDev, list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
2059 dev_kfree_skb_any( skb );
2060 list->buffer[8].address = 0;
2061 list->buffer[9].address = 0;
2062 }
2063 }
2064 }
2065}
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084void TLan_PrintDio( u16 io_base )
2085{
2086 u32 data0, data1;
2087 int i;
2088
2089 printk( "TLAN: Contents of internal registers for io base 0x%04hx.\n", io_base );
2090 printk( "TLAN: Off. +0 +4\n" );
2091 for ( i = 0; i < 0x4C; i+= 8 ) {
2092 data0 = TLan_DioRead32( io_base, i );
2093 data1 = TLan_DioRead32( io_base, i + 0x4 );
2094 printk( "TLAN: 0x%02x 0x%08x 0x%08x\n", i, data0, data1 );
2095 }
2096
2097}
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119void TLan_PrintList( TLanList *list, char *type, int num)
2120{
2121 int i;
2122
2123 printk( "TLAN: %s List %d at 0x%08x\n", type, num, (u32) list );
2124 printk( "TLAN: Forward = 0x%08x\n", list->forward );
2125 printk( "TLAN: CSTAT = 0x%04hx\n", list->cStat );
2126 printk( "TLAN: Frame Size = 0x%04hx\n", list->frameSize );
2127
2128 for ( i = 0; i < 2; i++ ) {
2129 printk( "TLAN: Buffer[%d].count, addr = 0x%08x, 0x%08x\n", i, list->buffer[i].count, list->buffer[i].address );
2130 }
2131
2132}
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155void TLan_ReadAndClearStats( struct net_device *dev, int record )
2156{
2157 TLanPrivateInfo *priv = netdev_priv(dev);
2158 u32 tx_good, tx_under;
2159 u32 rx_good, rx_over;
2160 u32 def_tx, crc, code;
2161 u32 multi_col, single_col;
2162 u32 excess_col, late_col, loss;
2163
2164 outw( TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2165 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2166 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2167 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2168 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2169
2170 outw( TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2171 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2172 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2173 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2174 rx_over = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2175
2176 outw( TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR );
2177 def_tx = inb( dev->base_addr + TLAN_DIO_DATA );
2178 def_tx += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2179 crc = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2180 code = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2181
2182 outw( TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2183 multi_col = inb( dev->base_addr + TLAN_DIO_DATA );
2184 multi_col += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2185 single_col = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2186 single_col += inb( dev->base_addr + TLAN_DIO_DATA + 3 ) << 8;
2187
2188 outw( TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2189 excess_col = inb( dev->base_addr + TLAN_DIO_DATA );
2190 late_col = inb( dev->base_addr + TLAN_DIO_DATA + 1 );
2191 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2192
2193 if ( record ) {
2194 priv->stats.rx_packets += rx_good;
2195 priv->stats.rx_errors += rx_over + crc + code;
2196 priv->stats.tx_packets += tx_good;
2197 priv->stats.tx_errors += tx_under + loss;
2198 priv->stats.collisions += multi_col + single_col + excess_col + late_col;
2199
2200 priv->stats.rx_over_errors += rx_over;
2201 priv->stats.rx_crc_errors += crc;
2202 priv->stats.rx_frame_errors += code;
2203
2204 priv->stats.tx_aborted_errors += tx_under;
2205 priv->stats.tx_carrier_errors += loss;
2206 }
2207
2208}
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230void
2231TLan_ResetAdapter( struct net_device *dev )
2232{
2233 TLanPrivateInfo *priv = netdev_priv(dev);
2234 int i;
2235 u32 addr;
2236 u32 data;
2237 u8 data8;
2238
2239 priv->tlanFullDuplex = FALSE;
2240 priv->phyOnline=0;
2241 netif_carrier_off(dev);
2242
2243
2244
2245 data = inl(dev->base_addr + TLAN_HOST_CMD);
2246 data |= TLAN_HC_AD_RST;
2247 outl(data, dev->base_addr + TLAN_HOST_CMD);
2248
2249 udelay(1000);
2250
2251
2252
2253 data = inl(dev->base_addr + TLAN_HOST_CMD);
2254 data |= TLAN_HC_INT_OFF;
2255 outl(data, dev->base_addr + TLAN_HOST_CMD);
2256
2257
2258
2259 for ( i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4 ) {
2260 TLan_DioWrite32( dev->base_addr, (u16) i, 0 );
2261 }
2262
2263
2264
2265 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2266 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2267
2268
2269
2270 outl( TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD );
2271 outl( TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD );
2272
2273
2274
2275 outw( TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR );
2276 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2277 TLan_SetBit( TLAN_NET_SIO_NMRST, addr );
2278
2279
2280
2281 if ( priv->tlanRev >= 0x30 ) {
2282 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
2283 TLan_DioWrite8( dev->base_addr, TLAN_INT_DIS, data8 );
2284 }
2285 TLan_PhyDetect( dev );
2286 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
2287
2288 if ( priv->adapter->flags & TLAN_ADAPTER_BIT_RATE_PHY ) {
2289 data |= TLAN_NET_CFG_BIT;
2290 if ( priv->aui == 1 ) {
2291 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x0a );
2292 } else if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2293 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x00 );
2294 priv->tlanFullDuplex = TRUE;
2295 } else {
2296 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x08 );
2297 }
2298 }
2299
2300 if ( priv->phyNum == 0 ) {
2301 data |= TLAN_NET_CFG_PHY_EN;
2302 }
2303 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2304
2305 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2306 TLan_FinishReset( dev );
2307 } else {
2308 TLan_PhyPowerDown( dev );
2309 }
2310
2311}
2312
2313
2314
2315
2316void
2317TLan_FinishReset( struct net_device *dev )
2318{
2319 TLanPrivateInfo *priv = netdev_priv(dev);
2320 u8 data;
2321 u32 phy;
2322 u8 sio;
2323 u16 status;
2324 u16 partner;
2325 u16 tlphy_ctl;
2326 u16 tlphy_par;
2327 u16 tlphy_id1, tlphy_id2;
2328 int i;
2329
2330 phy = priv->phy[priv->phyNum];
2331
2332 data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
2333 if ( priv->tlanFullDuplex ) {
2334 data |= TLAN_NET_CMD_DUPLEX;
2335 }
2336 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, data );
2337 data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
2338 if ( priv->phyNum == 0 ) {
2339 data |= TLAN_NET_MASK_MASK7;
2340 }
2341 TLan_DioWrite8( dev->base_addr, TLAN_NET_MASK, data );
2342 TLan_DioWrite16( dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7 );
2343 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
2344 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
2345
2346 if ( ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) || ( priv->aui ) ) {
2347 status = MII_GS_LINK;
2348 printk( "TLAN: %s: Link forced.\n", dev->name );
2349 } else {
2350 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2351 udelay( 1000 );
2352 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2353 if ( (status & MII_GS_LINK) &&
2354 (tlphy_id1 == NAT_SEM_ID1) &&
2355 (tlphy_id2 == NAT_SEM_ID2) ) {
2356 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
2357 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_PAR, &tlphy_par );
2358
2359 printk( "TLAN: %s: Link active with ", dev->name );
2360 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
2361 printk( "forced 10%sMbps %s-Duplex\n",
2362 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2363 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2364 } else {
2365 printk( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
2366 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2367 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2368 printk("TLAN: Partner capability: ");
2369 for (i = 5; i <= 10; i++)
2370 if (partner & (1<<i))
2371 printk("%s",media[i-5]);
2372 printk("\n");
2373 }
2374
2375 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2376#ifdef MONITOR
2377
2378 priv->link = 1;
2379
2380 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_LINK_BEAT );
2381#endif
2382 } else if (status & MII_GS_LINK) {
2383 printk( "TLAN: %s: Link active\n", dev->name );
2384 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2385 }
2386 }
2387
2388 if ( priv->phyNum == 0 ) {
2389 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
2390 tlphy_ctl |= TLAN_TC_INTEN;
2391 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl );
2392 sio = TLan_DioRead8( dev->base_addr, TLAN_NET_SIO );
2393 sio |= TLAN_NET_SIO_MINTEN;
2394 TLan_DioWrite8( dev->base_addr, TLAN_NET_SIO, sio );
2395 }
2396
2397 if ( status & MII_GS_LINK ) {
2398 TLan_SetMac( dev, 0, dev->dev_addr );
2399 priv->phyOnline = 1;
2400 outb( ( TLAN_HC_INT_ON >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2401 if ( debug >= 1 && debug != TLAN_DEBUG_PROBE ) {
2402 outb( ( TLAN_HC_REQ_INT >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2403 }
2404 outl( priv->rxListDMA, dev->base_addr + TLAN_CH_PARM );
2405 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD );
2406 netif_carrier_on(dev);
2407 } else {
2408 printk( "TLAN: %s: Link inactive, will retry in 10 secs...\n", dev->name );
2409 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET );
2410 return;
2411 }
2412 TLan_SetMulticastList(dev);
2413
2414}
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440void TLan_SetMac( struct net_device *dev, int areg, char *mac )
2441{
2442 int i;
2443
2444 areg *= 6;
2445
2446 if ( mac != NULL ) {
2447 for ( i = 0; i < 6; i++ )
2448 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, mac[i] );
2449 } else {
2450 for ( i = 0; i < 6; i++ )
2451 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, 0 );
2452 }
2453
2454}
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482void TLan_PhyPrint( struct net_device *dev )
2483{
2484 TLanPrivateInfo *priv = netdev_priv(dev);
2485 u16 i, data0, data1, data2, data3, phy;
2486
2487 phy = priv->phy[priv->phyNum];
2488
2489 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2490 printk( "TLAN: Device %s, Unmanaged PHY.\n", dev->name );
2491 } else if ( phy <= TLAN_PHY_MAX_ADDR ) {
2492 printk( "TLAN: Device %s, PHY 0x%02x.\n", dev->name, phy );
2493 printk( "TLAN: Off. +0 +1 +2 +3 \n" );
2494 for ( i = 0; i < 0x20; i+= 4 ) {
2495 printk( "TLAN: 0x%02x", i );
2496 TLan_MiiReadReg( dev, phy, i, &data0 );
2497 printk( " 0x%04hx", data0 );
2498 TLan_MiiReadReg( dev, phy, i + 1, &data1 );
2499 printk( " 0x%04hx", data1 );
2500 TLan_MiiReadReg( dev, phy, i + 2, &data2 );
2501 printk( " 0x%04hx", data2 );
2502 TLan_MiiReadReg( dev, phy, i + 3, &data3 );
2503 printk( " 0x%04hx\n", data3 );
2504 }
2505 } else {
2506 printk( "TLAN: Device %s, Invalid PHY.\n", dev->name );
2507 }
2508
2509}
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531void TLan_PhyDetect( struct net_device *dev )
2532{
2533 TLanPrivateInfo *priv = netdev_priv(dev);
2534 u16 control;
2535 u16 hi;
2536 u16 lo;
2537 u32 phy;
2538
2539 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2540 priv->phyNum = 0xFFFF;
2541 return;
2542 }
2543
2544 TLan_MiiReadReg( dev, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi );
2545
2546 if ( hi != 0xFFFF ) {
2547 priv->phy[0] = TLAN_PHY_MAX_ADDR;
2548 } else {
2549 priv->phy[0] = TLAN_PHY_NONE;
2550 }
2551
2552 priv->phy[1] = TLAN_PHY_NONE;
2553 for ( phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++ ) {
2554 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
2555 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
2556 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
2557 if ( ( control != 0xFFFF ) || ( hi != 0xFFFF ) || ( lo != 0xFFFF ) ) {
2558 TLAN_DBG( TLAN_DEBUG_GNRL, "PHY found at %02x %04x %04x %04x\n", phy, control, hi, lo );
2559 if ( ( priv->phy[1] == TLAN_PHY_NONE ) && ( phy != TLAN_PHY_MAX_ADDR ) ) {
2560 priv->phy[1] = phy;
2561 }
2562 }
2563 }
2564
2565 if ( priv->phy[1] != TLAN_PHY_NONE ) {
2566 priv->phyNum = 1;
2567 } else if ( priv->phy[0] != TLAN_PHY_NONE ) {
2568 priv->phyNum = 0;
2569 } else {
2570 printk( "TLAN: Cannot initialize device, no PHY was found!\n" );
2571 }
2572
2573}
2574
2575
2576
2577
2578void TLan_PhyPowerDown( struct net_device *dev )
2579{
2580 TLanPrivateInfo *priv = netdev_priv(dev);
2581 u16 value;
2582
2583 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering down PHY(s).\n", dev->name );
2584 value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
2585 TLan_MiiSync( dev->base_addr );
2586 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2587 if ( ( priv->phyNum == 0 ) && ( priv->phy[1] != TLAN_PHY_NONE ) && ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) {
2588 TLan_MiiSync( dev->base_addr );
2589 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
2590 }
2591
2592
2593
2594
2595
2596 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP );
2597
2598}
2599
2600
2601
2602
2603void TLan_PhyPowerUp( struct net_device *dev )
2604{
2605 TLanPrivateInfo *priv = netdev_priv(dev);
2606 u16 value;
2607
2608 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering up PHY.\n", dev->name );
2609 TLan_MiiSync( dev->base_addr );
2610 value = MII_GC_LOOPBK;
2611 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2612 TLan_MiiSync(dev->base_addr);
2613
2614
2615
2616
2617 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET );
2618
2619}
2620
2621
2622
2623
2624void TLan_PhyReset( struct net_device *dev )
2625{
2626 TLanPrivateInfo *priv = netdev_priv(dev);
2627 u16 phy;
2628 u16 value;
2629
2630 phy = priv->phy[priv->phyNum];
2631
2632 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Reseting PHY.\n", dev->name );
2633 TLan_MiiSync( dev->base_addr );
2634 value = MII_GC_LOOPBK | MII_GC_RESET;
2635 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, value );
2636 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2637 while ( value & MII_GC_RESET ) {
2638 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2639 }
2640
2641
2642
2643
2644
2645 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK );
2646
2647}
2648
2649
2650
2651
2652void TLan_PhyStartLink( struct net_device *dev )
2653{
2654 TLanPrivateInfo *priv = netdev_priv(dev);
2655 u16 ability;
2656 u16 control;
2657 u16 data;
2658 u16 phy;
2659 u16 status;
2660 u16 tctl;
2661
2662 phy = priv->phy[priv->phyNum];
2663 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Trying to activate link.\n", dev->name );
2664 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2665 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &ability );
2666
2667 if ( ( status & MII_GS_AUTONEG ) &&
2668 ( ! priv->aui ) ) {
2669 ability = status >> 11;
2670 if ( priv->speed == TLAN_SPEED_10 &&
2671 priv->duplex == TLAN_DUPLEX_HALF) {
2672 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0000);
2673 } else if ( priv->speed == TLAN_SPEED_10 &&
2674 priv->duplex == TLAN_DUPLEX_FULL) {
2675 priv->tlanFullDuplex = TRUE;
2676 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0100);
2677 } else if ( priv->speed == TLAN_SPEED_100 &&
2678 priv->duplex == TLAN_DUPLEX_HALF) {
2679 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2000);
2680 } else if ( priv->speed == TLAN_SPEED_100 &&
2681 priv->duplex == TLAN_DUPLEX_FULL) {
2682 priv->tlanFullDuplex = TRUE;
2683 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2100);
2684 } else {
2685
2686
2687 TLan_MiiWriteReg( dev, phy, MII_AN_ADV, (ability << 5) | 1);
2688
2689 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1000 );
2690
2691 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1200 );
2692
2693
2694
2695
2696
2697 printk( "TLAN: %s: Starting autonegotiation.\n", dev->name );
2698 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN );
2699 return;
2700 }
2701
2702 }
2703
2704 if ( ( priv->aui ) && ( priv->phyNum != 0 ) ) {
2705 priv->phyNum = 0;
2706 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2707 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2708 TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2709 return;
2710 } else if ( priv->phyNum == 0 ) {
2711 control = 0;
2712 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tctl );
2713 if ( priv->aui ) {
2714 tctl |= TLAN_TC_AUISEL;
2715 } else {
2716 tctl &= ~TLAN_TC_AUISEL;
2717 if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2718 control |= MII_GC_DUPLEX;
2719 priv->tlanFullDuplex = TRUE;
2720 }
2721 if ( priv->speed == TLAN_SPEED_100 ) {
2722 control |= MII_GC_SPEEDSEL;
2723 }
2724 }
2725 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, control );
2726 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tctl );
2727 }
2728
2729
2730
2731
2732 TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET );
2733
2734}
2735
2736
2737
2738
2739void TLan_PhyFinishAutoNeg( struct net_device *dev )
2740{
2741 TLanPrivateInfo *priv = netdev_priv(dev);
2742 u16 an_adv;
2743 u16 an_lpa;
2744 u16 data;
2745 u16 mode;
2746 u16 phy;
2747 u16 status;
2748
2749 phy = priv->phy[priv->phyNum];
2750
2751 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2752 udelay( 1000 );
2753 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2754
2755 if ( ! ( status & MII_GS_AUTOCMPLT ) ) {
2756
2757
2758
2759 if (!priv->neg_be_verbose++) {
2760 printk(KERN_INFO "TLAN: Giving autonegotiation more time.\n");
2761 printk(KERN_INFO "TLAN: Please check that your adapter has\n");
2762 printk(KERN_INFO "TLAN: been properly connected to a HUB or Switch.\n");
2763 printk(KERN_INFO "TLAN: Trying to establish link in the background...\n");
2764 }
2765 TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN );
2766 return;
2767 }
2768
2769 printk( "TLAN: %s: Autonegotiation complete.\n", dev->name );
2770 TLan_MiiReadReg( dev, phy, MII_AN_ADV, &an_adv );
2771 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &an_lpa );
2772 mode = an_adv & an_lpa & 0x03E0;
2773 if ( mode & 0x0100 ) {
2774 priv->tlanFullDuplex = TRUE;
2775 } else if ( ! ( mode & 0x0080 ) && ( mode & 0x0040 ) ) {
2776 priv->tlanFullDuplex = TRUE;
2777 }
2778
2779 if ( ( ! ( mode & 0x0180 ) ) && ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) && ( priv->phyNum != 0 ) ) {
2780 priv->phyNum = 0;
2781 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2782 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2783 TLan_SetTimer( dev, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2784 return;
2785 }
2786
2787 if ( priv->phyNum == 0 ) {
2788 if ( ( priv->duplex == TLAN_DUPLEX_FULL ) || ( an_adv & an_lpa & 0x0040 ) ) {
2789 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB | MII_GC_DUPLEX );
2790 printk( "TLAN: Starting internal PHY with FULL-DUPLEX\n" );
2791 } else {
2792 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
2793 printk( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
2794 }
2795 }
2796
2797
2798
2799 TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET );
2800
2801}
2802
2803#ifdef MONITOR
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823void TLan_PhyMonitor( struct net_device *dev )
2824{
2825 TLanPrivateInfo *priv = netdev_priv(dev);
2826 u16 phy;
2827 u16 phy_status;
2828
2829 phy = priv->phy[priv->phyNum];
2830
2831
2832 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &phy_status );
2833
2834
2835 if (!(phy_status & MII_GS_LINK)) {
2836 if (priv->link) {
2837 priv->link = 0;
2838 printk(KERN_DEBUG "TLAN: %s has lost link\n", dev->name);
2839 netif_carrier_off(dev);
2840 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2841 return;
2842 }
2843 }
2844
2845
2846 if ((phy_status & MII_GS_LINK) && !priv->link) {
2847 priv->link = 1;
2848 printk(KERN_DEBUG "TLAN: %s has reestablished link\n", dev->name);
2849 netif_carrier_on(dev);
2850 }
2851
2852
2853 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2854}
2855
2856#endif
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val )
2896{
2897 u8 nack;
2898 u16 sio, tmp;
2899 u32 i;
2900 int err;
2901 int minten;
2902 TLanPrivateInfo *priv = netdev_priv(dev);
2903 unsigned long flags = 0;
2904
2905 err = FALSE;
2906 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
2907 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2908
2909 if (!in_irq())
2910 spin_lock_irqsave(&priv->lock, flags);
2911
2912 TLan_MiiSync(dev->base_addr);
2913
2914 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
2915 if ( minten )
2916 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
2917
2918 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
2919 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
2920 TLan_MiiSendData( dev->base_addr, phy, 5 );
2921 TLan_MiiSendData( dev->base_addr, reg, 5 );
2922
2923
2924 TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
2925
2926 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2927 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2928 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2929
2930 nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);
2931 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2932 if (nack) {
2933 for (i = 0; i < 16; i++) {
2934 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2935 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2936 }
2937 tmp = 0xffff;
2938 err = TRUE;
2939 } else {
2940 for (tmp = 0, i = 0x8000; i; i >>= 1) {
2941 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2942 if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
2943 tmp |= i;
2944 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2945 }
2946 }
2947
2948
2949 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2950 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2951
2952 if ( minten )
2953 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
2954
2955 *val = tmp;
2956
2957 if (!in_irq())
2958 spin_unlock_irqrestore(&priv->lock, flags);
2959
2960 return err;
2961
2962}
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits )
2986{
2987 u16 sio;
2988 u32 i;
2989
2990 if ( num_bits == 0 )
2991 return;
2992
2993 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
2994 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
2995 TLan_SetBit( TLAN_NET_SIO_MTXEN, sio );
2996
2997 for ( i = ( 0x1 << ( num_bits - 1 ) ); i; i >>= 1 ) {
2998 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
2999 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
3000 if ( data & i )
3001 TLan_SetBit( TLAN_NET_SIO_MDATA, sio );
3002 else
3003 TLan_ClearBit( TLAN_NET_SIO_MDATA, sio );
3004 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3005 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
3006 }
3007
3008}
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027void TLan_MiiSync( u16 base_port )
3028{
3029 int i;
3030 u16 sio;
3031
3032 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
3033 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
3034
3035 TLan_ClearBit( TLAN_NET_SIO_MTXEN, sio );
3036 for ( i = 0; i < 32; i++ ) {
3037 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3038 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3039 }
3040
3041}
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val )
3067{
3068 u16 sio;
3069 int minten;
3070 unsigned long flags = 0;
3071 TLanPrivateInfo *priv = netdev_priv(dev);
3072
3073 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
3074 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
3075
3076 if (!in_irq())
3077 spin_lock_irqsave(&priv->lock, flags);
3078
3079 TLan_MiiSync( dev->base_addr );
3080
3081 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
3082 if ( minten )
3083 TLan_ClearBit( TLAN_NET_SIO_MINTEN, sio );
3084
3085 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3086 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3087 TLan_MiiSendData( dev->base_addr, phy, 5 );
3088 TLan_MiiSendData( dev->base_addr, reg, 5 );
3089
3090 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
3091 TLan_MiiSendData( dev->base_addr, val, 16 );
3092
3093 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3094 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3095
3096 if ( minten )
3097 TLan_SetBit( TLAN_NET_SIO_MINTEN, sio );
3098
3099 if (!in_irq())
3100 spin_unlock_irqrestore(&priv->lock, flags);
3101
3102}
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136void TLan_EeSendStart( u16 io_base )
3137{
3138 u16 sio;
3139
3140 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3141 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3142
3143 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3144 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3145 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3146 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3147 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3148
3149}
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176int TLan_EeSendByte( u16 io_base, u8 data, int stop )
3177{
3178 int err;
3179 u8 place;
3180 u16 sio;
3181
3182 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3183 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3184
3185
3186 for ( place = 0x80; place != 0; place >>= 1 ) {
3187 if ( place & data )
3188 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3189 else
3190 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3191 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3192 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3193 }
3194 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3195 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3196 err = TLan_GetBit( TLAN_NET_SIO_EDATA, sio );
3197 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3198 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3199
3200 if ( ( ! err ) && stop ) {
3201 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3202 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3203 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3204 }
3205
3206 return ( err );
3207
3208}
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop )
3238{
3239 u8 place;
3240 u16 sio;
3241
3242 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3243 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3244 *data = 0;
3245
3246
3247 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3248 for ( place = 0x80; place; place >>= 1 ) {
3249 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3250 if ( TLan_GetBit( TLAN_NET_SIO_EDATA, sio ) )
3251 *data |= place;
3252 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3253 }
3254
3255 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3256 if ( ! stop ) {
3257 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3258 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3259 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3260 } else {
3261 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3262 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3263 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3264 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3265 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3266 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3267 }
3268
3269}
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295int TLan_EeReadByte( struct net_device *dev, u8 ee_addr, u8 *data )
3296{
3297 int err;
3298 TLanPrivateInfo *priv = netdev_priv(dev);
3299 unsigned long flags = 0;
3300 int ret=0;
3301
3302 spin_lock_irqsave(&priv->lock, flags);
3303
3304 TLan_EeSendStart( dev->base_addr );
3305 err = TLan_EeSendByte( dev->base_addr, 0xA0, TLAN_EEPROM_ACK );
3306 if (err)
3307 {
3308 ret=1;
3309 goto fail;
3310 }
3311 err = TLan_EeSendByte( dev->base_addr, ee_addr, TLAN_EEPROM_ACK );
3312 if (err)
3313 {
3314 ret=2;
3315 goto fail;
3316 }
3317 TLan_EeSendStart( dev->base_addr );
3318 err = TLan_EeSendByte( dev->base_addr, 0xA1, TLAN_EEPROM_ACK );
3319 if (err)
3320 {
3321 ret=3;
3322 goto fail;
3323 }
3324 TLan_EeReceiveByte( dev->base_addr, data, TLAN_EEPROM_STOP );
3325fail:
3326 spin_unlock_irqrestore(&priv->lock, flags);
3327
3328 return ret;
3329
3330}
3331
3332
3333
3334