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446#include <linux/module.h>
447#include <linux/kernel.h>
448#include <linux/string.h>
449#include <linux/interrupt.h>
450#include <linux/ptrace.h>
451#include <linux/errno.h>
452#include <linux/ioport.h>
453#include <linux/slab.h>
454#include <linux/pci.h>
455#include <linux/eisa.h>
456#include <linux/delay.h>
457#include <linux/init.h>
458#include <linux/spinlock.h>
459#include <linux/crc32.h>
460#include <linux/netdevice.h>
461#include <linux/etherdevice.h>
462#include <linux/skbuff.h>
463#include <linux/time.h>
464#include <linux/types.h>
465#include <linux/unistd.h>
466#include <linux/ctype.h>
467#include <linux/dma-mapping.h>
468#include <linux/moduleparam.h>
469#include <linux/bitops.h>
470
471#include <asm/io.h>
472#include <asm/dma.h>
473#include <asm/byteorder.h>
474#include <asm/unaligned.h>
475#include <asm/uaccess.h>
476#ifdef CONFIG_PPC_PMAC
477#include <asm/machdep.h>
478#endif
479
480#include "de4x5.h"
481
482static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
483
484#define c_char const char
485#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((__le16 *)(a)))
486
487
488
489
490struct phy_table {
491 int reset;
492 int id;
493 int ta;
494 struct {
495 int reg;
496 int mask;
497 int value;
498 } spd;
499};
500
501struct mii_phy {
502 int reset;
503 int id;
504 int ta;
505 struct {
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr;
511 u_char *gep;
512 u_char *rst;
513 u_int mc;
514 u_int ana;
515 u_int fdx;
516 u_int ttm;
517 u_int mci;
518};
519
520#define DE4X5_MAX_PHY 8
521
522struct sia_phy {
523 u_char mc;
524 u_char ext;
525 int csr13;
526 int csr14;
527 int csr15;
528 int gepc;
529 int gep;
530};
531
532
533
534
535
536static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}},
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}},
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}},
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}},
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}}
542};
543
544
545
546
547
548
549#define GENERIC_REG 0x05
550#define GENERIC_MASK MII_ANLPA_100M
551#define GENERIC_VALUE MII_ANLPA_100M
552
553
554
555
556static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559};
560
561#define SMC 1
562#define ACCTON 2
563
564
565
566
567
568
569static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08,
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574};
575
576
577#ifdef DE4X5_DEBUG
578static int de4x5_debug = DE4X5_DEBUG;
579#else
580
581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582#endif
583
584
585
586
587
588
589
590
591
592
593#ifdef DE4X5_PARM
594static char *args = DE4X5_PARM;
595#else
596static char *args;
597#endif
598
599struct parameters {
600 bool fdx;
601 int autosense;
602};
603
604#define DE4X5_AUTOSENSE_MS 250
605
606#define DE4X5_NDA 0xffe0
607
608
609
610
611#define PROBE_LENGTH 32
612#define ETH_PROM_SIG 0xAA5500FFUL
613
614
615
616
617#define PKT_BUF_SZ 1536
618#define IEEE802_3_SZ 1518
619#define MAX_PKT_SZ 1514
620#define MAX_DAT_SZ 1500
621#define MIN_DAT_SZ 1
622#define PKT_HDR_LEN 14
623#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624#define QUEUE_PKT_TIMEOUT (3*HZ)
625
626
627
628
629
630#define DE4X5_EISA_IO_PORTS 0x0c00
631#define DE4X5_EISA_TOTAL_SIZE 0x100
632
633#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636#define DE4X5_NAME_LENGTH 8
637
638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640
641
642
643#define PROBE_LENGTH 32
644#define ETH_PROM_SIG 0xAA5500FFUL
645
646
647
648
649#define PCI_MAX_BUS_NUM 8
650#define DE4X5_PCI_TOTAL_SIZE 0x80
651#define DE4X5_CLASS_CODE 0x00020000
652
653
654
655
656
657
658
659#define DE4X5_ALIGN4 ((u_long)4 - 1)
660#define DE4X5_ALIGN8 ((u_long)8 - 1)
661#define DE4X5_ALIGN16 ((u_long)16 - 1)
662#define DE4X5_ALIGN32 ((u_long)32 - 1)
663#define DE4X5_ALIGN64 ((u_long)64 - 1)
664#define DE4X5_ALIGN128 ((u_long)128 - 1)
665
666#define DE4X5_ALIGN DE4X5_ALIGN32
667#define DE4X5_CACHE_ALIGN CAL_16LONG
668#define DESC_SKIP_LEN DSL_0
669
670#define DESC_ALIGN
671
672#ifndef DEC_ONLY
673static int dec_only;
674#else
675static int dec_only = 1;
676#endif
677
678
679
680
681#define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); \
684}
685
686#define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); \
690}
691
692#define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); \
695}
696
697#define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); \
701}
702
703
704
705
706#define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); \
710}
711
712#define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); \
716}
717
718
719
720
721#define RESET_SIA outl(0, DE4X5_SICR);
722
723
724
725
726#define DE4X5_AUTOSENSE_MS 250
727
728
729
730
731struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742};
743#define SUB_VENDOR_ID 0x500a
744
745
746
747
748
749
750
751
752
753#define NUM_RX_DESC 8
754#define NUM_TX_DESC 32
755#define RX_BUFF_SZ 1536
756
757
758struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764};
765
766
767
768
769#define DE4X5_PKT_STAT_SZ 16
770#define DE4X5_PKT_BIN_SZ 128
771
772
773struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ];
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785};
786
787struct de4x5_private {
788 char adapter_name[80];
789 u_long interrupt;
790 struct de4x5_desc *rx_ring;
791 struct de4x5_desc *tx_ring;
792 struct sk_buff *tx_skb[NUM_TX_DESC];
793 struct sk_buff *rx_skb[NUM_RX_DESC];
794 int rx_new, rx_old;
795 int tx_new, tx_old;
796 char setup_frame[SETUP_FRAME_LEN];
797 char frame[64];
798 spinlock_t lock;
799 struct net_device_stats stats;
800 struct pkt_stats pktStats;
801 char rxRingSize;
802 char txRingSize;
803 int bus;
804 int bus_num;
805 int device;
806 int state;
807 int chipset;
808 s32 irq_mask;
809 s32 irq_en;
810 int media;
811 int c_media;
812 bool fdx;
813 int linkOK;
814 int autosense;
815 bool tx_enable;
816 int setup_f;
817 int local_state;
818 struct mii_phy phy[DE4X5_MAX_PHY];
819 struct sia_phy sia;
820 int active;
821 int mii_cnt;
822 int timeout;
823 struct timer_list timer;
824 int tmp;
825 struct {
826 u_long lock;
827 s32 csr0;
828 s32 csr6;
829 s32 csr7;
830 s32 gep;
831 s32 gepc;
832 s32 csr13;
833 s32 csr14;
834 s32 csr15;
835 int save_cnt;
836 struct sk_buff *skb;
837 } cache;
838 struct de4x5_srom srom;
839 int cfrv;
840 int rx_ovf;
841 bool useSROM;
842 bool useMII;
843 int asBitValid;
844 int asPolarity;
845 int asBit;
846 int defMedium;
847 int tcount;
848 int infoblock_init;
849 int infoleaf_offset;
850 s32 infoblock_csr6;
851 int infoblock_media;
852 int (*infoleaf_fn)(struct net_device *);
853 u_char *rst;
854 u_char ibn;
855 struct parameters params;
856 struct device *gendev;
857 dma_addr_t dma_rings;
858 int dma_size;
859 char *rx_bufs;
860};
861
862
863
864
865
866
867
868
869
870
871
872
873
874static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879} last = {0,};
880
881
882
883
884
885
886
887
888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894
895
896
897static int de4x5_open(struct net_device *dev);
898static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
900static int de4x5_close(struct net_device *dev);
901static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903static void set_multicast_list(struct net_device *dev);
904static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906
907
908
909static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910static int de4x5_init(struct net_device *dev);
911static int de4x5_sw_reset(struct net_device *dev);
912static int de4x5_rx(struct net_device *dev);
913static int de4x5_tx(struct net_device *dev);
914static void de4x5_ast(struct net_device *dev);
915static int de4x5_txur(struct net_device *dev);
916static int de4x5_rx_ovfc(struct net_device *dev);
917
918static int autoconf_media(struct net_device *dev);
919static void create_packet(struct net_device *dev, char *frame, int len);
920static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921static int dc21040_autoconf(struct net_device *dev);
922static int dc21041_autoconf(struct net_device *dev);
923static int dc21140m_autoconf(struct net_device *dev);
924static int dc2114x_autoconf(struct net_device *dev);
925static int srom_autoconf(struct net_device *dev);
926static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929static int test_for_100Mb(struct net_device *dev, int msec);
930static int wait_for_link(struct net_device *dev);
931static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
932static int is_spd_100(struct net_device *dev);
933static int is_100_up(struct net_device *dev);
934static int is_10_up(struct net_device *dev);
935static int is_anc_capable(struct net_device *dev);
936static int ping_media(struct net_device *dev, int msec);
937static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938static void de4x5_free_rx_buffs(struct net_device *dev);
939static void de4x5_free_tx_buffs(struct net_device *dev);
940static void de4x5_save_skbs(struct net_device *dev);
941static void de4x5_rst_desc_ring(struct net_device *dev);
942static void de4x5_cache_state(struct net_device *dev, int flag);
943static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946static void de4x5_setup_intr(struct net_device *dev);
947static void de4x5_init_connection(struct net_device *dev);
948static int de4x5_reset_phy(struct net_device *dev);
949static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951static int test_tp(struct net_device *dev, s32 msec);
952static int EISA_signature(char *name, struct device *device);
953static int PCI_signature(char *name, struct de4x5_private *lp);
954static void DevicePresent(struct net_device *dev, u_long iobase);
955static void enet_addr_rst(u_long aprom_addr);
956static int de4x5_bad_srom(struct de4x5_private *lp);
957static short srom_rd(u_long address, u_char offset);
958static void srom_latch(u_int command, u_long address);
959static void srom_command(u_int command, u_long address);
960static void srom_address(u_int command, u_long address, u_char offset);
961static short srom_data(u_int command, u_long address);
962
963static void sendto_srom(u_int command, u_long addr);
964static int getfrom_srom(u_long addr);
965static int srom_map_media(struct net_device *dev);
966static int srom_infoleaf_info(struct net_device *dev);
967static void srom_init(struct net_device *dev);
968static void srom_exec(struct net_device *dev, u_char *p);
969static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971static int mii_rdata(u_long ioaddr);
972static void mii_wdata(int data, int len, u_long ioaddr);
973static void mii_ta(u_long rw, u_long ioaddr);
974static int mii_swap(int data, int len);
975static void mii_address(u_char addr, u_long ioaddr);
976static void sendto_mii(u32 command, int data, u_long ioaddr);
977static int getfrom_mii(u32 command, u_long ioaddr);
978static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979static int mii_get_phy(struct net_device *dev);
980static void SetMulticastFilter(struct net_device *dev);
981static int get_hw_addr(struct net_device *dev);
982static void srom_repair(struct net_device *dev, int card);
983static int test_bad_enet(struct net_device *dev, int status);
984static int an_exception(struct de4x5_private *lp);
985static char *build_setup_frame(struct net_device *dev, int mode);
986static void disable_ast(struct net_device *dev);
987static long de4x5_switch_mac_port(struct net_device *dev);
988static int gep_rd(struct net_device *dev);
989static void gep_wr(s32 data, struct net_device *dev);
990static void yawn(struct net_device *dev, int state);
991static void de4x5_parse_params(struct net_device *dev);
992static void de4x5_dbg_open(struct net_device *dev);
993static void de4x5_dbg_mii(struct net_device *dev, int k);
994static void de4x5_dbg_media(struct net_device *dev);
995static void de4x5_dbg_srom(struct de4x5_srom *p);
996static void de4x5_dbg_rx(struct sk_buff *skb, int len);
997static int de4x5_strncmp(char *a, char *b, int n);
998static int dc21041_infoleaf(struct net_device *dev);
999static int dc21140_infoleaf(struct net_device *dev);
1000static int dc21142_infoleaf(struct net_device *dev);
1001static int dc21143_infoleaf(struct net_device *dev);
1002static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1003static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1004static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1009
1010
1011
1012
1013
1014
1015
1016static int io=0x0;
1017
1018module_param(io, int, 0);
1019module_param(de4x5_debug, int, 0);
1020module_param(dec_only, int, 0);
1021module_param(args, charp, 0);
1022
1023MODULE_PARM_DESC(io, "de4x5 I/O base address");
1024MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1025MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1026MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1027MODULE_LICENSE("GPL");
1028
1029
1030
1031
1032struct InfoLeaf {
1033 int chipset;
1034 int (*fn)(struct net_device *);
1035};
1036static struct InfoLeaf infoleaf_array[] = {
1037 {DC21041, dc21041_infoleaf},
1038 {DC21140, dc21140_infoleaf},
1039 {DC21142, dc21142_infoleaf},
1040 {DC21143, dc21143_infoleaf}
1041};
1042#define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1043
1044
1045
1046
1047static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1048 type0_infoblock,
1049 type1_infoblock,
1050 type2_infoblock,
1051 type3_infoblock,
1052 type4_infoblock,
1053 type5_infoblock,
1054 compact_infoblock
1055};
1056
1057#define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1058
1059
1060
1061
1062#define RESET_DE4X5 {\
1063 int i;\
1064 i=inl(DE4X5_BMR);\
1065 mdelay(1);\
1066 outl(i | BMR_SWR, DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i, DE4X5_BMR);\
1069 mdelay(1);\
1070 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1071 mdelay(1);\
1072}
1073
1074#define PHY_HARD_RESET {\
1075 outl(GEP_HRST, DE4X5_GEP); \
1076 mdelay(1); \
1077 outl(0x00, DE4X5_GEP);\
1078 mdelay(2); \
1079}
1080
1081
1082static int __devinit
1083de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1084{
1085 char name[DE4X5_NAME_LENGTH + 1];
1086 struct de4x5_private *lp = netdev_priv(dev);
1087 struct pci_dev *pdev = NULL;
1088 int i, status=0;
1089 DECLARE_MAC_BUF(mac);
1090
1091 gendev->driver_data = dev;
1092
1093
1094 if (lp->bus == EISA) {
1095 outb(WAKEUP, PCI_CFPM);
1096 } else {
1097 pdev = to_pci_dev (gendev);
1098 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1099 }
1100 mdelay(10);
1101
1102 RESET_DE4X5;
1103
1104 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1105 return -ENXIO;
1106 }
1107
1108
1109
1110
1111 lp->useSROM = false;
1112 if (lp->bus == PCI) {
1113 PCI_signature(name, lp);
1114 } else {
1115 EISA_signature(name, gendev);
1116 }
1117
1118 if (*name == '\0') {
1119 return -ENXIO;
1120 }
1121
1122 dev->base_addr = iobase;
1123 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1124
1125 status = get_hw_addr(dev);
1126 printk(", h/w address %s\n", print_mac(mac, dev->dev_addr));
1127
1128 if (status != 0) {
1129 printk(" which has an Ethernet PROM CRC error.\n");
1130 return -ENXIO;
1131 } else {
1132 lp->cache.gepc = GEP_INIT;
1133 lp->asBit = GEP_SLNK;
1134 lp->asPolarity = GEP_SLNK;
1135 lp->asBitValid = ~0;
1136 lp->timeout = -1;
1137 lp->gendev = gendev;
1138 spin_lock_init(&lp->lock);
1139 init_timer(&lp->timer);
1140 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1141 lp->timer.data = (unsigned long)dev;
1142 de4x5_parse_params(dev);
1143
1144
1145
1146
1147 lp->autosense = lp->params.autosense;
1148 if (lp->chipset != DC21140) {
1149 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1150 lp->params.autosense = TP;
1151 }
1152 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1153 lp->params.autosense = BNC;
1154 }
1155 }
1156 lp->fdx = lp->params.fdx;
1157 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1158
1159 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1160#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1161 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1162#endif
1163 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1164 &lp->dma_rings, GFP_ATOMIC);
1165 if (lp->rx_ring == NULL) {
1166 return -ENOMEM;
1167 }
1168
1169 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1170
1171
1172
1173
1174
1175#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1176 for (i=0; i<NUM_RX_DESC; i++) {
1177 lp->rx_ring[i].status = 0;
1178 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1179 lp->rx_ring[i].buf = 0;
1180 lp->rx_ring[i].next = 0;
1181 lp->rx_skb[i] = (struct sk_buff *) 1;
1182 }
1183
1184#else
1185 {
1186 dma_addr_t dma_rx_bufs;
1187
1188 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1189 * sizeof(struct de4x5_desc);
1190 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1191 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1192 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1193 for (i=0; i<NUM_RX_DESC; i++) {
1194 lp->rx_ring[i].status = 0;
1195 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1196 lp->rx_ring[i].buf =
1197 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1198 lp->rx_ring[i].next = 0;
1199 lp->rx_skb[i] = (struct sk_buff *) 1;
1200 }
1201
1202 }
1203#endif
1204
1205 barrier();
1206
1207 lp->rxRingSize = NUM_RX_DESC;
1208 lp->txRingSize = NUM_TX_DESC;
1209
1210
1211 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1212 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1213
1214
1215 outl(lp->dma_rings, DE4X5_RRBA);
1216 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1217 DE4X5_TRBA);
1218
1219
1220 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1221 lp->irq_en = IMR_NIM | IMR_AIM;
1222
1223
1224 create_packet(dev, lp->frame, sizeof(lp->frame));
1225
1226
1227 i = lp->cfrv & 0x000000fe;
1228 if ((lp->chipset == DC21140) && (i == 0x20)) {
1229 lp->rx_ovf = 1;
1230 }
1231
1232
1233 if (lp->useSROM) {
1234 lp->state = INITIALISED;
1235 if (srom_infoleaf_info(dev)) {
1236 dma_free_coherent (gendev, lp->dma_size,
1237 lp->rx_ring, lp->dma_rings);
1238 return -ENXIO;
1239 }
1240 srom_init(dev);
1241 }
1242
1243 lp->state = CLOSED;
1244
1245
1246
1247
1248 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1249 mii_get_phy(dev);
1250 }
1251
1252 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1253 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1254 }
1255
1256 if (de4x5_debug & DEBUG_VERSION) {
1257 printk(version);
1258 }
1259
1260
1261 SET_NETDEV_DEV(dev, gendev);
1262 dev->open = &de4x5_open;
1263 dev->hard_start_xmit = &de4x5_queue_pkt;
1264 dev->stop = &de4x5_close;
1265 dev->get_stats = &de4x5_get_stats;
1266 dev->set_multicast_list = &set_multicast_list;
1267 dev->do_ioctl = &de4x5_ioctl;
1268
1269 dev->mem_start = 0;
1270
1271
1272 if ((status = register_netdev (dev))) {
1273 dma_free_coherent (gendev, lp->dma_size,
1274 lp->rx_ring, lp->dma_rings);
1275 return status;
1276 }
1277
1278
1279 yawn(dev, SLEEP);
1280
1281 return status;
1282}
1283
1284
1285static int
1286de4x5_open(struct net_device *dev)
1287{
1288 struct de4x5_private *lp = netdev_priv(dev);
1289 u_long iobase = dev->base_addr;
1290 int i, status = 0;
1291 s32 omr;
1292
1293
1294 for (i=0; i<lp->rxRingSize; i++) {
1295 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1296 de4x5_free_rx_buffs(dev);
1297 return -EAGAIN;
1298 }
1299 }
1300
1301
1302
1303
1304 yawn(dev, WAKEUP);
1305
1306
1307
1308
1309 status = de4x5_init(dev);
1310 spin_lock_init(&lp->lock);
1311 lp->state = OPEN;
1312 de4x5_dbg_open(dev);
1313
1314 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1315 lp->adapter_name, dev)) {
1316 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1317 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1318 lp->adapter_name, dev)) {
1319 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1320 disable_ast(dev);
1321 de4x5_free_rx_buffs(dev);
1322 de4x5_free_tx_buffs(dev);
1323 yawn(dev, SLEEP);
1324 lp->state = CLOSED;
1325 return -EAGAIN;
1326 } else {
1327 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1328 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1329 }
1330 }
1331
1332 lp->interrupt = UNMASK_INTERRUPTS;
1333 dev->trans_start = jiffies;
1334
1335 START_DE4X5;
1336
1337 de4x5_setup_intr(dev);
1338
1339 if (de4x5_debug & DEBUG_OPEN) {
1340 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1341 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1342 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1343 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1344 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1345 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1346 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1347 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1348 }
1349
1350 return status;
1351}
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361static int
1362de4x5_init(struct net_device *dev)
1363{
1364
1365 netif_stop_queue(dev);
1366
1367 de4x5_sw_reset(dev);
1368
1369
1370 autoconf_media(dev);
1371
1372 return 0;
1373}
1374
1375static int
1376de4x5_sw_reset(struct net_device *dev)
1377{
1378 struct de4x5_private *lp = netdev_priv(dev);
1379 u_long iobase = dev->base_addr;
1380 int i, j, status = 0;
1381 s32 bmr, omr;
1382
1383
1384 if (!lp->useSROM) {
1385 if (lp->phy[lp->active].id != 0) {
1386 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1387 } else {
1388 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1389 }
1390 de4x5_switch_mac_port(dev);
1391 }
1392
1393
1394
1395
1396
1397
1398 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1399 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1400 outl(bmr, DE4X5_BMR);
1401
1402 omr = inl(DE4X5_OMR) & ~OMR_PR;
1403 if (lp->chipset == DC21140) {
1404 omr |= (OMR_SDP | OMR_SB);
1405 }
1406 lp->setup_f = PERFECT;
1407 outl(lp->dma_rings, DE4X5_RRBA);
1408 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1409 DE4X5_TRBA);
1410
1411 lp->rx_new = lp->rx_old = 0;
1412 lp->tx_new = lp->tx_old = 0;
1413
1414 for (i = 0; i < lp->rxRingSize; i++) {
1415 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1416 }
1417
1418 for (i = 0; i < lp->txRingSize; i++) {
1419 lp->tx_ring[i].status = cpu_to_le32(0);
1420 }
1421
1422 barrier();
1423
1424
1425 SetMulticastFilter(dev);
1426
1427 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1428 outl(omr|OMR_ST, DE4X5_OMR);
1429
1430
1431
1432 for (j=0, i=0;(i<500) && (j==0);i++) {
1433 mdelay(1);
1434 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1435 }
1436 outl(omr, DE4X5_OMR);
1437
1438 if (j == 0) {
1439 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1440 inl(DE4X5_STS));
1441 status = -EIO;
1442 }
1443
1444 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1445 lp->tx_old = lp->tx_new;
1446
1447 return status;
1448}
1449
1450
1451
1452
1453static int
1454de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1455{
1456 struct de4x5_private *lp = netdev_priv(dev);
1457 u_long iobase = dev->base_addr;
1458 int status = 0;
1459 u_long flags = 0;
1460
1461 netif_stop_queue(dev);
1462 if (!lp->tx_enable) {
1463 return -1;
1464 }
1465
1466
1467
1468
1469
1470
1471 spin_lock_irqsave(&lp->lock, flags);
1472 de4x5_tx(dev);
1473 spin_unlock_irqrestore(&lp->lock, flags);
1474
1475
1476 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1477 return -1;
1478
1479
1480 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1481 if (lp->interrupt) {
1482 de4x5_putb_cache(dev, skb);
1483 } else {
1484 de4x5_put_cache(dev, skb);
1485 }
1486 if (de4x5_debug & DEBUG_TX) {
1487 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1488 }
1489 } else if (skb->len > 0) {
1490
1491 if (lp->cache.skb && !lp->interrupt) {
1492 de4x5_put_cache(dev, skb);
1493 skb = de4x5_get_cache(dev);
1494 }
1495
1496 while (skb && !netif_queue_stopped(dev) &&
1497 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1498 spin_lock_irqsave(&lp->lock, flags);
1499 netif_stop_queue(dev);
1500 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1501 lp->stats.tx_bytes += skb->len;
1502 outl(POLL_DEMAND, DE4X5_TPD);
1503
1504 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1505 dev->trans_start = jiffies;
1506
1507 if (TX_BUFFS_AVAIL) {
1508 netif_start_queue(dev);
1509 }
1510 skb = de4x5_get_cache(dev);
1511 spin_unlock_irqrestore(&lp->lock, flags);
1512 }
1513 if (skb) de4x5_putb_cache(dev, skb);
1514 }
1515
1516 lp->cache.lock = 0;
1517
1518 return status;
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532static irqreturn_t
1533de4x5_interrupt(int irq, void *dev_id)
1534{
1535 struct net_device *dev = dev_id;
1536 struct de4x5_private *lp;
1537 s32 imr, omr, sts, limit;
1538 u_long iobase;
1539 unsigned int handled = 0;
1540
1541 lp = netdev_priv(dev);
1542 spin_lock(&lp->lock);
1543 iobase = dev->base_addr;
1544
1545 DISABLE_IRQs;
1546
1547 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1548 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1549
1550 synchronize_irq(dev->irq);
1551
1552 for (limit=0; limit<8; limit++) {
1553 sts = inl(DE4X5_STS);
1554 outl(sts, DE4X5_STS);
1555
1556 if (!(sts & lp->irq_mask)) break;
1557 handled = 1;
1558
1559 if (sts & (STS_RI | STS_RU))
1560 de4x5_rx(dev);
1561
1562 if (sts & (STS_TI | STS_TU))
1563 de4x5_tx(dev);
1564
1565 if (sts & STS_LNF) {
1566 lp->irq_mask &= ~IMR_LFM;
1567 }
1568
1569 if (sts & STS_UNF) {
1570 de4x5_txur(dev);
1571 }
1572
1573 if (sts & STS_SE) {
1574 STOP_DE4X5;
1575 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1576 dev->name, sts);
1577 spin_unlock(&lp->lock);
1578 return IRQ_HANDLED;
1579 }
1580 }
1581
1582
1583 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1584 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1585 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1586 }
1587 lp->cache.lock = 0;
1588 }
1589
1590 lp->interrupt = UNMASK_INTERRUPTS;
1591 ENABLE_IRQs;
1592 spin_unlock(&lp->lock);
1593
1594 return IRQ_RETVAL(handled);
1595}
1596
1597static int
1598de4x5_rx(struct net_device *dev)
1599{
1600 struct de4x5_private *lp = netdev_priv(dev);
1601 u_long iobase = dev->base_addr;
1602 int entry;
1603 s32 status;
1604
1605 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1606 entry=lp->rx_new) {
1607 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1608
1609 if (lp->rx_ovf) {
1610 if (inl(DE4X5_MFC) & MFC_FOCM) {
1611 de4x5_rx_ovfc(dev);
1612 break;
1613 }
1614 }
1615
1616 if (status & RD_FS) {
1617 lp->rx_old = entry;
1618 }
1619
1620 if (status & RD_LS) {
1621 if (lp->tx_enable) lp->linkOK++;
1622 if (status & RD_ES) {
1623 lp->stats.rx_errors++;
1624 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1625 if (status & RD_CE) lp->stats.rx_crc_errors++;
1626 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1627 if (status & RD_TL) lp->stats.rx_length_errors++;
1628 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1629 if (status & RD_CS) lp->pktStats.rx_collision++;
1630 if (status & RD_DB) lp->pktStats.rx_dribble++;
1631 if (status & RD_OF) lp->pktStats.rx_overflow++;
1632 } else {
1633 struct sk_buff *skb;
1634 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1635 >> 16) - 4;
1636
1637 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1638 printk("%s: Insufficient memory; nuking packet.\n",
1639 dev->name);
1640 lp->stats.rx_dropped++;
1641 } else {
1642 de4x5_dbg_rx(skb, pkt_len);
1643
1644
1645 skb->protocol=eth_type_trans(skb,dev);
1646 de4x5_local_stats(dev, skb->data, pkt_len);
1647 netif_rx(skb);
1648
1649
1650 dev->last_rx = jiffies;
1651 lp->stats.rx_packets++;
1652 lp->stats.rx_bytes += pkt_len;
1653 }
1654 }
1655
1656
1657 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1658 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1659 barrier();
1660 }
1661 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1662 barrier();
1663 }
1664
1665
1666
1667
1668 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1669 }
1670
1671 return 0;
1672}
1673
1674static inline void
1675de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1676{
1677 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1678 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1679 DMA_TO_DEVICE);
1680 if ((u_long) lp->tx_skb[entry] > 1)
1681 dev_kfree_skb_irq(lp->tx_skb[entry]);
1682 lp->tx_skb[entry] = NULL;
1683}
1684
1685
1686
1687
1688static int
1689de4x5_tx(struct net_device *dev)
1690{
1691 struct de4x5_private *lp = netdev_priv(dev);
1692 u_long iobase = dev->base_addr;
1693 int entry;
1694 s32 status;
1695
1696 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1697 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1698 if (status < 0) {
1699 break;
1700 } else if (status != 0x7fffffff) {
1701 if (status & TD_ES) {
1702 lp->stats.tx_errors++;
1703 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1704 if (status & TD_LC) lp->stats.tx_window_errors++;
1705 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1706 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1707 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1708
1709 if (TX_PKT_PENDING) {
1710 outl(POLL_DEMAND, DE4X5_TPD);
1711 }
1712 } else {
1713 lp->stats.tx_packets++;
1714 if (lp->tx_enable) lp->linkOK++;
1715 }
1716
1717 lp->stats.collisions += ((status & TD_EC) ? 16 :
1718 ((status & TD_CC) >> 3));
1719
1720
1721 if (lp->tx_skb[entry] != NULL)
1722 de4x5_free_tx_buff(lp, entry);
1723 }
1724
1725
1726 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1727 }
1728
1729
1730 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1731 if (lp->interrupt)
1732 netif_wake_queue(dev);
1733 else
1734 netif_start_queue(dev);
1735 }
1736
1737 return 0;
1738}
1739
1740static void
1741de4x5_ast(struct net_device *dev)
1742{
1743 struct de4x5_private *lp = netdev_priv(dev);
1744 int next_tick = DE4X5_AUTOSENSE_MS;
1745 int dt;
1746
1747 if (lp->useSROM)
1748 next_tick = srom_autoconf(dev);
1749 else if (lp->chipset == DC21140)
1750 next_tick = dc21140m_autoconf(dev);
1751 else if (lp->chipset == DC21041)
1752 next_tick = dc21041_autoconf(dev);
1753 else if (lp->chipset == DC21040)
1754 next_tick = dc21040_autoconf(dev);
1755 lp->linkOK = 0;
1756
1757 dt = (next_tick * HZ) / 1000;
1758
1759 if (!dt)
1760 dt = 1;
1761
1762 mod_timer(&lp->timer, jiffies + dt);
1763}
1764
1765static int
1766de4x5_txur(struct net_device *dev)
1767{
1768 struct de4x5_private *lp = netdev_priv(dev);
1769 u_long iobase = dev->base_addr;
1770 int omr;
1771
1772 omr = inl(DE4X5_OMR);
1773 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1774 omr &= ~(OMR_ST|OMR_SR);
1775 outl(omr, DE4X5_OMR);
1776 while (inl(DE4X5_STS) & STS_TS);
1777 if ((omr & OMR_TR) < OMR_TR) {
1778 omr += 0x4000;
1779 } else {
1780 omr |= OMR_SF;
1781 }
1782 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1783 }
1784
1785 return 0;
1786}
1787
1788static int
1789de4x5_rx_ovfc(struct net_device *dev)
1790{
1791 struct de4x5_private *lp = netdev_priv(dev);
1792 u_long iobase = dev->base_addr;
1793 int omr;
1794
1795 omr = inl(DE4X5_OMR);
1796 outl(omr & ~OMR_SR, DE4X5_OMR);
1797 while (inl(DE4X5_STS) & STS_RS);
1798
1799 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1800 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1801 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1802 }
1803
1804 outl(omr, DE4X5_OMR);
1805
1806 return 0;
1807}
1808
1809static int
1810de4x5_close(struct net_device *dev)
1811{
1812 struct de4x5_private *lp = netdev_priv(dev);
1813 u_long iobase = dev->base_addr;
1814 s32 imr, omr;
1815
1816 disable_ast(dev);
1817
1818 netif_stop_queue(dev);
1819
1820 if (de4x5_debug & DEBUG_CLOSE) {
1821 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1822 dev->name, inl(DE4X5_STS));
1823 }
1824
1825
1826
1827
1828 DISABLE_IRQs;
1829 STOP_DE4X5;
1830
1831
1832 free_irq(dev->irq, dev);
1833 lp->state = CLOSED;
1834
1835
1836 de4x5_free_rx_buffs(dev);
1837 de4x5_free_tx_buffs(dev);
1838
1839
1840 yawn(dev, SLEEP);
1841
1842 return 0;
1843}
1844
1845static struct net_device_stats *
1846de4x5_get_stats(struct net_device *dev)
1847{
1848 struct de4x5_private *lp = netdev_priv(dev);
1849 u_long iobase = dev->base_addr;
1850
1851 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1852
1853 return &lp->stats;
1854}
1855
1856static void
1857de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1858{
1859 struct de4x5_private *lp = netdev_priv(dev);
1860 int i;
1861
1862 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1863 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1864 lp->pktStats.bins[i]++;
1865 i = DE4X5_PKT_STAT_SZ;
1866 }
1867 }
1868 if (buf[0] & 0x01) {
1869 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1870 lp->pktStats.broadcast++;
1871 } else {
1872 lp->pktStats.multicast++;
1873 }
1874 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1875 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1876 lp->pktStats.unicast++;
1877 }
1878
1879 lp->pktStats.bins[0]++;
1880 if (lp->pktStats.bins[0] == 0) {
1881 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1882 }
1883
1884 return;
1885}
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895static void
1896load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1897{
1898 struct de4x5_private *lp = netdev_priv(dev);
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1901
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1905 lp->tx_skb[lp->tx_new] = skb;
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1907 barrier();
1908
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1910 barrier();
1911}
1912
1913
1914
1915
1916static void
1917set_multicast_list(struct net_device *dev)
1918{
1919 struct de4x5_private *lp = netdev_priv(dev);
1920 u_long iobase = dev->base_addr;
1921
1922
1923 if (lp->state == OPEN) {
1924 if (dev->flags & IFF_PROMISC) {
1925 u32 omr;
1926 omr = inl(DE4X5_OMR);
1927 omr |= OMR_PR;
1928 outl(omr, DE4X5_OMR);
1929 } else {
1930 SetMulticastFilter(dev);
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1932 SETUP_FRAME_LEN, (struct sk_buff *)1);
1933
1934 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1935 outl(POLL_DEMAND, DE4X5_TPD);
1936 dev->trans_start = jiffies;
1937 }
1938 }
1939}
1940
1941
1942
1943
1944
1945
1946static void
1947SetMulticastFilter(struct net_device *dev)
1948{
1949 struct de4x5_private *lp = netdev_priv(dev);
1950 struct dev_mc_list *dmi=dev->mc_list;
1951 u_long iobase = dev->base_addr;
1952 int i, j, bit, byte;
1953 u16 hashcode;
1954 u32 omr, crc;
1955 char *pa;
1956 unsigned char *addrs;
1957
1958 omr = inl(DE4X5_OMR);
1959 omr &= ~(OMR_PR | OMR_PM);
1960 pa = build_setup_frame(dev, ALL);
1961
1962 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1963 omr |= OMR_PM;
1964 } else if (lp->setup_f == HASH_PERF) {
1965 for (i=0;i<dev->mc_count;i++) {
1966 addrs=dmi->dmi_addr;
1967 dmi=dmi->next;
1968 if ((*addrs & 0x01) == 1) {
1969 crc = ether_crc_le(ETH_ALEN, addrs);
1970 hashcode = crc & HASH_BITS;
1971
1972 byte = hashcode >> 3;
1973 bit = 1 << (hashcode & 0x07);
1974
1975 byte <<= 1;
1976 if (byte & 0x02) {
1977 byte -= 1;
1978 }
1979 lp->setup_frame[byte] |= bit;
1980 }
1981 }
1982 } else {
1983 for (j=0; j<dev->mc_count; j++) {
1984 addrs=dmi->dmi_addr;
1985 dmi=dmi->next;
1986 for (i=0; i<ETH_ALEN; i++) {
1987 *(pa + (i&1)) = *addrs++;
1988 if (i & 0x01) pa += 4;
1989 }
1990 }
1991 }
1992 outl(omr, DE4X5_OMR);
1993
1994 return;
1995}
1996
1997#ifdef CONFIG_EISA
1998
1999static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2000
2001static int __init de4x5_eisa_probe (struct device *gendev)
2002{
2003 struct eisa_device *edev;
2004 u_long iobase;
2005 u_char irq, regval;
2006 u_short vendor;
2007 u32 cfid;
2008 int status, device;
2009 struct net_device *dev;
2010 struct de4x5_private *lp;
2011
2012 edev = to_eisa_device (gendev);
2013 iobase = edev->base_addr;
2014
2015 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2016 return -EBUSY;
2017
2018 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2019 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2020 status = -EBUSY;
2021 goto release_reg_1;
2022 }
2023
2024 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2025 status = -ENOMEM;
2026 goto release_reg_2;
2027 }
2028 lp = netdev_priv(dev);
2029
2030 cfid = (u32) inl(PCI_CFID);
2031 lp->cfrv = (u_short) inl(PCI_CFRV);
2032 device = (cfid >> 8) & 0x00ffff00;
2033 vendor = (u_short) cfid;
2034
2035
2036 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2037#ifdef CONFIG_ALPHA
2038
2039
2040
2041
2042
2043
2044 outb (ER1_IAM | 1, EISA_REG1);
2045 mdelay (1);
2046
2047
2048 outb (ER1_IAM, EISA_REG1);
2049 mdelay (1);
2050
2051
2052 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2053
2054
2055 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2056#endif
2057 irq = de4x5_irq[(regval >> 1) & 0x03];
2058
2059 if (is_DC2114x) {
2060 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2061 }
2062 lp->chipset = device;
2063 lp->bus = EISA;
2064
2065
2066 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2067 outl(0x00006000, PCI_CFLT);
2068 outl(iobase, PCI_CBIO);
2069
2070 DevicePresent(dev, EISA_APROM);
2071
2072 dev->irq = irq;
2073
2074 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2075 return 0;
2076 }
2077
2078 free_netdev (dev);
2079 release_reg_2:
2080 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2081 release_reg_1:
2082 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2083
2084 return status;
2085}
2086
2087static int __devexit de4x5_eisa_remove (struct device *device)
2088{
2089 struct net_device *dev;
2090 u_long iobase;
2091
2092 dev = device->driver_data;
2093 iobase = dev->base_addr;
2094
2095 unregister_netdev (dev);
2096 free_netdev (dev);
2097 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2098 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2099
2100 return 0;
2101}
2102
2103static struct eisa_device_id de4x5_eisa_ids[] = {
2104 { "DEC4250", 0 },
2105 { "" }
2106};
2107MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2108
2109static struct eisa_driver de4x5_eisa_driver = {
2110 .id_table = de4x5_eisa_ids,
2111 .driver = {
2112 .name = "de4x5",
2113 .probe = de4x5_eisa_probe,
2114 .remove = __devexit_p (de4x5_eisa_remove),
2115 }
2116};
2117MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2118#endif
2119
2120#ifdef CONFIG_PCI
2121
2122
2123
2124
2125
2126
2127
2128static void __devinit
2129srom_search(struct net_device *dev, struct pci_dev *pdev)
2130{
2131 u_char pb;
2132 u_short vendor, status;
2133 u_int irq = 0, device;
2134 u_long iobase = 0;
2135 int i, j;
2136 struct de4x5_private *lp = netdev_priv(dev);
2137 struct list_head *walk;
2138
2139 list_for_each(walk, &pdev->bus_list) {
2140 struct pci_dev *this_dev = pci_dev_b(walk);
2141
2142
2143 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2144
2145 vendor = this_dev->vendor;
2146 device = this_dev->device << 8;
2147 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2148
2149
2150 pb = this_dev->bus->number;
2151
2152
2153 lp->device = PCI_SLOT(this_dev->devfn);
2154 lp->bus_num = pb;
2155
2156
2157 if (is_DC2114x) {
2158 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2159 ? DC21142 : DC21143);
2160 }
2161 lp->chipset = device;
2162
2163
2164 iobase = pci_resource_start(this_dev, 0);
2165
2166
2167 irq = this_dev->irq;
2168 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2169
2170
2171 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2172 if (!(status & PCI_COMMAND_IO)) continue;
2173
2174
2175 DevicePresent(dev, DE4X5_APROM);
2176 for (j=0, i=0; i<ETH_ALEN; i++) {
2177 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2178 }
2179 if (j != 0 && j != 6 * 0xff) {
2180 last.chipset = device;
2181 last.bus = pb;
2182 last.irq = irq;
2183 for (i=0; i<ETH_ALEN; i++) {
2184 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2185 }
2186 return;
2187 }
2188 }
2189
2190 return;
2191}
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2210 const struct pci_device_id *ent)
2211{
2212 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2213 u_short vendor, status;
2214 u_int irq = 0, device;
2215 u_long iobase = 0;
2216 int error;
2217 struct net_device *dev;
2218 struct de4x5_private *lp;
2219
2220 dev_num = PCI_SLOT(pdev->devfn);
2221 pb = pdev->bus->number;
2222
2223 if (io) {
2224 pbus = (u_short)(io >> 8);
2225 dnum = (u_short)(io & 0xff);
2226 if ((pbus != pb) || (dnum != dev_num))
2227 return -ENODEV;
2228 }
2229
2230 vendor = pdev->vendor;
2231 device = pdev->device << 8;
2232 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2233 return -ENODEV;
2234
2235
2236 if ((error = pci_enable_device (pdev)))
2237 return error;
2238
2239 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2240 error = -ENOMEM;
2241 goto disable_dev;
2242 }
2243
2244 lp = netdev_priv(dev);
2245 lp->bus = PCI;
2246 lp->bus_num = 0;
2247
2248
2249 if (lp->bus_num != pb) {
2250 lp->bus_num = pb;
2251 srom_search(dev, pdev);
2252 }
2253
2254
2255 lp->cfrv = pdev->revision;
2256
2257
2258 lp->device = dev_num;
2259 lp->bus_num = pb;
2260
2261
2262 if (is_DC2114x) {
2263 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2264 }
2265 lp->chipset = device;
2266
2267
2268 iobase = pci_resource_start(pdev, 0);
2269
2270
2271 irq = pdev->irq;
2272 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2273 error = -ENODEV;
2274 goto free_dev;
2275 }
2276
2277
2278 pci_read_config_word(pdev, PCI_COMMAND, &status);
2279#ifdef __powerpc__
2280 if (!(status & PCI_COMMAND_IO)) {
2281 status |= PCI_COMMAND_IO;
2282 pci_write_config_word(pdev, PCI_COMMAND, status);
2283 pci_read_config_word(pdev, PCI_COMMAND, &status);
2284 }
2285#endif
2286 if (!(status & PCI_COMMAND_IO)) {
2287 error = -ENODEV;
2288 goto free_dev;
2289 }
2290
2291 if (!(status & PCI_COMMAND_MASTER)) {
2292 status |= PCI_COMMAND_MASTER;
2293 pci_write_config_word(pdev, PCI_COMMAND, status);
2294 pci_read_config_word(pdev, PCI_COMMAND, &status);
2295 }
2296 if (!(status & PCI_COMMAND_MASTER)) {
2297 error = -ENODEV;
2298 goto free_dev;
2299 }
2300
2301
2302 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2303 if (timer < 0x60) {
2304 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2305 }
2306
2307 DevicePresent(dev, DE4X5_APROM);
2308
2309 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2310 error = -EBUSY;
2311 goto free_dev;
2312 }
2313
2314 dev->irq = irq;
2315
2316 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2317 goto release;
2318 }
2319
2320 return 0;
2321
2322 release:
2323 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2324 free_dev:
2325 free_netdev (dev);
2326 disable_dev:
2327 pci_disable_device (pdev);
2328 return error;
2329}
2330
2331static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2332{
2333 struct net_device *dev;
2334 u_long iobase;
2335
2336 dev = pdev->dev.driver_data;
2337 iobase = dev->base_addr;
2338
2339 unregister_netdev (dev);
2340 free_netdev (dev);
2341 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2342 pci_disable_device (pdev);
2343}
2344
2345static struct pci_device_id de4x5_pci_tbl[] = {
2346 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2348 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2350 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2352 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2354 { },
2355};
2356
2357static struct pci_driver de4x5_pci_driver = {
2358 .name = "de4x5",
2359 .id_table = de4x5_pci_tbl,
2360 .probe = de4x5_pci_probe,
2361 .remove = __devexit_p (de4x5_pci_remove),
2362};
2363
2364#endif
2365
2366
2367
2368
2369
2370
2371
2372
2373static int
2374autoconf_media(struct net_device *dev)
2375{
2376 struct de4x5_private *lp = netdev_priv(dev);
2377 u_long iobase = dev->base_addr;
2378
2379 disable_ast(dev);
2380
2381 lp->c_media = AUTO;
2382 inl(DE4X5_MFC);
2383 lp->media = INIT;
2384 lp->tcount = 0;
2385
2386 de4x5_ast(dev);
2387
2388 return lp->media;
2389}
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403static int
2404dc21040_autoconf(struct net_device *dev)
2405{
2406 struct de4x5_private *lp = netdev_priv(dev);
2407 u_long iobase = dev->base_addr;
2408 int next_tick = DE4X5_AUTOSENSE_MS;
2409 s32 imr;
2410
2411 switch (lp->media) {
2412 case INIT:
2413 DISABLE_IRQs;
2414 lp->tx_enable = false;
2415 lp->timeout = -1;
2416 de4x5_save_skbs(dev);
2417 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2418 lp->media = TP;
2419 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2420 lp->media = BNC_AUI;
2421 } else if (lp->autosense == EXT_SIA) {
2422 lp->media = EXT_SIA;
2423 } else {
2424 lp->media = NC;
2425 }
2426 lp->local_state = 0;
2427 next_tick = dc21040_autoconf(dev);
2428 break;
2429
2430 case TP:
2431 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2432 TP_SUSPECT, test_tp);
2433 break;
2434
2435 case TP_SUSPECT:
2436 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2437 break;
2438
2439 case BNC:
2440 case AUI:
2441 case BNC_AUI:
2442 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2443 BNC_AUI_SUSPECT, ping_media);
2444 break;
2445
2446 case BNC_AUI_SUSPECT:
2447 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2448 break;
2449
2450 case EXT_SIA:
2451 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2452 NC, EXT_SIA_SUSPECT, ping_media);
2453 break;
2454
2455 case EXT_SIA_SUSPECT:
2456 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2457 break;
2458
2459 case NC:
2460
2461 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2462 if (lp->media != lp->c_media) {
2463 de4x5_dbg_media(dev);
2464 lp->c_media = lp->media;
2465 }
2466 lp->media = INIT;
2467 lp->tx_enable = false;
2468 break;
2469 }
2470
2471 return next_tick;
2472}
2473
2474static int
2475dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2476 int next_state, int suspect_state,
2477 int (*fn)(struct net_device *, int))
2478{
2479 struct de4x5_private *lp = netdev_priv(dev);
2480 int next_tick = DE4X5_AUTOSENSE_MS;
2481 int linkBad;
2482
2483 switch (lp->local_state) {
2484 case 0:
2485 reset_init_sia(dev, csr13, csr14, csr15);
2486 lp->local_state++;
2487 next_tick = 500;
2488 break;
2489
2490 case 1:
2491 if (!lp->tx_enable) {
2492 linkBad = fn(dev, timeout);
2493 if (linkBad < 0) {
2494 next_tick = linkBad & ~TIMER_CB;
2495 } else {
2496 if (linkBad && (lp->autosense == AUTO)) {
2497 lp->local_state = 0;
2498 lp->media = next_state;
2499 } else {
2500 de4x5_init_connection(dev);
2501 }
2502 }
2503 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2504 lp->media = suspect_state;
2505 next_tick = 3000;
2506 }
2507 break;
2508 }
2509
2510 return next_tick;
2511}
2512
2513static int
2514de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2515 int (*fn)(struct net_device *, int),
2516 int (*asfn)(struct net_device *))
2517{
2518 struct de4x5_private *lp = netdev_priv(dev);
2519 int next_tick = DE4X5_AUTOSENSE_MS;
2520 int linkBad;
2521
2522 switch (lp->local_state) {
2523 case 1:
2524 if (lp->linkOK) {
2525 lp->media = prev_state;
2526 } else {
2527 lp->local_state++;
2528 next_tick = asfn(dev);
2529 }
2530 break;
2531
2532 case 2:
2533 linkBad = fn(dev, timeout);
2534 if (linkBad < 0) {
2535 next_tick = linkBad & ~TIMER_CB;
2536 } else if (!linkBad) {
2537 lp->local_state--;
2538 lp->media = prev_state;
2539 } else {
2540 lp->media = INIT;
2541 lp->tcount++;
2542 }
2543 }
2544
2545 return next_tick;
2546}
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557static int
2558dc21041_autoconf(struct net_device *dev)
2559{
2560 struct de4x5_private *lp = netdev_priv(dev);
2561 u_long iobase = dev->base_addr;
2562 s32 sts, irqs, irq_mask, imr, omr;
2563 int next_tick = DE4X5_AUTOSENSE_MS;
2564
2565 switch (lp->media) {
2566 case INIT:
2567 DISABLE_IRQs;
2568 lp->tx_enable = false;
2569 lp->timeout = -1;
2570 de4x5_save_skbs(dev);
2571 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2572 lp->media = TP;
2573 } else if (lp->autosense == TP) {
2574 lp->media = TP;
2575 } else if (lp->autosense == BNC) {
2576 lp->media = BNC;
2577 } else if (lp->autosense == AUI) {
2578 lp->media = AUI;
2579 } else {
2580 lp->media = NC;
2581 }
2582 lp->local_state = 0;
2583 next_tick = dc21041_autoconf(dev);
2584 break;
2585
2586 case TP_NW:
2587 if (lp->timeout < 0) {
2588 omr = inl(DE4X5_OMR);
2589 outl(omr | OMR_FDX, DE4X5_OMR);
2590 }
2591 irqs = STS_LNF | STS_LNP;
2592 irq_mask = IMR_LFM | IMR_LPM;
2593 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2594 if (sts < 0) {
2595 next_tick = sts & ~TIMER_CB;
2596 } else {
2597 if (sts & STS_LNP) {
2598 lp->media = ANS;
2599 } else {
2600 lp->media = AUI;
2601 }
2602 next_tick = dc21041_autoconf(dev);
2603 }
2604 break;
2605
2606 case ANS:
2607 if (!lp->tx_enable) {
2608 irqs = STS_LNP;
2609 irq_mask = IMR_LPM;
2610 sts = test_ans(dev, irqs, irq_mask, 3000);
2611 if (sts < 0) {
2612 next_tick = sts & ~TIMER_CB;
2613 } else {
2614 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2615 lp->media = TP;
2616 next_tick = dc21041_autoconf(dev);
2617 } else {
2618 lp->local_state = 1;
2619 de4x5_init_connection(dev);
2620 }
2621 }
2622 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2623 lp->media = ANS_SUSPECT;
2624 next_tick = 3000;
2625 }
2626 break;
2627
2628 case ANS_SUSPECT:
2629 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2630 break;
2631
2632 case TP:
2633 if (!lp->tx_enable) {
2634 if (lp->timeout < 0) {
2635 omr = inl(DE4X5_OMR);
2636 outl(omr & ~OMR_FDX, DE4X5_OMR);
2637 }
2638 irqs = STS_LNF | STS_LNP;
2639 irq_mask = IMR_LFM | IMR_LPM;
2640 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2641 if (sts < 0) {
2642 next_tick = sts & ~TIMER_CB;
2643 } else {
2644 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2645 if (inl(DE4X5_SISR) & SISR_NRA) {
2646 lp->media = AUI;
2647 } else {
2648 lp->media = BNC;
2649 }
2650 next_tick = dc21041_autoconf(dev);
2651 } else {
2652 lp->local_state = 1;
2653 de4x5_init_connection(dev);
2654 }
2655 }
2656 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2657 lp->media = TP_SUSPECT;
2658 next_tick = 3000;
2659 }
2660 break;
2661
2662 case TP_SUSPECT:
2663 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2664 break;
2665
2666 case AUI:
2667 if (!lp->tx_enable) {
2668 if (lp->timeout < 0) {
2669 omr = inl(DE4X5_OMR);
2670 outl(omr & ~OMR_FDX, DE4X5_OMR);
2671 }
2672 irqs = 0;
2673 irq_mask = 0;
2674 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2675 if (sts < 0) {
2676 next_tick = sts & ~TIMER_CB;
2677 } else {
2678 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2679 lp->media = BNC;
2680 next_tick = dc21041_autoconf(dev);
2681 } else {
2682 lp->local_state = 1;
2683 de4x5_init_connection(dev);
2684 }
2685 }
2686 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2687 lp->media = AUI_SUSPECT;
2688 next_tick = 3000;
2689 }
2690 break;
2691
2692 case AUI_SUSPECT:
2693 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2694 break;
2695
2696 case BNC:
2697 switch (lp->local_state) {
2698 case 0:
2699 if (lp->timeout < 0) {
2700 omr = inl(DE4X5_OMR);
2701 outl(omr & ~OMR_FDX, DE4X5_OMR);
2702 }
2703 irqs = 0;
2704 irq_mask = 0;
2705 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2706 if (sts < 0) {
2707 next_tick = sts & ~TIMER_CB;
2708 } else {
2709 lp->local_state++;
2710 next_tick = dc21041_autoconf(dev);
2711 }
2712 break;
2713
2714 case 1:
2715 if (!lp->tx_enable) {
2716 if ((sts = ping_media(dev, 3000)) < 0) {
2717 next_tick = sts & ~TIMER_CB;
2718 } else {
2719 if (sts) {
2720 lp->local_state = 0;
2721 lp->media = NC;
2722 } else {
2723 de4x5_init_connection(dev);
2724 }
2725 }
2726 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2727 lp->media = BNC_SUSPECT;
2728 next_tick = 3000;
2729 }
2730 break;
2731 }
2732 break;
2733
2734 case BNC_SUSPECT:
2735 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2736 break;
2737
2738 case NC:
2739 omr = inl(DE4X5_OMR);
2740 outl(omr | OMR_FDX, DE4X5_OMR);
2741 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);
2742 if (lp->media != lp->c_media) {
2743 de4x5_dbg_media(dev);
2744 lp->c_media = lp->media;
2745 }
2746 lp->media = INIT;
2747 lp->tx_enable = false;
2748 break;
2749 }
2750
2751 return next_tick;
2752}
2753
2754
2755
2756
2757
2758
2759static int
2760dc21140m_autoconf(struct net_device *dev)
2761{
2762 struct de4x5_private *lp = netdev_priv(dev);
2763 int ana, anlpa, cap, cr, slnk, sr;
2764 int next_tick = DE4X5_AUTOSENSE_MS;
2765 u_long imr, omr, iobase = dev->base_addr;
2766
2767 switch(lp->media) {
2768 case INIT:
2769 if (lp->timeout < 0) {
2770 DISABLE_IRQs;
2771 lp->tx_enable = false;
2772 lp->linkOK = 0;
2773 de4x5_save_skbs(dev);
2774 }
2775 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2776 next_tick &= ~TIMER_CB;
2777 } else {
2778 if (lp->useSROM) {
2779 if (srom_map_media(dev) < 0) {
2780 lp->tcount++;
2781 return next_tick;
2782 }
2783 srom_exec(dev, lp->phy[lp->active].gep);
2784 if (lp->infoblock_media == ANS) {
2785 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2786 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2787 }
2788 } else {
2789 lp->tmp = MII_SR_ASSC;
2790 SET_10Mb;
2791 if (lp->autosense == _100Mb) {
2792 lp->media = _100Mb;
2793 } else if (lp->autosense == _10Mb) {
2794 lp->media = _10Mb;
2795 } else if ((lp->autosense == AUTO) &&
2796 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2797 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2798 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2799 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2800 lp->media = ANS;
2801 } else if (lp->autosense == AUTO) {
2802 lp->media = SPD_DET;
2803 } else if (is_spd_100(dev) && is_100_up(dev)) {
2804 lp->media = _100Mb;
2805 } else {
2806 lp->media = NC;
2807 }
2808 }
2809 lp->local_state = 0;
2810 next_tick = dc21140m_autoconf(dev);
2811 }
2812 break;
2813
2814 case ANS:
2815 switch (lp->local_state) {
2816 case 0:
2817 if (lp->timeout < 0) {
2818 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2819 }
2820 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2821 if (cr < 0) {
2822 next_tick = cr & ~TIMER_CB;
2823 } else {
2824 if (cr) {
2825 lp->local_state = 0;
2826 lp->media = SPD_DET;
2827 } else {
2828 lp->local_state++;
2829 }
2830 next_tick = dc21140m_autoconf(dev);
2831 }
2832 break;
2833
2834 case 1:
2835 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2836 next_tick = sr & ~TIMER_CB;
2837 } else {
2838 lp->media = SPD_DET;
2839 lp->local_state = 0;
2840 if (sr) {
2841 lp->tmp = MII_SR_ASSC;
2842 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2843 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2844 if (!(anlpa & MII_ANLPA_RF) &&
2845 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2846 if (cap & MII_ANA_100M) {
2847 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2848 lp->media = _100Mb;
2849 } else if (cap & MII_ANA_10M) {
2850 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2851
2852 lp->media = _10Mb;
2853 }
2854 }
2855 }
2856 next_tick = dc21140m_autoconf(dev);
2857 }
2858 break;
2859 }
2860 break;
2861
2862 case SPD_DET:
2863 if (lp->timeout < 0) {
2864 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2865 (~gep_rd(dev) & GEP_LNP));
2866 SET_100Mb_PDET;
2867 }
2868 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2869 next_tick = slnk & ~TIMER_CB;
2870 } else {
2871 if (is_spd_100(dev) && is_100_up(dev)) {
2872 lp->media = _100Mb;
2873 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2874 lp->media = _10Mb;
2875 } else {
2876 lp->media = NC;
2877 }
2878 next_tick = dc21140m_autoconf(dev);
2879 }
2880 break;
2881
2882 case _100Mb:
2883 next_tick = 3000;
2884 if (!lp->tx_enable) {
2885 SET_100Mb;
2886 de4x5_init_connection(dev);
2887 } else {
2888 if (!lp->linkOK && (lp->autosense == AUTO)) {
2889 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2890 lp->media = INIT;
2891 lp->tcount++;
2892 next_tick = DE4X5_AUTOSENSE_MS;
2893 }
2894 }
2895 }
2896 break;
2897
2898 case BNC:
2899 case AUI:
2900 case _10Mb:
2901 next_tick = 3000;
2902 if (!lp->tx_enable) {
2903 SET_10Mb;
2904 de4x5_init_connection(dev);
2905 } else {
2906 if (!lp->linkOK && (lp->autosense == AUTO)) {
2907 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2908 lp->media = INIT;
2909 lp->tcount++;
2910 next_tick = DE4X5_AUTOSENSE_MS;
2911 }
2912 }
2913 }
2914 break;
2915
2916 case NC:
2917 if (lp->media != lp->c_media) {
2918 de4x5_dbg_media(dev);
2919 lp->c_media = lp->media;
2920 }
2921 lp->media = INIT;
2922 lp->tx_enable = false;
2923 break;
2924 }
2925
2926 return next_tick;
2927}
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943static int
2944dc2114x_autoconf(struct net_device *dev)
2945{
2946 struct de4x5_private *lp = netdev_priv(dev);
2947 u_long iobase = dev->base_addr;
2948 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2949 int next_tick = DE4X5_AUTOSENSE_MS;
2950
2951 switch (lp->media) {
2952 case INIT:
2953 if (lp->timeout < 0) {
2954 DISABLE_IRQs;
2955 lp->tx_enable = false;
2956 lp->linkOK = 0;
2957 lp->timeout = -1;
2958 de4x5_save_skbs(dev);
2959 if (lp->params.autosense & ~AUTO) {
2960 srom_map_media(dev);
2961 if (lp->media != lp->params.autosense) {
2962 lp->tcount++;
2963 lp->media = INIT;
2964 return next_tick;
2965 }
2966 lp->media = INIT;
2967 }
2968 }
2969 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2970 next_tick &= ~TIMER_CB;
2971 } else {
2972 if (lp->autosense == _100Mb) {
2973 lp->media = _100Mb;
2974 } else if (lp->autosense == _10Mb) {
2975 lp->media = _10Mb;
2976 } else if (lp->autosense == TP) {
2977 lp->media = TP;
2978 } else if (lp->autosense == BNC) {
2979 lp->media = BNC;
2980 } else if (lp->autosense == AUI) {
2981 lp->media = AUI;
2982 } else {
2983 lp->media = SPD_DET;
2984 if ((lp->infoblock_media == ANS) &&
2985 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2986 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2987 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2988 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2989 lp->media = ANS;
2990 }
2991 }
2992 lp->local_state = 0;
2993 next_tick = dc2114x_autoconf(dev);
2994 }
2995 break;
2996
2997 case ANS:
2998 switch (lp->local_state) {
2999 case 0:
3000 if (lp->timeout < 0) {
3001 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3002 }
3003 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
3004 if (cr < 0) {
3005 next_tick = cr & ~TIMER_CB;
3006 } else {
3007 if (cr) {
3008 lp->local_state = 0;
3009 lp->media = SPD_DET;
3010 } else {
3011 lp->local_state++;
3012 }
3013 next_tick = dc2114x_autoconf(dev);
3014 }
3015 break;
3016
3017 case 1:
3018 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3019 if (sr < 0) {
3020 next_tick = sr & ~TIMER_CB;
3021 } else {
3022 lp->media = SPD_DET;
3023 lp->local_state = 0;
3024 if (sr) {
3025 lp->tmp = MII_SR_ASSC;
3026 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3027 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3028 if (!(anlpa & MII_ANLPA_RF) &&
3029 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3030 if (cap & MII_ANA_100M) {
3031 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3032 lp->media = _100Mb;
3033 } else if (cap & MII_ANA_10M) {
3034 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3035 lp->media = _10Mb;
3036 }
3037 }
3038 }
3039 next_tick = dc2114x_autoconf(dev);
3040 }
3041 break;
3042 }
3043 break;
3044
3045 case AUI:
3046 if (!lp->tx_enable) {
3047 if (lp->timeout < 0) {
3048 omr = inl(DE4X5_OMR);
3049 outl(omr & ~OMR_FDX, DE4X5_OMR);
3050 }
3051 irqs = 0;
3052 irq_mask = 0;
3053 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3054 if (sts < 0) {
3055 next_tick = sts & ~TIMER_CB;
3056 } else {
3057 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3058 lp->media = BNC;
3059 next_tick = dc2114x_autoconf(dev);
3060 } else {
3061 lp->local_state = 1;
3062 de4x5_init_connection(dev);
3063 }
3064 }
3065 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3066 lp->media = AUI_SUSPECT;
3067 next_tick = 3000;
3068 }
3069 break;
3070
3071 case AUI_SUSPECT:
3072 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3073 break;
3074
3075 case BNC:
3076 switch (lp->local_state) {
3077 case 0:
3078 if (lp->timeout < 0) {
3079 omr = inl(DE4X5_OMR);
3080 outl(omr & ~OMR_FDX, DE4X5_OMR);
3081 }
3082 irqs = 0;
3083 irq_mask = 0;
3084 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3085 if (sts < 0) {
3086 next_tick = sts & ~TIMER_CB;
3087 } else {
3088 lp->local_state++;
3089 next_tick = dc2114x_autoconf(dev);
3090 }
3091 break;
3092
3093 case 1:
3094 if (!lp->tx_enable) {
3095 if ((sts = ping_media(dev, 3000)) < 0) {
3096 next_tick = sts & ~TIMER_CB;
3097 } else {
3098 if (sts) {
3099 lp->local_state = 0;
3100 lp->tcount++;
3101 lp->media = INIT;
3102 } else {
3103 de4x5_init_connection(dev);
3104 }
3105 }
3106 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3107 lp->media = BNC_SUSPECT;
3108 next_tick = 3000;
3109 }
3110 break;
3111 }
3112 break;
3113
3114 case BNC_SUSPECT:
3115 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3116 break;
3117
3118 case SPD_DET:
3119 if (srom_map_media(dev) < 0) {
3120 lp->tcount++;
3121 lp->media = INIT;
3122 return next_tick;
3123 }
3124 if (lp->media == _100Mb) {
3125 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3126 lp->media = SPD_DET;
3127 return (slnk & ~TIMER_CB);
3128 }
3129 } else {
3130 if (wait_for_link(dev) < 0) {
3131 lp->media = SPD_DET;
3132 return PDET_LINK_WAIT;
3133 }
3134 }
3135 if (lp->media == ANS) {
3136 if (is_spd_100(dev)) {
3137 lp->media = _100Mb;
3138 } else {
3139 lp->media = _10Mb;
3140 }
3141 next_tick = dc2114x_autoconf(dev);
3142 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3143 (((lp->media == _10Mb) || (lp->media == TP) ||
3144 (lp->media == BNC) || (lp->media == AUI)) &&
3145 is_10_up(dev))) {
3146 next_tick = dc2114x_autoconf(dev);
3147 } else {
3148 lp->tcount++;
3149 lp->media = INIT;
3150 }
3151 break;
3152
3153 case _10Mb:
3154 next_tick = 3000;
3155 if (!lp->tx_enable) {
3156 SET_10Mb;
3157 de4x5_init_connection(dev);
3158 } else {
3159 if (!lp->linkOK && (lp->autosense == AUTO)) {
3160 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3161 lp->media = INIT;
3162 lp->tcount++;
3163 next_tick = DE4X5_AUTOSENSE_MS;
3164 }
3165 }
3166 }
3167 break;
3168
3169 case _100Mb:
3170 next_tick = 3000;
3171 if (!lp->tx_enable) {
3172 SET_100Mb;
3173 de4x5_init_connection(dev);
3174 } else {
3175 if (!lp->linkOK && (lp->autosense == AUTO)) {
3176 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3177 lp->media = INIT;
3178 lp->tcount++;
3179 next_tick = DE4X5_AUTOSENSE_MS;
3180 }
3181 }
3182 }
3183 break;
3184
3185 default:
3186 lp->tcount++;
3187printk("Huh?: media:%02x\n", lp->media);
3188 lp->media = INIT;
3189 break;
3190 }
3191
3192 return next_tick;
3193}
3194
3195static int
3196srom_autoconf(struct net_device *dev)
3197{
3198 struct de4x5_private *lp = netdev_priv(dev);
3199
3200 return lp->infoleaf_fn(dev);
3201}
3202
3203
3204
3205
3206
3207
3208static int
3209srom_map_media(struct net_device *dev)
3210{
3211 struct de4x5_private *lp = netdev_priv(dev);
3212
3213 lp->fdx = false;
3214 if (lp->infoblock_media == lp->media)
3215 return 0;
3216
3217 switch(lp->infoblock_media) {
3218 case SROM_10BASETF:
3219 if (!lp->params.fdx) return -1;
3220 lp->fdx = true;
3221 case SROM_10BASET:
3222 if (lp->params.fdx && !lp->fdx) return -1;
3223 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3224 lp->media = _10Mb;
3225 } else {
3226 lp->media = TP;
3227 }
3228 break;
3229
3230 case SROM_10BASE2:
3231 lp->media = BNC;
3232 break;
3233
3234 case SROM_10BASE5:
3235 lp->media = AUI;
3236 break;
3237
3238 case SROM_100BASETF:
3239 if (!lp->params.fdx) return -1;
3240 lp->fdx = true;
3241 case SROM_100BASET:
3242 if (lp->params.fdx && !lp->fdx) return -1;
3243 lp->media = _100Mb;
3244 break;
3245
3246 case SROM_100BASET4:
3247 lp->media = _100Mb;
3248 break;
3249
3250 case SROM_100BASEFF:
3251 if (!lp->params.fdx) return -1;
3252 lp->fdx = true;
3253 case SROM_100BASEF:
3254 if (lp->params.fdx && !lp->fdx) return -1;
3255 lp->media = _100Mb;
3256 break;
3257
3258 case ANS:
3259 lp->media = ANS;
3260 lp->fdx = lp->params.fdx;
3261 break;
3262
3263 default:
3264 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3265 lp->infoblock_media);
3266 return -1;
3267 break;
3268 }
3269
3270 return 0;
3271}
3272
3273static void
3274de4x5_init_connection(struct net_device *dev)
3275{
3276 struct de4x5_private *lp = netdev_priv(dev);
3277 u_long iobase = dev->base_addr;
3278 u_long flags = 0;
3279
3280 if (lp->media != lp->c_media) {
3281 de4x5_dbg_media(dev);
3282 lp->c_media = lp->media;
3283 }
3284
3285 spin_lock_irqsave(&lp->lock, flags);
3286 de4x5_rst_desc_ring(dev);
3287 de4x5_setup_intr(dev);
3288 lp->tx_enable = true;
3289 spin_unlock_irqrestore(&lp->lock, flags);
3290 outl(POLL_DEMAND, DE4X5_TPD);
3291
3292 netif_wake_queue(dev);
3293
3294 return;
3295}
3296
3297
3298
3299
3300
3301
3302static int
3303de4x5_reset_phy(struct net_device *dev)
3304{
3305 struct de4x5_private *lp = netdev_priv(dev);
3306 u_long iobase = dev->base_addr;
3307 int next_tick = 0;
3308
3309 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3310 if (lp->timeout < 0) {
3311 if (lp->useSROM) {
3312 if (lp->phy[lp->active].rst) {
3313 srom_exec(dev, lp->phy[lp->active].rst);
3314 srom_exec(dev, lp->phy[lp->active].rst);
3315 } else if (lp->rst) {
3316 srom_exec(dev, lp->rst);
3317 srom_exec(dev, lp->rst);
3318 }
3319 } else {
3320 PHY_HARD_RESET;
3321 }
3322 if (lp->useMII) {
3323 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3324 }
3325 }
3326 if (lp->useMII) {
3327 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3328 }
3329 } else if (lp->chipset == DC21140) {
3330 PHY_HARD_RESET;
3331 }
3332
3333 return next_tick;
3334}
3335
3336static int
3337test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3338{
3339 struct de4x5_private *lp = netdev_priv(dev);
3340 u_long iobase = dev->base_addr;
3341 s32 sts, csr12;
3342
3343 if (lp->timeout < 0) {
3344 lp->timeout = msec/100;
3345 if (!lp->useSROM) {
3346 reset_init_sia(dev, csr13, csr14, csr15);
3347 }
3348
3349
3350 outl(irq_mask, DE4X5_IMR);
3351
3352
3353 sts = inl(DE4X5_STS);
3354 outl(sts, DE4X5_STS);
3355
3356
3357 if ((lp->chipset == DC21041) || lp->useSROM) {
3358 csr12 = inl(DE4X5_SISR);
3359 outl(csr12, DE4X5_SISR);
3360 }
3361 }
3362
3363 sts = inl(DE4X5_STS) & ~TIMER_CB;
3364
3365 if (!(sts & irqs) && --lp->timeout) {
3366 sts = 100 | TIMER_CB;
3367 } else {
3368 lp->timeout = -1;
3369 }
3370
3371 return sts;
3372}
3373
3374static int
3375test_tp(struct net_device *dev, s32 msec)
3376{
3377 struct de4x5_private *lp = netdev_priv(dev);
3378 u_long iobase = dev->base_addr;
3379 int sisr;
3380
3381 if (lp->timeout < 0) {
3382 lp->timeout = msec/100;
3383 }
3384
3385 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3386
3387 if (sisr && --lp->timeout) {
3388 sisr = 100 | TIMER_CB;
3389 } else {
3390 lp->timeout = -1;
3391 }
3392
3393 return sisr;
3394}
3395
3396
3397
3398
3399
3400
3401#define SAMPLE_INTERVAL 500
3402#define SAMPLE_DELAY 2000
3403static int
3404test_for_100Mb(struct net_device *dev, int msec)
3405{
3406 struct de4x5_private *lp = netdev_priv(dev);
3407 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3408
3409 if (lp->timeout < 0) {
3410 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3411 if (msec > SAMPLE_DELAY) {
3412 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3413 gep = SAMPLE_DELAY | TIMER_CB;
3414 return gep;
3415 } else {
3416 lp->timeout = msec/SAMPLE_INTERVAL;
3417 }
3418 }
3419
3420 if (lp->phy[lp->active].id || lp->useSROM) {
3421 gep = is_100_up(dev) | is_spd_100(dev);
3422 } else {
3423 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3424 }
3425 if (!(gep & ret) && --lp->timeout) {
3426 gep = SAMPLE_INTERVAL | TIMER_CB;
3427 } else {
3428 lp->timeout = -1;
3429 }
3430
3431 return gep;
3432}
3433
3434static int
3435wait_for_link(struct net_device *dev)
3436{
3437 struct de4x5_private *lp = netdev_priv(dev);
3438
3439 if (lp->timeout < 0) {
3440 lp->timeout = 1;
3441 }
3442
3443 if (lp->timeout--) {
3444 return TIMER_CB;
3445 } else {
3446 lp->timeout = -1;
3447 }
3448
3449 return 0;
3450}
3451
3452
3453
3454
3455
3456static int
3457test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3458{
3459 struct de4x5_private *lp = netdev_priv(dev);
3460 int test;
3461 u_long iobase = dev->base_addr;
3462
3463 if (lp->timeout < 0) {
3464 lp->timeout = msec/100;
3465 }
3466
3467 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3468 test = (reg ^ (pol ? ~0 : 0)) & mask;
3469
3470 if (test && --lp->timeout) {
3471 reg = 100 | TIMER_CB;
3472 } else {
3473 lp->timeout = -1;
3474 }
3475
3476 return reg;
3477}
3478
3479static int
3480is_spd_100(struct net_device *dev)
3481{
3482 struct de4x5_private *lp = netdev_priv(dev);
3483 u_long iobase = dev->base_addr;
3484 int spd;
3485
3486 if (lp->useMII) {
3487 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3488 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3489 spd &= lp->phy[lp->active].spd.mask;
3490 } else if (!lp->useSROM) {
3491 spd = ((~gep_rd(dev)) & GEP_SLNK);
3492 } else {
3493 if ((lp->ibn == 2) || !lp->asBitValid)
3494 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3495
3496 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3497 (lp->linkOK & ~lp->asBitValid);
3498 }
3499
3500 return spd;
3501}
3502
3503static int
3504is_100_up(struct net_device *dev)
3505{
3506 struct de4x5_private *lp = netdev_priv(dev);
3507 u_long iobase = dev->base_addr;
3508
3509 if (lp->useMII) {
3510
3511 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3512 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3513 } else if (!lp->useSROM) {
3514 return ((~gep_rd(dev)) & GEP_SLNK);
3515 } else {
3516 if ((lp->ibn == 2) || !lp->asBitValid)
3517 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3518
3519 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3520 (lp->linkOK & ~lp->asBitValid));
3521 }
3522}
3523
3524static int
3525is_10_up(struct net_device *dev)
3526{
3527 struct de4x5_private *lp = netdev_priv(dev);
3528 u_long iobase = dev->base_addr;
3529
3530 if (lp->useMII) {
3531
3532 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3533 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3534 } else if (!lp->useSROM) {
3535 return ((~gep_rd(dev)) & GEP_LNP);
3536 } else {
3537 if ((lp->ibn == 2) || !lp->asBitValid)
3538 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3539 (~inl(DE4X5_SISR)&SISR_LS10):
3540 0);
3541
3542 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3543 (lp->linkOK & ~lp->asBitValid));
3544 }
3545}
3546
3547static int
3548is_anc_capable(struct net_device *dev)
3549{
3550 struct de4x5_private *lp = netdev_priv(dev);
3551 u_long iobase = dev->base_addr;
3552
3553 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3554 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3555 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3556 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3557 } else {
3558 return 0;
3559 }
3560}
3561
3562
3563
3564
3565
3566static int
3567ping_media(struct net_device *dev, int msec)
3568{
3569 struct de4x5_private *lp = netdev_priv(dev);
3570 u_long iobase = dev->base_addr;
3571 int sisr;
3572
3573 if (lp->timeout < 0) {
3574 lp->timeout = msec/100;
3575
3576 lp->tmp = lp->tx_new;
3577 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3578 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3579 outl(POLL_DEMAND, DE4X5_TPD);
3580 }
3581
3582 sisr = inl(DE4X5_SISR);
3583
3584 if ((!(sisr & SISR_NCR)) &&
3585 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3586 (--lp->timeout)) {
3587 sisr = 100 | TIMER_CB;
3588 } else {
3589 if ((!(sisr & SISR_NCR)) &&
3590 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3591 lp->timeout) {
3592 sisr = 0;
3593 } else {
3594 sisr = 1;
3595 }
3596 lp->timeout = -1;
3597 }
3598
3599 return sisr;
3600}
3601
3602
3603
3604
3605
3606
3607static struct sk_buff *
3608de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3609{
3610 struct de4x5_private *lp = netdev_priv(dev);
3611 struct sk_buff *p;
3612
3613#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3614 struct sk_buff *ret;
3615 u_long i=0, tmp;
3616
3617 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3618 if (!p) return NULL;
3619
3620 tmp = virt_to_bus(p->data);
3621 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3622 skb_reserve(p, i);
3623 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3624
3625 ret = lp->rx_skb[index];
3626 lp->rx_skb[index] = p;
3627
3628 if ((u_long) ret > 1) {
3629 skb_put(ret, len);
3630 }
3631
3632 return ret;
3633
3634#else
3635 if (lp->state != OPEN) return (struct sk_buff *)1;
3636
3637 p = dev_alloc_skb(len + 2);
3638 if (!p) return NULL;
3639
3640 skb_reserve(p, 2);
3641 if (index < lp->rx_old) {
3642 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3643 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3644 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3645 } else {
3646 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3647 }
3648
3649 return p;
3650#endif
3651}
3652
3653static void
3654de4x5_free_rx_buffs(struct net_device *dev)
3655{
3656 struct de4x5_private *lp = netdev_priv(dev);
3657 int i;
3658
3659 for (i=0; i<lp->rxRingSize; i++) {
3660 if ((u_long) lp->rx_skb[i] > 1) {
3661 dev_kfree_skb(lp->rx_skb[i]);
3662 }
3663 lp->rx_ring[i].status = 0;
3664 lp->rx_skb[i] = (struct sk_buff *)1;
3665 }
3666
3667 return;
3668}
3669
3670static void
3671de4x5_free_tx_buffs(struct net_device *dev)
3672{
3673 struct de4x5_private *lp = netdev_priv(dev);
3674 int i;
3675
3676 for (i=0; i<lp->txRingSize; i++) {
3677 if (lp->tx_skb[i])
3678 de4x5_free_tx_buff(lp, i);
3679 lp->tx_ring[i].status = 0;
3680 }
3681
3682
3683 while (lp->cache.skb) {
3684 dev_kfree_skb(de4x5_get_cache(dev));
3685 }
3686
3687 return;
3688}
3689
3690
3691
3692
3693
3694
3695
3696
3697static void
3698de4x5_save_skbs(struct net_device *dev)
3699{
3700 struct de4x5_private *lp = netdev_priv(dev);
3701 u_long iobase = dev->base_addr;
3702 s32 omr;
3703
3704 if (!lp->cache.save_cnt) {
3705 STOP_DE4X5;
3706 de4x5_tx(dev);
3707 de4x5_free_tx_buffs(dev);
3708 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3709 de4x5_sw_reset(dev);
3710 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3711 lp->cache.save_cnt++;
3712 START_DE4X5;
3713 }
3714
3715 return;
3716}
3717
3718static void
3719de4x5_rst_desc_ring(struct net_device *dev)
3720{
3721 struct de4x5_private *lp = netdev_priv(dev);
3722 u_long iobase = dev->base_addr;
3723 int i;
3724 s32 omr;
3725
3726 if (lp->cache.save_cnt) {
3727 STOP_DE4X5;
3728 outl(lp->dma_rings, DE4X5_RRBA);
3729 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3730 DE4X5_TRBA);
3731
3732 lp->rx_new = lp->rx_old = 0;
3733 lp->tx_new = lp->tx_old = 0;
3734
3735 for (i = 0; i < lp->rxRingSize; i++) {
3736 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3737 }
3738
3739 for (i = 0; i < lp->txRingSize; i++) {
3740 lp->tx_ring[i].status = cpu_to_le32(0);
3741 }
3742
3743 barrier();
3744 lp->cache.save_cnt--;
3745 START_DE4X5;
3746 }
3747
3748 return;
3749}
3750
3751static void
3752de4x5_cache_state(struct net_device *dev, int flag)
3753{
3754 struct de4x5_private *lp = netdev_priv(dev);
3755 u_long iobase = dev->base_addr;
3756
3757 switch(flag) {
3758 case DE4X5_SAVE_STATE:
3759 lp->cache.csr0 = inl(DE4X5_BMR);
3760 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3761 lp->cache.csr7 = inl(DE4X5_IMR);
3762 break;
3763
3764 case DE4X5_RESTORE_STATE:
3765 outl(lp->cache.csr0, DE4X5_BMR);
3766 outl(lp->cache.csr6, DE4X5_OMR);
3767 outl(lp->cache.csr7, DE4X5_IMR);
3768 if (lp->chipset == DC21140) {
3769 gep_wr(lp->cache.gepc, dev);
3770 gep_wr(lp->cache.gep, dev);
3771 } else {
3772 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3773 lp->cache.csr15);
3774 }
3775 break;
3776 }
3777
3778 return;
3779}
3780
3781static void
3782de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3783{
3784 struct de4x5_private *lp = netdev_priv(dev);
3785 struct sk_buff *p;
3786
3787 if (lp->cache.skb) {
3788 for (p=lp->cache.skb; p->next; p=p->next);
3789 p->next = skb;
3790 } else {
3791 lp->cache.skb = skb;
3792 }
3793 skb->next = NULL;
3794
3795 return;
3796}
3797
3798static void
3799de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3800{
3801 struct de4x5_private *lp = netdev_priv(dev);
3802 struct sk_buff *p = lp->cache.skb;
3803
3804 lp->cache.skb = skb;
3805 skb->next = p;
3806
3807 return;
3808}
3809
3810static struct sk_buff *
3811de4x5_get_cache(struct net_device *dev)
3812{
3813 struct de4x5_private *lp = netdev_priv(dev);
3814 struct sk_buff *p = lp->cache.skb;
3815
3816 if (p) {
3817 lp->cache.skb = p->next;
3818 p->next = NULL;
3819 }
3820
3821 return p;
3822}
3823
3824
3825
3826
3827
3828static int
3829test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3830{
3831 struct de4x5_private *lp = netdev_priv(dev);
3832 u_long iobase = dev->base_addr;
3833 s32 sts, ans;
3834
3835 if (lp->timeout < 0) {
3836 lp->timeout = msec/100;
3837 outl(irq_mask, DE4X5_IMR);
3838
3839
3840 sts = inl(DE4X5_STS);
3841 outl(sts, DE4X5_STS);
3842 }
3843
3844 ans = inl(DE4X5_SISR) & SISR_ANS;
3845 sts = inl(DE4X5_STS) & ~TIMER_CB;
3846
3847 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3848 sts = 100 | TIMER_CB;
3849 } else {
3850 lp->timeout = -1;
3851 }
3852
3853 return sts;
3854}
3855
3856static void
3857de4x5_setup_intr(struct net_device *dev)
3858{
3859 struct de4x5_private *lp = netdev_priv(dev);
3860 u_long iobase = dev->base_addr;
3861 s32 imr, sts;
3862
3863 if (inl(DE4X5_OMR) & OMR_SR) {
3864 imr = 0;
3865 UNMASK_IRQs;
3866 sts = inl(DE4X5_STS);
3867 outl(sts, DE4X5_STS);
3868 ENABLE_IRQs;
3869 }
3870
3871 return;
3872}
3873
3874
3875
3876
3877static void
3878reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3879{
3880 struct de4x5_private *lp = netdev_priv(dev);
3881 u_long iobase = dev->base_addr;
3882
3883 RESET_SIA;
3884 if (lp->useSROM) {
3885 if (lp->ibn == 3) {
3886 srom_exec(dev, lp->phy[lp->active].rst);
3887 srom_exec(dev, lp->phy[lp->active].gep);
3888 outl(1, DE4X5_SICR);
3889 return;
3890 } else {
3891 csr15 = lp->cache.csr15;
3892 csr14 = lp->cache.csr14;
3893 csr13 = lp->cache.csr13;
3894 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3895 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3896 }
3897 } else {
3898 outl(csr15, DE4X5_SIGR);
3899 }
3900 outl(csr14, DE4X5_STRR);
3901 outl(csr13, DE4X5_SICR);
3902
3903 mdelay(10);
3904
3905 return;
3906}
3907
3908
3909
3910
3911static void
3912create_packet(struct net_device *dev, char *frame, int len)
3913{
3914 int i;
3915 char *buf = frame;
3916
3917 for (i=0; i<ETH_ALEN; i++) {
3918 *buf++ = dev->dev_addr[i];
3919 }
3920 for (i=0; i<ETH_ALEN; i++) {
3921 *buf++ = dev->dev_addr[i];
3922 }
3923
3924 *buf++ = 0;
3925 *buf++ = 1;
3926
3927 return;
3928}
3929
3930
3931
3932
3933static int
3934EISA_signature(char *name, struct device *device)
3935{
3936 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3937 struct eisa_device *edev;
3938
3939 *name = '\0';
3940 edev = to_eisa_device (device);
3941 i = edev->id.driver_data;
3942
3943 if (i >= 0 && i < siglen) {
3944 strcpy (name, de4x5_signatures[i]);
3945 status = 1;
3946 }
3947
3948 return status;
3949}
3950
3951
3952
3953
3954static int
3955PCI_signature(char *name, struct de4x5_private *lp)
3956{
3957 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3958
3959 if (lp->chipset == DC21040) {
3960 strcpy(name, "DE434/5");
3961 return status;
3962 } else {
3963 int i = *((char *)&lp->srom + 19) * 3;
3964 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3965 }
3966 name[8] = '\0';
3967 for (i=0; i<siglen; i++) {
3968 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3969 }
3970 if (i == siglen) {
3971 if (dec_only) {
3972 *name = '\0';
3973 } else {
3974 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3975 ((lp->chipset == DC21041) ? "DC21041" :
3976 ((lp->chipset == DC21140) ? "DC21140" :
3977 ((lp->chipset == DC21142) ? "DC21142" :
3978 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3979 )))))));
3980 }
3981 if (lp->chipset != DC21041) {
3982 lp->useSROM = true;
3983 }
3984 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3985 lp->useSROM = true;
3986 }
3987
3988 return status;
3989}
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999static void
4000DevicePresent(struct net_device *dev, u_long aprom_addr)
4001{
4002 int i, j=0;
4003 struct de4x5_private *lp = netdev_priv(dev);
4004
4005 if (lp->chipset == DC21040) {
4006 if (lp->bus == EISA) {
4007 enet_addr_rst(aprom_addr);
4008 } else {
4009 outl(0, aprom_addr);
4010 }
4011 } else {
4012 u_short tmp;
4013 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
4014 for (i=0; i<(ETH_ALEN>>1); i++) {
4015 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4016 j += tmp;
4017 *p = cpu_to_le16(tmp);
4018 }
4019 if (j == 0 || j == 3 * 0xffff) {
4020
4021 return;
4022 }
4023
4024 p = (__le16 *)&lp->srom;
4025 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4026 tmp = srom_rd(aprom_addr, i);
4027 *p++ = cpu_to_le16(tmp);
4028 }
4029 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4030 }
4031
4032 return;
4033}
4034
4035
4036
4037
4038
4039
4040static void
4041enet_addr_rst(u_long aprom_addr)
4042{
4043 union {
4044 struct {
4045 u32 a;
4046 u32 b;
4047 } llsig;
4048 char Sig[sizeof(u32) << 1];
4049 } dev;
4050 short sigLength=0;
4051 s8 data;
4052 int i, j;
4053
4054 dev.llsig.a = ETH_PROM_SIG;
4055 dev.llsig.b = ETH_PROM_SIG;
4056 sigLength = sizeof(u32) << 1;
4057
4058 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4059 data = inb(aprom_addr);
4060 if (dev.Sig[j] == data) {
4061 j++;
4062 } else {
4063 if (data == dev.Sig[0]) {
4064 j=1;
4065 } else {
4066 j=0;
4067 }
4068 }
4069 }
4070
4071 return;
4072}
4073
4074
4075
4076
4077
4078
4079
4080static int
4081get_hw_addr(struct net_device *dev)
4082{
4083 u_long iobase = dev->base_addr;
4084 int broken, i, k, tmp, status = 0;
4085 u_short j,chksum;
4086 struct de4x5_private *lp = netdev_priv(dev);
4087
4088 broken = de4x5_bad_srom(lp);
4089
4090 for (i=0,k=0,j=0;j<3;j++) {
4091 k <<= 1;
4092 if (k > 0xffff) k-=0xffff;
4093
4094 if (lp->bus == PCI) {
4095 if (lp->chipset == DC21040) {
4096 while ((tmp = inl(DE4X5_APROM)) < 0);
4097 k += (u_char) tmp;
4098 dev->dev_addr[i++] = (u_char) tmp;
4099 while ((tmp = inl(DE4X5_APROM)) < 0);
4100 k += (u_short) (tmp << 8);
4101 dev->dev_addr[i++] = (u_char) tmp;
4102 } else if (!broken) {
4103 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4104 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4105 } else if ((broken == SMC) || (broken == ACCTON)) {
4106 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4107 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4108 }
4109 } else {
4110 k += (u_char) (tmp = inb(EISA_APROM));
4111 dev->dev_addr[i++] = (u_char) tmp;
4112 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4113 dev->dev_addr[i++] = (u_char) tmp;
4114 }
4115
4116 if (k > 0xffff) k-=0xffff;
4117 }
4118 if (k == 0xffff) k=0;
4119
4120 if (lp->bus == PCI) {
4121 if (lp->chipset == DC21040) {
4122 while ((tmp = inl(DE4X5_APROM)) < 0);
4123 chksum = (u_char) tmp;
4124 while ((tmp = inl(DE4X5_APROM)) < 0);
4125 chksum |= (u_short) (tmp << 8);
4126 if ((k != chksum) && (dec_only)) status = -1;
4127 }
4128 } else {
4129 chksum = (u_char) inb(EISA_APROM);
4130 chksum |= (u_short) (inb(EISA_APROM) << 8);
4131 if ((k != chksum) && (dec_only)) status = -1;
4132 }
4133
4134
4135 srom_repair(dev, broken);
4136
4137#ifdef CONFIG_PPC_PMAC
4138
4139
4140
4141
4142 if ( machine_is(powermac) &&
4143 (dev->dev_addr[0] == 0) &&
4144 (dev->dev_addr[1] == 0xa0) )
4145 {
4146 for (i = 0; i < ETH_ALEN; ++i)
4147 {
4148 int x = dev->dev_addr[i];
4149 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4150 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4151 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4152 }
4153 }
4154#endif
4155
4156
4157 status = test_bad_enet(dev, status);
4158
4159 return status;
4160}
4161
4162
4163
4164
4165
4166static int
4167de4x5_bad_srom(struct de4x5_private *lp)
4168{
4169 int i, status = 0;
4170
4171 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4172 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4173 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4174 if (i == 0) {
4175 status = SMC;
4176 } else if (i == 1) {
4177 status = ACCTON;
4178 }
4179 break;
4180 }
4181 }
4182
4183 return status;
4184}
4185
4186static int
4187de4x5_strncmp(char *a, char *b, int n)
4188{
4189 int ret=0;
4190
4191 for (;n && !ret;n--) {
4192 ret = *a++ - *b++;
4193 }
4194
4195 return ret;
4196}
4197
4198static void
4199srom_repair(struct net_device *dev, int card)
4200{
4201 struct de4x5_private *lp = netdev_priv(dev);
4202
4203 switch(card) {
4204 case SMC:
4205 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4206 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4207 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4208 lp->useSROM = true;
4209 break;
4210 }
4211
4212 return;
4213}
4214
4215
4216
4217
4218
4219static int
4220test_bad_enet(struct net_device *dev, int status)
4221{
4222 struct de4x5_private *lp = netdev_priv(dev);
4223 int i, tmp;
4224
4225 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4226 if ((tmp == 0) || (tmp == 0x5fa)) {
4227 if ((lp->chipset == last.chipset) &&
4228 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4229 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4230 for (i=ETH_ALEN-1; i>2; --i) {
4231 dev->dev_addr[i] += 1;
4232 if (dev->dev_addr[i] != 0) break;
4233 }
4234 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4235 if (!an_exception(lp)) {
4236 dev->irq = last.irq;
4237 }
4238
4239 status = 0;
4240 }
4241 } else if (!status) {
4242 last.chipset = lp->chipset;
4243 last.bus = lp->bus_num;
4244 last.irq = dev->irq;
4245 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4246 }
4247
4248 return status;
4249}
4250
4251
4252
4253
4254static int
4255an_exception(struct de4x5_private *lp)
4256{
4257 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4258 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4259 return -1;
4260 }
4261
4262 return 0;
4263}
4264
4265
4266
4267
4268static short
4269srom_rd(u_long addr, u_char offset)
4270{
4271 sendto_srom(SROM_RD | SROM_SR, addr);
4272
4273 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4274 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4275 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4276
4277 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4278}
4279
4280static void
4281srom_latch(u_int command, u_long addr)
4282{
4283 sendto_srom(command, addr);
4284 sendto_srom(command | DT_CLK, addr);
4285 sendto_srom(command, addr);
4286
4287 return;
4288}
4289
4290static void
4291srom_command(u_int command, u_long addr)
4292{
4293 srom_latch(command, addr);
4294 srom_latch(command, addr);
4295 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4296
4297 return;
4298}
4299
4300static void
4301srom_address(u_int command, u_long addr, u_char offset)
4302{
4303 int i, a;
4304
4305 a = offset << 2;
4306 for (i=0; i<6; i++, a <<= 1) {
4307 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4308 }
4309 udelay(1);
4310
4311 i = (getfrom_srom(addr) >> 3) & 0x01;
4312
4313 return;
4314}
4315
4316static short
4317srom_data(u_int command, u_long addr)
4318{
4319 int i;
4320 short word = 0;
4321 s32 tmp;
4322
4323 for (i=0; i<16; i++) {
4324 sendto_srom(command | DT_CLK, addr);
4325 tmp = getfrom_srom(addr);
4326 sendto_srom(command, addr);
4327
4328 word = (word << 1) | ((tmp >> 3) & 0x01);
4329 }
4330
4331 sendto_srom(command & 0x0000ff00, addr);
4332
4333 return word;
4334}
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352static void
4353sendto_srom(u_int command, u_long addr)
4354{
4355 outl(command, addr);
4356 udelay(1);
4357
4358 return;
4359}
4360
4361static int
4362getfrom_srom(u_long addr)
4363{
4364 s32 tmp;
4365
4366 tmp = inl(addr);
4367 udelay(1);
4368
4369 return tmp;
4370}
4371
4372static int
4373srom_infoleaf_info(struct net_device *dev)
4374{
4375 struct de4x5_private *lp = netdev_priv(dev);
4376 int i, count;
4377 u_char *p;
4378
4379
4380 for (i=0; i<INFOLEAF_SIZE; i++) {
4381 if (lp->chipset == infoleaf_array[i].chipset) break;
4382 }
4383 if (i == INFOLEAF_SIZE) {
4384 lp->useSROM = false;
4385 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4386 dev->name);
4387 return -ENXIO;
4388 }
4389
4390 lp->infoleaf_fn = infoleaf_array[i].fn;
4391
4392
4393 count = *((u_char *)&lp->srom + 19);
4394 p = (u_char *)&lp->srom + 26;
4395
4396 if (count > 1) {
4397 for (i=count; i; --i, p+=3) {
4398 if (lp->device == *p) break;
4399 }
4400 if (i == 0) {
4401 lp->useSROM = false;
4402 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4403 dev->name, lp->device);
4404 return -ENXIO;
4405 }
4406 }
4407
4408 lp->infoleaf_offset = TWIDDLE(p+1);
4409
4410 return 0;
4411}
4412
4413
4414
4415
4416
4417
4418
4419
4420static void
4421srom_init(struct net_device *dev)
4422{
4423 struct de4x5_private *lp = netdev_priv(dev);
4424 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4425 u_char count;
4426
4427 p+=2;
4428 if (lp->chipset == DC21140) {
4429 lp->cache.gepc = (*p++ | GEP_CTRL);
4430 gep_wr(lp->cache.gepc, dev);
4431 }
4432
4433
4434 count = *p++;
4435
4436
4437 for (;count; --count) {
4438 if (*p < 128) {
4439 p += COMPACT_LEN;
4440 } else if (*(p+1) == 5) {
4441 type5_infoblock(dev, 1, p);
4442 p += ((*p & BLOCK_LEN) + 1);
4443 } else if (*(p+1) == 4) {
4444 p += ((*p & BLOCK_LEN) + 1);
4445 } else if (*(p+1) == 3) {
4446 type3_infoblock(dev, 1, p);
4447 p += ((*p & BLOCK_LEN) + 1);
4448 } else if (*(p+1) == 2) {
4449 p += ((*p & BLOCK_LEN) + 1);
4450 } else if (*(p+1) == 1) {
4451 type1_infoblock(dev, 1, p);
4452 p += ((*p & BLOCK_LEN) + 1);
4453 } else {
4454 p += ((*p & BLOCK_LEN) + 1);
4455 }
4456 }
4457
4458 return;
4459}
4460
4461
4462
4463
4464
4465static void
4466srom_exec(struct net_device *dev, u_char *p)
4467{
4468 struct de4x5_private *lp = netdev_priv(dev);
4469 u_long iobase = dev->base_addr;
4470 u_char count = (p ? *p++ : 0);
4471 u_short *w = (u_short *)p;
4472
4473 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4474
4475 if (lp->chipset != DC21140) RESET_SIA;
4476
4477 while (count--) {
4478 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4479 *p++ : TWIDDLE(w++)), dev);
4480 mdelay(2);
4481 }
4482
4483 if (lp->chipset != DC21140) {
4484 outl(lp->cache.csr14, DE4X5_STRR);
4485 outl(lp->cache.csr13, DE4X5_SICR);
4486 }
4487
4488 return;
4489}
4490
4491
4492
4493
4494
4495
4496static int
4497dc21041_infoleaf(struct net_device *dev)
4498{
4499 return DE4X5_AUTOSENSE_MS;
4500}
4501
4502static int
4503dc21140_infoleaf(struct net_device *dev)
4504{
4505 struct de4x5_private *lp = netdev_priv(dev);
4506 u_char count = 0;
4507 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4508 int next_tick = DE4X5_AUTOSENSE_MS;
4509
4510
4511 p+=2;
4512
4513
4514 lp->cache.gepc = (*p++ | GEP_CTRL);
4515
4516
4517 count = *p++;
4518
4519
4520 if (*p < 128) {
4521 next_tick = dc_infoblock[COMPACT](dev, count, p);
4522 } else {
4523 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4524 }
4525
4526 if (lp->tcount == count) {
4527 lp->media = NC;
4528 if (lp->media != lp->c_media) {
4529 de4x5_dbg_media(dev);
4530 lp->c_media = lp->media;
4531 }
4532 lp->media = INIT;
4533 lp->tcount = 0;
4534 lp->tx_enable = false;
4535 }
4536
4537 return next_tick & ~TIMER_CB;
4538}
4539
4540static int
4541dc21142_infoleaf(struct net_device *dev)
4542{
4543 struct de4x5_private *lp = netdev_priv(dev);
4544 u_char count = 0;
4545 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4546 int next_tick = DE4X5_AUTOSENSE_MS;
4547
4548
4549 p+=2;
4550
4551
4552 count = *p++;
4553
4554
4555 if (*p < 128) {
4556 next_tick = dc_infoblock[COMPACT](dev, count, p);
4557 } else {
4558 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4559 }
4560
4561 if (lp->tcount == count) {
4562 lp->media = NC;
4563 if (lp->media != lp->c_media) {
4564 de4x5_dbg_media(dev);
4565 lp->c_media = lp->media;
4566 }
4567 lp->media = INIT;
4568 lp->tcount = 0;
4569 lp->tx_enable = false;
4570 }
4571
4572 return next_tick & ~TIMER_CB;
4573}
4574
4575static int
4576dc21143_infoleaf(struct net_device *dev)
4577{
4578 struct de4x5_private *lp = netdev_priv(dev);
4579 u_char count = 0;
4580 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4581 int next_tick = DE4X5_AUTOSENSE_MS;
4582
4583
4584 p+=2;
4585
4586
4587 count = *p++;
4588
4589
4590 if (*p < 128) {
4591 next_tick = dc_infoblock[COMPACT](dev, count, p);
4592 } else {
4593 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4594 }
4595 if (lp->tcount == count) {
4596 lp->media = NC;
4597 if (lp->media != lp->c_media) {
4598 de4x5_dbg_media(dev);
4599 lp->c_media = lp->media;
4600 }
4601 lp->media = INIT;
4602 lp->tcount = 0;
4603 lp->tx_enable = false;
4604 }
4605
4606 return next_tick & ~TIMER_CB;
4607}
4608
4609
4610
4611
4612
4613static int
4614compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4615{
4616 struct de4x5_private *lp = netdev_priv(dev);
4617 u_char flags, csr6;
4618
4619
4620 if (--count > lp->tcount) {
4621 if (*(p+COMPACT_LEN) < 128) {
4622 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4623 } else {
4624 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4625 }
4626 }
4627
4628 if ((lp->media == INIT) && (lp->timeout < 0)) {
4629 lp->ibn = COMPACT;
4630 lp->active = 0;
4631 gep_wr(lp->cache.gepc, dev);
4632 lp->infoblock_media = (*p++) & COMPACT_MC;
4633 lp->cache.gep = *p++;
4634 csr6 = *p++;
4635 flags = *p++;
4636
4637 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4638 lp->defMedium = (flags & 0x40) ? -1 : 0;
4639 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4640 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4641 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4642 lp->useMII = false;
4643
4644 de4x5_switch_mac_port(dev);
4645 }
4646
4647 return dc21140m_autoconf(dev);
4648}
4649
4650
4651
4652
4653static int
4654type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4655{
4656 struct de4x5_private *lp = netdev_priv(dev);
4657 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4658
4659
4660 if (--count > lp->tcount) {
4661 if (*(p+len) < 128) {
4662 return dc_infoblock[COMPACT](dev, count, p+len);
4663 } else {
4664 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4665 }
4666 }
4667
4668 if ((lp->media == INIT) && (lp->timeout < 0)) {
4669 lp->ibn = 0;
4670 lp->active = 0;
4671 gep_wr(lp->cache.gepc, dev);
4672 p+=2;
4673 lp->infoblock_media = (*p++) & BLOCK0_MC;
4674 lp->cache.gep = *p++;
4675 csr6 = *p++;
4676 flags = *p++;
4677
4678 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4679 lp->defMedium = (flags & 0x40) ? -1 : 0;
4680 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4681 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4682 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4683 lp->useMII = false;
4684
4685 de4x5_switch_mac_port(dev);
4686 }
4687
4688 return dc21140m_autoconf(dev);
4689}
4690
4691
4692
4693static int
4694type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4695{
4696 struct de4x5_private *lp = netdev_priv(dev);
4697 u_char len = (*p & BLOCK_LEN)+1;
4698
4699
4700 if (--count > lp->tcount) {
4701 if (*(p+len) < 128) {
4702 return dc_infoblock[COMPACT](dev, count, p+len);
4703 } else {
4704 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4705 }
4706 }
4707
4708 p += 2;
4709 if (lp->state == INITIALISED) {
4710 lp->ibn = 1;
4711 lp->active = *p++;
4712 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4713 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4714 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4715 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4716 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4717 lp->phy[lp->active].ttm = TWIDDLE(p);
4718 return 0;
4719 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4720 lp->ibn = 1;
4721 lp->active = *p;
4722 lp->infoblock_csr6 = OMR_MII_100;
4723 lp->useMII = true;
4724 lp->infoblock_media = ANS;
4725
4726 de4x5_switch_mac_port(dev);
4727 }
4728
4729 return dc21140m_autoconf(dev);
4730}
4731
4732static int
4733type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4734{
4735 struct de4x5_private *lp = netdev_priv(dev);
4736 u_char len = (*p & BLOCK_LEN)+1;
4737
4738
4739 if (--count > lp->tcount) {
4740 if (*(p+len) < 128) {
4741 return dc_infoblock[COMPACT](dev, count, p+len);
4742 } else {
4743 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4744 }
4745 }
4746
4747 if ((lp->media == INIT) && (lp->timeout < 0)) {
4748 lp->ibn = 2;
4749 lp->active = 0;
4750 p += 2;
4751 lp->infoblock_media = (*p) & MEDIA_CODE;
4752
4753 if ((*p++) & EXT_FIELD) {
4754 lp->cache.csr13 = TWIDDLE(p); p += 2;
4755 lp->cache.csr14 = TWIDDLE(p); p += 2;
4756 lp->cache.csr15 = TWIDDLE(p); p += 2;
4757 } else {
4758 lp->cache.csr13 = CSR13;
4759 lp->cache.csr14 = CSR14;
4760 lp->cache.csr15 = CSR15;
4761 }
4762 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4763 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4764 lp->infoblock_csr6 = OMR_SIA;
4765 lp->useMII = false;
4766
4767 de4x5_switch_mac_port(dev);
4768 }
4769
4770 return dc2114x_autoconf(dev);
4771}
4772
4773static int
4774type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4775{
4776 struct de4x5_private *lp = netdev_priv(dev);
4777 u_char len = (*p & BLOCK_LEN)+1;
4778
4779
4780 if (--count > lp->tcount) {
4781 if (*(p+len) < 128) {
4782 return dc_infoblock[COMPACT](dev, count, p+len);
4783 } else {
4784 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4785 }
4786 }
4787
4788 p += 2;
4789 if (lp->state == INITIALISED) {
4790 lp->ibn = 3;
4791 lp->active = *p++;
4792 if (MOTO_SROM_BUG) lp->active = 0;
4793 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4794 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4795 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4796 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4797 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4798 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4799 lp->phy[lp->active].mci = *p;
4800 return 0;
4801 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4802 lp->ibn = 3;
4803 lp->active = *p;
4804 if (MOTO_SROM_BUG) lp->active = 0;
4805 lp->infoblock_csr6 = OMR_MII_100;
4806 lp->useMII = true;
4807 lp->infoblock_media = ANS;
4808
4809 de4x5_switch_mac_port(dev);
4810 }
4811
4812 return dc2114x_autoconf(dev);
4813}
4814
4815static int
4816type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4817{
4818 struct de4x5_private *lp = netdev_priv(dev);
4819 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4820
4821
4822 if (--count > lp->tcount) {
4823 if (*(p+len) < 128) {
4824 return dc_infoblock[COMPACT](dev, count, p+len);
4825 } else {
4826 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4827 }
4828 }
4829
4830 if ((lp->media == INIT) && (lp->timeout < 0)) {
4831 lp->ibn = 4;
4832 lp->active = 0;
4833 p+=2;
4834 lp->infoblock_media = (*p++) & MEDIA_CODE;
4835 lp->cache.csr13 = CSR13;
4836 lp->cache.csr14 = CSR14;
4837 lp->cache.csr15 = CSR15;
4838 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4839 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4840 csr6 = *p++;
4841 flags = *p++;
4842
4843 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4844 lp->defMedium = (flags & 0x40) ? -1 : 0;
4845 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4846 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4847 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4848 lp->useMII = false;
4849
4850 de4x5_switch_mac_port(dev);
4851 }
4852
4853 return dc2114x_autoconf(dev);
4854}
4855
4856
4857
4858
4859
4860static int
4861type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4862{
4863 struct de4x5_private *lp = netdev_priv(dev);
4864 u_char len = (*p & BLOCK_LEN)+1;
4865
4866
4867 if (--count > lp->tcount) {
4868 if (*(p+len) < 128) {
4869 return dc_infoblock[COMPACT](dev, count, p+len);
4870 } else {
4871 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4872 }
4873 }
4874
4875
4876 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4877 p+=2;
4878 lp->rst = p;
4879 srom_exec(dev, lp->rst);
4880 }
4881
4882 return DE4X5_AUTOSENSE_MS;
4883}
4884
4885
4886
4887
4888
4889static int
4890mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4891{
4892 mii_wdata(MII_PREAMBLE, 2, ioaddr);
4893 mii_wdata(MII_PREAMBLE, 32, ioaddr);
4894 mii_wdata(MII_STRD, 4, ioaddr);
4895 mii_address(phyaddr, ioaddr);
4896 mii_address(phyreg, ioaddr);
4897 mii_ta(MII_STRD, ioaddr);
4898
4899 return mii_rdata(ioaddr);
4900}
4901
4902static void
4903mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4904{
4905 mii_wdata(MII_PREAMBLE, 2, ioaddr);
4906 mii_wdata(MII_PREAMBLE, 32, ioaddr);
4907 mii_wdata(MII_STWR, 4, ioaddr);
4908 mii_address(phyaddr, ioaddr);
4909 mii_address(phyreg, ioaddr);
4910 mii_ta(MII_STWR, ioaddr);
4911 data = mii_swap(data, 16);
4912 mii_wdata(data, 16, ioaddr);
4913
4914 return;
4915}
4916
4917static int
4918mii_rdata(u_long ioaddr)
4919{
4920 int i;
4921 s32 tmp = 0;
4922
4923 for (i=0; i<16; i++) {
4924 tmp <<= 1;
4925 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4926 }
4927
4928 return tmp;
4929}
4930
4931static void
4932mii_wdata(int data, int len, u_long ioaddr)
4933{
4934 int i;
4935
4936 for (i=0; i<len; i++) {
4937 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4938 data >>= 1;
4939 }
4940
4941 return;
4942}
4943
4944static void
4945mii_address(u_char addr, u_long ioaddr)
4946{
4947 int i;
4948
4949 addr = mii_swap(addr, 5);
4950 for (i=0; i<5; i++) {
4951 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4952 addr >>= 1;
4953 }
4954
4955 return;
4956}
4957
4958static void
4959mii_ta(u_long rw, u_long ioaddr)
4960{
4961 if (rw == MII_STWR) {
4962 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4963 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4964 } else {
4965 getfrom_mii(MII_MRD | MII_RD, ioaddr);
4966 }
4967
4968 return;
4969}
4970
4971static int
4972mii_swap(int data, int len)
4973{
4974 int i, tmp = 0;
4975
4976 for (i=0; i<len; i++) {
4977 tmp <<= 1;
4978 tmp |= (data & 1);
4979 data >>= 1;
4980 }
4981
4982 return tmp;
4983}
4984
4985static void
4986sendto_mii(u32 command, int data, u_long ioaddr)
4987{
4988 u32 j;
4989
4990 j = (data & 1) << 17;
4991 outl(command | j, ioaddr);
4992 udelay(1);
4993 outl(command | MII_MDC | j, ioaddr);
4994 udelay(1);
4995
4996 return;
4997}
4998
4999static int
5000getfrom_mii(u32 command, u_long ioaddr)
5001{
5002 outl(command, ioaddr);
5003 udelay(1);
5004 outl(command | MII_MDC, ioaddr);
5005 udelay(1);
5006
5007 return ((inl(ioaddr) >> 19) & 1);
5008}
5009
5010
5011
5012
5013static int
5014mii_get_oui(u_char phyaddr, u_long ioaddr)
5015{
5016
5017
5018
5019
5020
5021
5022 int r2, r3;
5023
5024
5025 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5026 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054 return r2;
5055}
5056
5057
5058
5059
5060static int
5061mii_get_phy(struct net_device *dev)
5062{
5063 struct de4x5_private *lp = netdev_priv(dev);
5064 u_long iobase = dev->base_addr;
5065 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
5066 int id;
5067
5068 lp->active = 0;
5069 lp->useMII = true;
5070
5071
5072 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5073 lp->phy[lp->active].addr = i;
5074 if (i==0) n++;
5075 while (de4x5_reset_phy(dev)<0) udelay(100);
5076 id = mii_get_oui(i, DE4X5_MII);
5077 if ((id == 0) || (id == 65535)) continue;
5078 for (j=0; j<limit; j++) {
5079 if (id != phy_info[j].id) continue;
5080 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5081 if (k < DE4X5_MAX_PHY) {
5082 memcpy((char *)&lp->phy[k],
5083 (char *)&phy_info[j], sizeof(struct phy_table));
5084 lp->phy[k].addr = i;
5085 lp->mii_cnt++;
5086 lp->active++;
5087 } else {
5088 goto purgatory;
5089 }
5090 break;
5091 }
5092 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5093 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5094 lp->phy[k].addr = i;
5095 lp->phy[k].id = id;
5096 lp->phy[k].spd.reg = GENERIC_REG;
5097 lp->phy[k].spd.mask = GENERIC_MASK;
5098 lp->phy[k].spd.value = GENERIC_VALUE;
5099 lp->mii_cnt++;
5100 lp->active++;
5101 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5102 j = de4x5_debug;
5103 de4x5_debug |= DEBUG_MII;
5104 de4x5_dbg_mii(dev, k);
5105 de4x5_debug = j;
5106 printk("\n");
5107 }
5108 }
5109 purgatory:
5110 lp->active = 0;
5111 if (lp->phy[0].id) {
5112 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) {
5113 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5114 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5115
5116 de4x5_dbg_mii(dev, k);
5117 }
5118 }
5119 if (!lp->mii_cnt) lp->useMII = false;
5120
5121 return lp->mii_cnt;
5122}
5123
5124static char *
5125build_setup_frame(struct net_device *dev, int mode)
5126{
5127 struct de4x5_private *lp = netdev_priv(dev);
5128 int i;
5129 char *pa = lp->setup_frame;
5130
5131
5132 if (mode == ALL) {
5133 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5134 }
5135
5136 if (lp->setup_f == HASH_PERF) {
5137 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5138 *(pa + i) = dev->dev_addr[i];
5139 if (i & 0x01) pa += 2;
5140 }
5141 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5142 } else {
5143 for (i=0; i<ETH_ALEN; i++) {
5144 *(pa + (i&1)) = dev->dev_addr[i];
5145 if (i & 0x01) pa += 4;
5146 }
5147 for (i=0; i<ETH_ALEN; i++) {
5148 *(pa + (i&1)) = (char) 0xff;
5149 if (i & 0x01) pa += 4;
5150 }
5151 }
5152
5153 return pa;
5154}
5155
5156static void
5157disable_ast(struct net_device *dev)
5158{
5159 struct de4x5_private *lp = netdev_priv(dev);
5160 del_timer_sync(&lp->timer);
5161}
5162
5163static long
5164de4x5_switch_mac_port(struct net_device *dev)
5165{
5166 struct de4x5_private *lp = netdev_priv(dev);
5167 u_long iobase = dev->base_addr;
5168 s32 omr;
5169
5170 STOP_DE4X5;
5171
5172
5173 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5174 OMR_FDX));
5175 omr |= lp->infoblock_csr6;
5176 if (omr & OMR_PS) omr |= OMR_HBD;
5177 outl(omr, DE4X5_OMR);
5178
5179
5180 RESET_DE4X5;
5181
5182
5183 if (lp->chipset == DC21140) {
5184 gep_wr(lp->cache.gepc, dev);
5185 gep_wr(lp->cache.gep, dev);
5186 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5187 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5188 }
5189
5190
5191 outl(omr, DE4X5_OMR);
5192
5193
5194 inl(DE4X5_MFC);
5195
5196 return omr;
5197}
5198
5199static void
5200gep_wr(s32 data, struct net_device *dev)
5201{
5202 struct de4x5_private *lp = netdev_priv(dev);
5203 u_long iobase = dev->base_addr;
5204
5205 if (lp->chipset == DC21140) {
5206 outl(data, DE4X5_GEP);
5207 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5208 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5209 }
5210
5211 return;
5212}
5213
5214static int
5215gep_rd(struct net_device *dev)
5216{
5217 struct de4x5_private *lp = netdev_priv(dev);
5218 u_long iobase = dev->base_addr;
5219
5220 if (lp->chipset == DC21140) {
5221 return inl(DE4X5_GEP);
5222 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5223 return (inl(DE4X5_SIGR) & 0x000fffff);
5224 }
5225
5226 return 0;
5227}
5228
5229static void
5230yawn(struct net_device *dev, int state)
5231{
5232 struct de4x5_private *lp = netdev_priv(dev);
5233 u_long iobase = dev->base_addr;
5234
5235 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5236
5237 if(lp->bus == EISA) {
5238 switch(state) {
5239 case WAKEUP:
5240 outb(WAKEUP, PCI_CFPM);
5241 mdelay(10);
5242 break;
5243
5244 case SNOOZE:
5245 outb(SNOOZE, PCI_CFPM);
5246 break;
5247
5248 case SLEEP:
5249 outl(0, DE4X5_SICR);
5250 outb(SLEEP, PCI_CFPM);
5251 break;
5252 }
5253 } else {
5254 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5255 switch(state) {
5256 case WAKEUP:
5257 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5258 mdelay(10);
5259 break;
5260
5261 case SNOOZE:
5262 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5263 break;
5264
5265 case SLEEP:
5266 outl(0, DE4X5_SICR);
5267 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5268 break;
5269 }
5270 }
5271
5272 return;
5273}
5274
5275static void
5276de4x5_parse_params(struct net_device *dev)
5277{
5278 struct de4x5_private *lp = netdev_priv(dev);
5279 char *p, *q, t;
5280
5281 lp->params.fdx = 0;
5282 lp->params.autosense = AUTO;
5283
5284 if (args == NULL) return;
5285
5286 if ((p = strstr(args, dev->name))) {
5287 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5288 t = *q;
5289 *q = '\0';
5290
5291 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5292
5293 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5294 if (strstr(p, "TP")) {
5295 lp->params.autosense = TP;
5296 } else if (strstr(p, "TP_NW")) {
5297 lp->params.autosense = TP_NW;
5298 } else if (strstr(p, "BNC")) {
5299 lp->params.autosense = BNC;
5300 } else if (strstr(p, "AUI")) {
5301 lp->params.autosense = AUI;
5302 } else if (strstr(p, "BNC_AUI")) {
5303 lp->params.autosense = BNC;
5304 } else if (strstr(p, "10Mb")) {
5305 lp->params.autosense = _10Mb;
5306 } else if (strstr(p, "100Mb")) {
5307 lp->params.autosense = _100Mb;
5308 } else if (strstr(p, "AUTO")) {
5309 lp->params.autosense = AUTO;
5310 }
5311 }
5312 *q = t;
5313 }
5314
5315 return;
5316}
5317
5318static void
5319de4x5_dbg_open(struct net_device *dev)
5320{
5321 struct de4x5_private *lp = netdev_priv(dev);
5322 int i;
5323
5324 if (de4x5_debug & DEBUG_OPEN) {
5325 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5326 printk("\tphysical address: ");
5327 for (i=0;i<6;i++) {
5328 printk("%2.2x:",(short)dev->dev_addr[i]);
5329 }
5330 printk("\n");
5331 printk("Descriptor head addresses:\n");
5332 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5333 printk("Descriptor addresses:\nRX: ");
5334 for (i=0;i<lp->rxRingSize-1;i++){
5335 if (i < 3) {
5336 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5337 }
5338 }
5339 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5340 printk("TX: ");
5341 for (i=0;i<lp->txRingSize-1;i++){
5342 if (i < 3) {
5343 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5344 }
5345 }
5346 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5347 printk("Descriptor buffers:\nRX: ");
5348 for (i=0;i<lp->rxRingSize-1;i++){
5349 if (i < 3) {
5350 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5351 }
5352 }
5353 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5354 printk("TX: ");
5355 for (i=0;i<lp->txRingSize-1;i++){
5356 if (i < 3) {
5357 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5358 }
5359 }
5360 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5361 printk("Ring size: \nRX: %d\nTX: %d\n",
5362 (short)lp->rxRingSize,
5363 (short)lp->txRingSize);
5364 }
5365
5366 return;
5367}
5368
5369static void
5370de4x5_dbg_mii(struct net_device *dev, int k)
5371{
5372 struct de4x5_private *lp = netdev_priv(dev);
5373 u_long iobase = dev->base_addr;
5374
5375 if (de4x5_debug & DEBUG_MII) {
5376 printk("\nMII device address: %d\n", lp->phy[k].addr);
5377 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5378 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5379 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5380 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5381 if (lp->phy[k].id != BROADCOM_T4) {
5382 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5383 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5384 }
5385 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5386 if (lp->phy[k].id != BROADCOM_T4) {
5387 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5388 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5389 } else {
5390 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5391 }
5392 }
5393
5394 return;
5395}
5396
5397static void
5398de4x5_dbg_media(struct net_device *dev)
5399{
5400 struct de4x5_private *lp = netdev_priv(dev);
5401
5402 if (lp->media != lp->c_media) {
5403 if (de4x5_debug & DEBUG_MEDIA) {
5404 printk("%s: media is %s%s\n", dev->name,
5405 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5406 (lp->media == TP ? "TP" :
5407 (lp->media == ANS ? "TP/Nway" :
5408 (lp->media == BNC ? "BNC" :
5409 (lp->media == AUI ? "AUI" :
5410 (lp->media == BNC_AUI ? "BNC/AUI" :
5411 (lp->media == EXT_SIA ? "EXT SIA" :
5412 (lp->media == _100Mb ? "100Mb/s" :
5413 (lp->media == _10Mb ? "10Mb/s" :
5414 "???"
5415 ))))))))), (lp->fdx?" full duplex.":"."));
5416 }
5417 lp->c_media = lp->media;
5418 }
5419
5420 return;
5421}
5422
5423static void
5424de4x5_dbg_srom(struct de4x5_srom *p)
5425{
5426 int i;
5427 DECLARE_MAC_BUF(mac);
5428
5429 if (de4x5_debug & DEBUG_SROM) {
5430 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5431 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5432 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5433 printk("SROM version: %02x\n", (u_char)(p->version));
5434 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5435
5436 printk("Hardware Address: %s\n", print_mac(mac, p->ieee_addr));
5437 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5438 for (i=0; i<64; i++) {
5439 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5440 }
5441 }
5442
5443 return;
5444}
5445
5446static void
5447de4x5_dbg_rx(struct sk_buff *skb, int len)
5448{
5449 int i, j;
5450 DECLARE_MAC_BUF(mac);
5451 DECLARE_MAC_BUF(mac2);
5452
5453 if (de4x5_debug & DEBUG_RX) {
5454 printk("R: %s <- %s len/SAP:%02x%02x [%d]\n",
5455 print_mac(mac, skb->data), print_mac(mac2, &skb->data[6]),
5456 (u_char)skb->data[12],
5457 (u_char)skb->data[13],
5458 len);
5459 for (j=0; len>0;j+=16, len-=16) {
5460 printk(" %03x: ",j);
5461 for (i=0; i<16 && i<len; i++) {
5462 printk("%02x ",(u_char)skb->data[i+j]);
5463 }
5464 printk("\n");
5465 }
5466 }
5467
5468 return;
5469}
5470
5471
5472
5473
5474
5475
5476static int
5477de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5478{
5479 struct de4x5_private *lp = netdev_priv(dev);
5480 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5481 u_long iobase = dev->base_addr;
5482 int i, j, status = 0;
5483 s32 omr;
5484 union {
5485 u8 addr[144];
5486 u16 sval[72];
5487 u32 lval[36];
5488 } tmp;
5489 u_long flags = 0;
5490
5491 switch(ioc->cmd) {
5492 case DE4X5_GET_HWADDR:
5493 ioc->len = ETH_ALEN;
5494 for (i=0; i<ETH_ALEN; i++) {
5495 tmp.addr[i] = dev->dev_addr[i];
5496 }
5497 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5498 break;
5499
5500 case DE4X5_SET_HWADDR:
5501 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5502 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5503 if (netif_queue_stopped(dev))
5504 return -EBUSY;
5505 netif_stop_queue(dev);
5506 for (i=0; i<ETH_ALEN; i++) {
5507 dev->dev_addr[i] = tmp.addr[i];
5508 }
5509 build_setup_frame(dev, PHYS_ADDR_ONLY);
5510
5511 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5512 SETUP_FRAME_LEN, (struct sk_buff *)1);
5513 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5514 outl(POLL_DEMAND, DE4X5_TPD);
5515 netif_wake_queue(dev);
5516 break;
5517
5518 case DE4X5_SET_PROM:
5519 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5520 omr = inl(DE4X5_OMR);
5521 omr |= OMR_PR;
5522 outl(omr, DE4X5_OMR);
5523 dev->flags |= IFF_PROMISC;
5524 break;
5525
5526 case DE4X5_CLR_PROM:
5527 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5528 omr = inl(DE4X5_OMR);
5529 omr &= ~OMR_PR;
5530 outl(omr, DE4X5_OMR);
5531 dev->flags &= ~IFF_PROMISC;
5532 break;
5533
5534 case DE4X5_SAY_BOO:
5535 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5536 printk("%s: Boo!\n", dev->name);
5537 break;
5538
5539 case DE4X5_MCA_EN:
5540 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5541 omr = inl(DE4X5_OMR);
5542 omr |= OMR_PM;
5543 outl(omr, DE4X5_OMR);
5544 break;
5545
5546 case DE4X5_GET_STATS:
5547 {
5548 struct pkt_stats statbuf;
5549 ioc->len = sizeof(statbuf);
5550 spin_lock_irqsave(&lp->lock, flags);
5551 memcpy(&statbuf, &lp->pktStats, ioc->len);
5552 spin_unlock_irqrestore(&lp->lock, flags);
5553 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5554 return -EFAULT;
5555 break;
5556 }
5557 case DE4X5_CLR_STATS:
5558 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5559 spin_lock_irqsave(&lp->lock, flags);
5560 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5561 spin_unlock_irqrestore(&lp->lock, flags);
5562 break;
5563
5564 case DE4X5_GET_OMR:
5565 tmp.addr[0] = inl(DE4X5_OMR);
5566 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5567 break;
5568
5569 case DE4X5_SET_OMR:
5570 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5571 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5572 outl(tmp.addr[0], DE4X5_OMR);
5573 break;
5574
5575 case DE4X5_GET_REG:
5576 j = 0;
5577 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5578 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5579 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5580 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5581 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5582 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5583 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5584 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5585 ioc->len = j;
5586 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5587 break;
5588
5589#define DE4X5_DUMP 0x0f
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679 default:
5680 return -EOPNOTSUPP;
5681 }
5682
5683 return status;
5684}
5685
5686static int __init de4x5_module_init (void)
5687{
5688 int err = 0;
5689
5690#ifdef CONFIG_PCI
5691 err = pci_register_driver(&de4x5_pci_driver);
5692#endif
5693#ifdef CONFIG_EISA
5694 err |= eisa_driver_register (&de4x5_eisa_driver);
5695#endif
5696
5697 return err;
5698}
5699
5700static void __exit de4x5_module_exit (void)
5701{
5702#ifdef CONFIG_PCI
5703 pci_unregister_driver (&de4x5_pci_driver);
5704#endif
5705#ifdef CONFIG_EISA
5706 eisa_driver_unregister (&de4x5_eisa_driver);
5707#endif
5708}
5709
5710module_init (de4x5_module_init);
5711module_exit (de4x5_module_exit);
5712