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48#include <linux/module.h>
49#include <linux/types.h>
50#include <linux/init.h>
51#include <linux/mm.h>
52#include <linux/errno.h>
53#include <linux/ioport.h>
54#include <linux/pci.h>
55#include <linux/kernel.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/skbuff.h>
59#include <linux/delay.h>
60#include <linux/timer.h>
61#include <linux/slab.h>
62#include <linux/interrupt.h>
63#include <linux/string.h>
64#include <linux/wait.h>
65#include <asm/io.h>
66#include <linux/if.h>
67#include <asm/uaccess.h>
68#include <linux/proc_fs.h>
69#include <linux/inetdevice.h>
70#include <linux/reboot.h>
71#include <linux/ethtool.h>
72#include <linux/mii.h>
73#include <linux/in.h>
74#include <linux/if_arp.h>
75#include <linux/if_vlan.h>
76#include <linux/ip.h>
77#include <linux/tcp.h>
78#include <linux/udp.h>
79#include <linux/crc-ccitt.h>
80#include <linux/crc32.h>
81
82#include "via-velocity.h"
83
84
85static int velocity_nics = 0;
86static int msglevel = MSG_LEVEL_INFO;
87
88
89
90
91
92
93
94
95
96
97static void mac_get_cam_mask(struct mac_regs __iomem * regs, u8 * mask)
98{
99 int i;
100
101
102 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
103
104 writeb(0, ®s->CAMADDR);
105
106
107 for (i = 0; i < 8; i++)
108 *mask++ = readb(&(regs->MARCAM[i]));
109
110
111 writeb(0, ®s->CAMADDR);
112
113
114 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
115
116}
117
118
119
120
121
122
123
124
125
126
127static void mac_set_cam_mask(struct mac_regs __iomem * regs, u8 * mask)
128{
129 int i;
130
131 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
132
133 writeb(CAMADDR_CAMEN, ®s->CAMADDR);
134
135 for (i = 0; i < 8; i++) {
136 writeb(*mask++, &(regs->MARCAM[i]));
137 }
138
139 writeb(0, ®s->CAMADDR);
140
141
142 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
143}
144
145static void mac_set_vlan_cam_mask(struct mac_regs __iomem * regs, u8 * mask)
146{
147 int i;
148
149 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
150
151 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, ®s->CAMADDR);
152
153 for (i = 0; i < 8; i++) {
154 writeb(*mask++, &(regs->MARCAM[i]));
155 }
156
157 writeb(0, ®s->CAMADDR);
158
159
160 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
161}
162
163
164
165
166
167
168
169
170
171
172static void mac_set_cam(struct mac_regs __iomem * regs, int idx, const u8 *addr)
173{
174 int i;
175
176
177 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
178
179 idx &= (64 - 1);
180
181 writeb(CAMADDR_CAMEN | idx, ®s->CAMADDR);
182
183 for (i = 0; i < 6; i++) {
184 writeb(*addr++, &(regs->MARCAM[i]));
185 }
186 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
187
188 udelay(10);
189
190 writeb(0, ®s->CAMADDR);
191
192
193 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
194}
195
196static void mac_set_vlan_cam(struct mac_regs __iomem * regs, int idx,
197 const u8 *addr)
198{
199
200
201 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
202
203 idx &= (64 - 1);
204
205 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, ®s->CAMADDR);
206 writew(*((u16 *) addr), ®s->MARCAM[0]);
207
208 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
209
210 udelay(10);
211
212 writeb(0, ®s->CAMADDR);
213
214
215 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
216}
217
218
219
220
221
222
223
224
225
226
227
228static void mac_wol_reset(struct mac_regs __iomem * regs)
229{
230
231
232 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, ®s->STICKHW);
233
234 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
235
236 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, ®s->CHIPGCR);
237 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
238
239 writeb(WOLCFG_PMEOVR, ®s->WOLCFGClr);
240
241 writew(0xFFFF, ®s->WOLCRClr);
242
243 writew(0xFFFF, ®s->WOLSRClr);
244}
245
246static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
247static const struct ethtool_ops velocity_ethtool_ops;
248
249
250
251
252
253MODULE_AUTHOR("VIA Networking Technologies, Inc.");
254MODULE_LICENSE("GPL");
255MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
256
257#define VELOCITY_PARAM(N,D) \
258 static int N[MAX_UNITS]=OPTION_DEFAULT;\
259 module_param_array(N, int, NULL, 0); \
260 MODULE_PARM_DESC(N, D);
261
262#define RX_DESC_MIN 64
263#define RX_DESC_MAX 255
264#define RX_DESC_DEF 64
265VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
266
267#define TX_DESC_MIN 16
268#define TX_DESC_MAX 256
269#define TX_DESC_DEF 64
270VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
271
272#define RX_THRESH_MIN 0
273#define RX_THRESH_MAX 3
274#define RX_THRESH_DEF 0
275
276
277
278
279
280
281VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
282
283#define DMA_LENGTH_MIN 0
284#define DMA_LENGTH_MAX 7
285#define DMA_LENGTH_DEF 0
286
287
288
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291
292
293
294
295
296
297VELOCITY_PARAM(DMA_length, "DMA length");
298
299#define IP_ALIG_DEF 0
300
301
302
303
304
305
306VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
307
308#define TX_CSUM_DEF 1
309
310
311
312
313
314VELOCITY_PARAM(txcsum_offload, "Enable transmit packet checksum offload");
315
316#define FLOW_CNTL_DEF 1
317#define FLOW_CNTL_MIN 1
318#define FLOW_CNTL_MAX 5
319
320
321
322
323
324
325
326
327VELOCITY_PARAM(flow_control, "Enable flow control ability");
328
329#define MED_LNK_DEF 0
330#define MED_LNK_MIN 0
331#define MED_LNK_MAX 4
332
333
334
335
336
337
338
339
340
341
342
343VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
344
345#define VAL_PKT_LEN_DEF 0
346
347
348
349
350VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
351
352#define WOL_OPT_DEF 0
353#define WOL_OPT_MIN 0
354#define WOL_OPT_MAX 7
355
356
357
358
359
360
361
362VELOCITY_PARAM(wol_opts, "Wake On Lan options");
363
364#define INT_WORKS_DEF 20
365#define INT_WORKS_MIN 10
366#define INT_WORKS_MAX 64
367
368VELOCITY_PARAM(int_works, "Number of packets per interrupt services");
369
370static int rx_copybreak = 200;
371module_param(rx_copybreak, int, 0644);
372MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
373
374static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
375 const struct velocity_info_tbl *info);
376static int velocity_get_pci_info(struct velocity_info *, struct pci_dev *pdev);
377static void velocity_print_info(struct velocity_info *vptr);
378static int velocity_open(struct net_device *dev);
379static int velocity_change_mtu(struct net_device *dev, int mtu);
380static int velocity_xmit(struct sk_buff *skb, struct net_device *dev);
381static int velocity_intr(int irq, void *dev_instance);
382static void velocity_set_multi(struct net_device *dev);
383static struct net_device_stats *velocity_get_stats(struct net_device *dev);
384static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
385static int velocity_close(struct net_device *dev);
386static int velocity_receive_frame(struct velocity_info *, int idx);
387static int velocity_alloc_rx_buf(struct velocity_info *, int idx);
388static void velocity_free_rd_ring(struct velocity_info *vptr);
389static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_info *);
390static int velocity_soft_reset(struct velocity_info *vptr);
391static void mii_init(struct velocity_info *vptr, u32 mii_status);
392static u32 velocity_get_link(struct net_device *dev);
393static u32 velocity_get_opt_media_mode(struct velocity_info *vptr);
394static void velocity_print_link_status(struct velocity_info *vptr);
395static void safe_disable_mii_autopoll(struct mac_regs __iomem * regs);
396static void velocity_shutdown(struct velocity_info *vptr);
397static void enable_flow_control_ability(struct velocity_info *vptr);
398static void enable_mii_autopoll(struct mac_regs __iomem * regs);
399static int velocity_mii_read(struct mac_regs __iomem *, u8 byIdx, u16 * pdata);
400static int velocity_mii_write(struct mac_regs __iomem *, u8 byMiiAddr, u16 data);
401static u32 mii_check_media_mode(struct mac_regs __iomem * regs);
402static u32 check_connection_type(struct mac_regs __iomem * regs);
403static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status);
404
405#ifdef CONFIG_PM
406
407static int velocity_suspend(struct pci_dev *pdev, pm_message_t state);
408static int velocity_resume(struct pci_dev *pdev);
409
410static DEFINE_SPINLOCK(velocity_dev_list_lock);
411static LIST_HEAD(velocity_dev_list);
412
413#endif
414
415#if defined(CONFIG_PM) && defined(CONFIG_INET)
416
417static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr);
418
419static struct notifier_block velocity_inetaddr_notifier = {
420 .notifier_call = velocity_netdev_event,
421};
422
423static void velocity_register_notifier(void)
424{
425 register_inetaddr_notifier(&velocity_inetaddr_notifier);
426}
427
428static void velocity_unregister_notifier(void)
429{
430 unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
431}
432
433#else
434
435#define velocity_register_notifier() do {} while (0)
436#define velocity_unregister_notifier() do {} while (0)
437
438#endif
439
440
441
442
443
444static const struct velocity_info_tbl chip_info_table[] __devinitdata = {
445 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
446 { }
447};
448
449
450
451
452
453
454static const struct pci_device_id velocity_id_table[] __devinitdata = {
455 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
456 { }
457};
458
459MODULE_DEVICE_TABLE(pci, velocity_id_table);
460
461
462
463
464
465
466
467
468
469static const char __devinit *get_chip_name(enum chip_type chip_id)
470{
471 int i;
472 for (i = 0; chip_info_table[i].name != NULL; i++)
473 if (chip_info_table[i].chip_id == chip_id)
474 break;
475 return chip_info_table[i].name;
476}
477
478
479
480
481
482
483
484
485
486
487static void __devexit velocity_remove1(struct pci_dev *pdev)
488{
489 struct net_device *dev = pci_get_drvdata(pdev);
490 struct velocity_info *vptr = netdev_priv(dev);
491
492#ifdef CONFIG_PM
493 unsigned long flags;
494
495 spin_lock_irqsave(&velocity_dev_list_lock, flags);
496 if (!list_empty(&velocity_dev_list))
497 list_del(&vptr->list);
498 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
499#endif
500 unregister_netdev(dev);
501 iounmap(vptr->mac_regs);
502 pci_release_regions(pdev);
503 pci_disable_device(pdev);
504 pci_set_drvdata(pdev, NULL);
505 free_netdev(dev);
506
507 velocity_nics--;
508}
509
510
511
512
513
514
515
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517
518
519
520
521
522
523
524
525static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, char *devname)
526{
527 if (val == -1)
528 *opt = def;
529 else if (val < min || val > max) {
530 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
531 devname, name, min, max);
532 *opt = def;
533 } else {
534 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
535 devname, name, val);
536 *opt = val;
537 }
538}
539
540
541
542
543
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545
546
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548
549
550
551
552
553
554static void __devinit velocity_set_bool_opt(u32 * opt, int val, int def, u32 flag, char *name, char *devname)
555{
556 (*opt) &= (~flag);
557 if (val == -1)
558 *opt |= (def ? flag : 0);
559 else if (val < 0 || val > 1) {
560 printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
561 devname, name);
562 *opt |= (def ? flag : 0);
563 } else {
564 printk(KERN_INFO "%s: set parameter %s to %s\n",
565 devname, name, val ? "TRUE" : "FALSE");
566 *opt |= (val ? flag : 0);
567 }
568}
569
570
571
572
573
574
575
576
577
578
579
580static void __devinit velocity_get_options(struct velocity_opt *opts, int index, char *devname)
581{
582
583 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
584 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
585 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
586 velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
587
588 velocity_set_bool_opt(&opts->flags, txcsum_offload[index], TX_CSUM_DEF, VELOCITY_FLAGS_TX_CSUM, "txcsum_offload", devname);
589 velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
590 velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
591 velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
592 velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
593 velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
594 velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
595 opts->numrx = (opts->numrx & ~3);
596}
597
598
599
600
601
602
603
604
605
606static void velocity_init_cam_filter(struct velocity_info *vptr)
607{
608 struct mac_regs __iomem * regs = vptr->mac_regs;
609 unsigned short vid;
610
611
612 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, ®s->MCFG);
613 WORD_REG_BITS_ON(MCFG_VIDFR, ®s->MCFG);
614
615
616 memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
617 memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
618 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
619 mac_set_cam_mask(regs, vptr->mCAMmask);
620
621
622 if (vptr->vlgrp) {
623 for (vid = 0; vid < VLAN_VID_MASK; vid++) {
624 if (vlan_group_get_device(vptr->vlgrp, vid)) {
625
626
627
628 if (vid != 0)
629 WORD_REG_BITS_ON(MCFG_RTGOPT, ®s->MCFG);
630
631 mac_set_vlan_cam(regs, 0, (u8 *) &vid);
632 }
633 }
634 vptr->vCAMmask[0] |= 1;
635 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
636 } else {
637 u16 temp = 0;
638 mac_set_vlan_cam(regs, 0, (u8 *) &temp);
639 temp = 1;
640 mac_set_vlan_cam_mask(regs, (u8 *) &temp);
641 }
642}
643
644static void velocity_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
645{
646 struct velocity_info *vptr = netdev_priv(dev);
647
648 spin_lock_irq(&vptr->lock);
649 velocity_init_cam_filter(vptr);
650 spin_unlock_irq(&vptr->lock);
651}
652
653static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
654{
655 struct velocity_info *vptr = netdev_priv(dev);
656
657 spin_lock_irq(&vptr->lock);
658 vlan_group_set_device(vptr->vlgrp, vid, NULL);
659 velocity_init_cam_filter(vptr);
660 spin_unlock_irq(&vptr->lock);
661}
662
663
664
665
666
667
668
669
670
671
672static void velocity_rx_reset(struct velocity_info *vptr)
673{
674
675 struct mac_regs __iomem * regs = vptr->mac_regs;
676 int i;
677
678 vptr->rd_dirty = vptr->rd_filled = vptr->rd_curr = 0;
679
680
681
682
683 for (i = 0; i < vptr->options.numrx; ++i)
684 vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC;
685
686 writew(vptr->options.numrx, ®s->RBRDU);
687 writel(vptr->rd_pool_dma, ®s->RDBaseLo);
688 writew(0, ®s->RDIdx);
689 writew(vptr->options.numrx - 1, ®s->RDCSize);
690}
691
692
693
694
695
696
697
698
699
700
701static void velocity_init_registers(struct velocity_info *vptr,
702 enum velocity_init_type type)
703{
704 struct mac_regs __iomem * regs = vptr->mac_regs;
705 int i, mii_status;
706
707 mac_wol_reset(regs);
708
709 switch (type) {
710 case VELOCITY_INIT_RESET:
711 case VELOCITY_INIT_WOL:
712
713 netif_stop_queue(vptr->dev);
714
715
716
717
718 velocity_rx_reset(vptr);
719 mac_rx_queue_run(regs);
720 mac_rx_queue_wake(regs);
721
722 mii_status = velocity_get_opt_media_mode(vptr);
723 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
724 velocity_print_link_status(vptr);
725 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
726 netif_wake_queue(vptr->dev);
727 }
728
729 enable_flow_control_ability(vptr);
730
731 mac_clear_isr(regs);
732 writel(CR0_STOP, ®s->CR0Clr);
733 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
734 ®s->CR0Set);
735
736 break;
737
738 case VELOCITY_INIT_COLD:
739 default:
740
741
742
743 velocity_soft_reset(vptr);
744 mdelay(5);
745
746 mac_eeprom_reload(regs);
747 for (i = 0; i < 6; i++) {
748 writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
749 }
750
751
752
753 BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
754 mac_set_rx_thresh(regs, vptr->options.rx_thresh);
755 mac_set_dma_length(regs, vptr->options.DMA_length);
756
757 writeb(WOLCFG_SAM | WOLCFG_SAB, ®s->WOLCFGSet);
758
759
760
761 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), ®s->CFGB);
762
763
764
765
766 velocity_init_cam_filter(vptr);
767
768
769
770
771 velocity_set_multi(vptr->dev);
772
773
774
775
776 enable_mii_autopoll(regs);
777
778 vptr->int_mask = INT_MASK_DEF;
779
780 writel(cpu_to_le32(vptr->rd_pool_dma), ®s->RDBaseLo);
781 writew(vptr->options.numrx - 1, ®s->RDCSize);
782 mac_rx_queue_run(regs);
783 mac_rx_queue_wake(regs);
784
785 writew(vptr->options.numtx - 1, ®s->TDCSize);
786
787 for (i = 0; i < vptr->num_txq; i++) {
788 writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i]));
789 mac_tx_queue_run(regs, i);
790 }
791
792 init_flow_control_register(vptr);
793
794 writel(CR0_STOP, ®s->CR0Clr);
795 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), ®s->CR0Set);
796
797 mii_status = velocity_get_opt_media_mode(vptr);
798 netif_stop_queue(vptr->dev);
799
800 mii_init(vptr, mii_status);
801
802 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
803 velocity_print_link_status(vptr);
804 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
805 netif_wake_queue(vptr->dev);
806 }
807
808 enable_flow_control_ability(vptr);
809 mac_hw_mibs_init(regs);
810 mac_write_int_mask(vptr->int_mask, regs);
811 mac_clear_isr(regs);
812
813 }
814}
815
816
817
818
819
820
821
822
823
824static int velocity_soft_reset(struct velocity_info *vptr)
825{
826 struct mac_regs __iomem * regs = vptr->mac_regs;
827 int i = 0;
828
829 writel(CR0_SFRST, ®s->CR0Set);
830
831 for (i = 0; i < W_MAX_TIMEOUT; i++) {
832 udelay(5);
833 if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, ®s->CR0Set))
834 break;
835 }
836
837 if (i == W_MAX_TIMEOUT) {
838 writel(CR0_FORSRST, ®s->CR0Set);
839
840
841 mdelay(2);
842 }
843 return 0;
844}
845
846
847
848
849
850
851
852
853
854
855static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_device_id *ent)
856{
857 static int first = 1;
858 struct net_device *dev;
859 int i;
860 const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
861 struct velocity_info *vptr;
862 struct mac_regs __iomem * regs;
863 int ret = -ENOMEM;
864
865
866
867
868 if (velocity_nics >= MAX_UNITS) {
869 dev_notice(&pdev->dev, "already found %d NICs.\n",
870 velocity_nics);
871 return -ENODEV;
872 }
873
874 dev = alloc_etherdev(sizeof(struct velocity_info));
875 if (!dev) {
876 dev_err(&pdev->dev, "allocate net device failed.\n");
877 goto out;
878 }
879
880
881
882 SET_NETDEV_DEV(dev, &pdev->dev);
883 vptr = netdev_priv(dev);
884
885
886 if (first) {
887 printk(KERN_INFO "%s Ver. %s\n",
888 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
889 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
890 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
891 first = 0;
892 }
893
894 velocity_init_info(pdev, vptr, info);
895
896 vptr->dev = dev;
897
898 dev->irq = pdev->irq;
899
900 ret = pci_enable_device(pdev);
901 if (ret < 0)
902 goto err_free_dev;
903
904 ret = velocity_get_pci_info(vptr, pdev);
905 if (ret < 0) {
906
907 goto err_disable;
908 }
909
910 ret = pci_request_regions(pdev, VELOCITY_NAME);
911 if (ret < 0) {
912 dev_err(&pdev->dev, "No PCI resources.\n");
913 goto err_disable;
914 }
915
916 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
917 if (regs == NULL) {
918 ret = -EIO;
919 goto err_release_res;
920 }
921
922 vptr->mac_regs = regs;
923
924 mac_wol_reset(regs);
925
926 dev->base_addr = vptr->ioaddr;
927
928 for (i = 0; i < 6; i++)
929 dev->dev_addr[i] = readb(®s->PAR[i]);
930
931
932 velocity_get_options(&vptr->options, velocity_nics, dev->name);
933
934
935
936
937
938 vptr->options.flags &= info->flags;
939
940
941
942
943
944 vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
945
946 vptr->wol_opts = vptr->options.wol_opts;
947 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
948
949 vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
950
951 dev->irq = pdev->irq;
952 dev->open = velocity_open;
953 dev->hard_start_xmit = velocity_xmit;
954 dev->stop = velocity_close;
955 dev->get_stats = velocity_get_stats;
956 dev->set_multicast_list = velocity_set_multi;
957 dev->do_ioctl = velocity_ioctl;
958 dev->ethtool_ops = &velocity_ethtool_ops;
959 dev->change_mtu = velocity_change_mtu;
960
961 dev->vlan_rx_add_vid = velocity_vlan_rx_add_vid;
962 dev->vlan_rx_kill_vid = velocity_vlan_rx_kill_vid;
963
964#ifdef VELOCITY_ZERO_COPY_SUPPORT
965 dev->features |= NETIF_F_SG;
966#endif
967 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER;
968
969 if (vptr->flags & VELOCITY_FLAGS_TX_CSUM)
970 dev->features |= NETIF_F_IP_CSUM;
971
972 ret = register_netdev(dev);
973 if (ret < 0)
974 goto err_iounmap;
975
976 if (velocity_get_link(dev))
977 netif_carrier_off(dev);
978
979 velocity_print_info(vptr);
980 pci_set_drvdata(pdev, dev);
981
982
983
984 pci_set_power_state(pdev, PCI_D3hot);
985#ifdef CONFIG_PM
986 {
987 unsigned long flags;
988
989 spin_lock_irqsave(&velocity_dev_list_lock, flags);
990 list_add(&vptr->list, &velocity_dev_list);
991 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
992 }
993#endif
994 velocity_nics++;
995out:
996 return ret;
997
998err_iounmap:
999 iounmap(regs);
1000err_release_res:
1001 pci_release_regions(pdev);
1002err_disable:
1003 pci_disable_device(pdev);
1004err_free_dev:
1005 free_netdev(dev);
1006 goto out;
1007}
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017static void __devinit velocity_print_info(struct velocity_info *vptr)
1018{
1019 struct net_device *dev = vptr->dev;
1020
1021 printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
1022 printk(KERN_INFO "%s: Ethernet Address: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
1023 dev->name,
1024 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1025 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1026}
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038static void __devinit velocity_init_info(struct pci_dev *pdev,
1039 struct velocity_info *vptr,
1040 const struct velocity_info_tbl *info)
1041{
1042 memset(vptr, 0, sizeof(struct velocity_info));
1043
1044 vptr->pdev = pdev;
1045 vptr->chip_id = info->chip_id;
1046 vptr->num_txq = info->txqueue;
1047 vptr->multicast_limit = MCAM_SIZE;
1048 spin_lock_init(&vptr->lock);
1049 INIT_LIST_HEAD(&vptr->list);
1050}
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
1062{
1063 vptr->rev_id = pdev->revision;
1064
1065 pci_set_master(pdev);
1066
1067 vptr->ioaddr = pci_resource_start(pdev, 0);
1068 vptr->memaddr = pci_resource_start(pdev, 1);
1069
1070 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
1071 dev_err(&pdev->dev,
1072 "region #0 is not an I/O resource, aborting.\n");
1073 return -EINVAL;
1074 }
1075
1076 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
1077 dev_err(&pdev->dev,
1078 "region #1 is an I/O resource, aborting.\n");
1079 return -EINVAL;
1080 }
1081
1082 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
1083 dev_err(&pdev->dev, "region #1 is too small.\n");
1084 return -EINVAL;
1085 }
1086 vptr->pdev = pdev;
1087
1088 return 0;
1089}
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099static int velocity_init_rings(struct velocity_info *vptr)
1100{
1101 int i;
1102 unsigned int psize;
1103 unsigned int tsize;
1104 dma_addr_t pool_dma;
1105 u8 *pool;
1106
1107
1108
1109
1110
1111 psize = vptr->options.numrx * sizeof(struct rx_desc) +
1112 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
1113
1114
1115
1116
1117
1118 pool = pci_alloc_consistent(vptr->pdev, psize, &pool_dma);
1119
1120 if (pool == NULL) {
1121 printk(KERN_ERR "%s : DMA memory allocation failed.\n",
1122 vptr->dev->name);
1123 return -ENOMEM;
1124 }
1125
1126 memset(pool, 0, psize);
1127
1128 vptr->rd_ring = (struct rx_desc *) pool;
1129
1130 vptr->rd_pool_dma = pool_dma;
1131
1132 tsize = vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq;
1133 vptr->tx_bufs = pci_alloc_consistent(vptr->pdev, tsize,
1134 &vptr->tx_bufs_dma);
1135
1136 if (vptr->tx_bufs == NULL) {
1137 printk(KERN_ERR "%s: DMA memory allocation failed.\n",
1138 vptr->dev->name);
1139 pci_free_consistent(vptr->pdev, psize, pool, pool_dma);
1140 return -ENOMEM;
1141 }
1142
1143 memset(vptr->tx_bufs, 0, vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq);
1144
1145 i = vptr->options.numrx * sizeof(struct rx_desc);
1146 pool += i;
1147 pool_dma += i;
1148 for (i = 0; i < vptr->num_txq; i++) {
1149 int offset = vptr->options.numtx * sizeof(struct tx_desc);
1150
1151 vptr->td_pool_dma[i] = pool_dma;
1152 vptr->td_rings[i] = (struct tx_desc *) pool;
1153 pool += offset;
1154 pool_dma += offset;
1155 }
1156 return 0;
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166static void velocity_free_rings(struct velocity_info *vptr)
1167{
1168 int size;
1169
1170 size = vptr->options.numrx * sizeof(struct rx_desc) +
1171 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
1172
1173 pci_free_consistent(vptr->pdev, size, vptr->rd_ring, vptr->rd_pool_dma);
1174
1175 size = vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq;
1176
1177 pci_free_consistent(vptr->pdev, size, vptr->tx_bufs, vptr->tx_bufs_dma);
1178}
1179
1180static inline void velocity_give_many_rx_descs(struct velocity_info *vptr)
1181{
1182 struct mac_regs __iomem *regs = vptr->mac_regs;
1183 int avail, dirty, unusable;
1184
1185
1186
1187
1188
1189 if (vptr->rd_filled < 4)
1190 return;
1191
1192 wmb();
1193
1194 unusable = vptr->rd_filled & 0x0003;
1195 dirty = vptr->rd_dirty - unusable;
1196 for (avail = vptr->rd_filled & 0xfffc; avail; avail--) {
1197 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1198 vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC;
1199 }
1200
1201 writew(vptr->rd_filled & 0xfffc, ®s->RBRDU);
1202 vptr->rd_filled = unusable;
1203}
1204
1205static int velocity_rx_refill(struct velocity_info *vptr)
1206{
1207 int dirty = vptr->rd_dirty, done = 0, ret = 0;
1208
1209 do {
1210 struct rx_desc *rd = vptr->rd_ring + dirty;
1211
1212
1213 if (rd->rdesc0.owner == OWNED_BY_NIC)
1214 break;
1215
1216 if (!vptr->rd_info[dirty].skb) {
1217 ret = velocity_alloc_rx_buf(vptr, dirty);
1218 if (ret < 0)
1219 break;
1220 }
1221 done++;
1222 dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1223 } while (dirty != vptr->rd_curr);
1224
1225 if (done) {
1226 vptr->rd_dirty = dirty;
1227 vptr->rd_filled += done;
1228 velocity_give_many_rx_descs(vptr);
1229 }
1230
1231 return ret;
1232}
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242static int velocity_init_rd_ring(struct velocity_info *vptr)
1243{
1244 int ret;
1245 int mtu = vptr->dev->mtu;
1246
1247 vptr->rx_buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1248
1249 vptr->rd_info = kcalloc(vptr->options.numrx,
1250 sizeof(struct velocity_rd_info), GFP_KERNEL);
1251 if (!vptr->rd_info)
1252 return -ENOMEM;
1253
1254 vptr->rd_filled = vptr->rd_dirty = vptr->rd_curr = 0;
1255
1256 ret = velocity_rx_refill(vptr);
1257 if (ret < 0) {
1258 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1259 "%s: failed to allocate RX buffer.\n", vptr->dev->name);
1260 velocity_free_rd_ring(vptr);
1261 }
1262
1263 return ret;
1264}
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274static void velocity_free_rd_ring(struct velocity_info *vptr)
1275{
1276 int i;
1277
1278 if (vptr->rd_info == NULL)
1279 return;
1280
1281 for (i = 0; i < vptr->options.numrx; i++) {
1282 struct velocity_rd_info *rd_info = &(vptr->rd_info[i]);
1283 struct rx_desc *rd = vptr->rd_ring + i;
1284
1285 memset(rd, 0, sizeof(*rd));
1286
1287 if (!rd_info->skb)
1288 continue;
1289 pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx_buf_sz,
1290 PCI_DMA_FROMDEVICE);
1291 rd_info->skb_dma = (dma_addr_t) NULL;
1292
1293 dev_kfree_skb(rd_info->skb);
1294 rd_info->skb = NULL;
1295 }
1296
1297 kfree(vptr->rd_info);
1298 vptr->rd_info = NULL;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310static int velocity_init_td_ring(struct velocity_info *vptr)
1311{
1312 int i, j;
1313 dma_addr_t curr;
1314 struct tx_desc *td;
1315 struct velocity_td_info *td_info;
1316
1317
1318 for (j = 0; j < vptr->num_txq; j++) {
1319 curr = vptr->td_pool_dma[j];
1320
1321 vptr->td_infos[j] = kcalloc(vptr->options.numtx,
1322 sizeof(struct velocity_td_info),
1323 GFP_KERNEL);
1324 if (!vptr->td_infos[j]) {
1325 while(--j >= 0)
1326 kfree(vptr->td_infos[j]);
1327 return -ENOMEM;
1328 }
1329
1330 for (i = 0; i < vptr->options.numtx; i++, curr += sizeof(struct tx_desc)) {
1331 td = &(vptr->td_rings[j][i]);
1332 td_info = &(vptr->td_infos[j][i]);
1333 td_info->buf = vptr->tx_bufs +
1334 (j * vptr->options.numtx + i) * PKT_BUF_SZ;
1335 td_info->buf_dma = vptr->tx_bufs_dma +
1336 (j * vptr->options.numtx + i) * PKT_BUF_SZ;
1337 }
1338 vptr->td_tail[j] = vptr->td_curr[j] = vptr->td_used[j] = 0;
1339 }
1340 return 0;
1341}
1342
1343
1344
1345
1346
1347static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1348 int q, int n)
1349{
1350 struct velocity_td_info * td_info = &(vptr->td_infos[q][n]);
1351 int i;
1352
1353 if (td_info == NULL)
1354 return;
1355
1356 if (td_info->skb) {
1357 for (i = 0; i < td_info->nskb_dma; i++)
1358 {
1359 if (td_info->skb_dma[i]) {
1360 pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
1361 td_info->skb->len, PCI_DMA_TODEVICE);
1362 td_info->skb_dma[i] = (dma_addr_t) NULL;
1363 }
1364 }
1365 dev_kfree_skb(td_info->skb);
1366 td_info->skb = NULL;
1367 }
1368}
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static void velocity_free_td_ring(struct velocity_info *vptr)
1379{
1380 int i, j;
1381
1382 for (j = 0; j < vptr->num_txq; j++) {
1383 if (vptr->td_infos[j] == NULL)
1384 continue;
1385 for (i = 0; i < vptr->options.numtx; i++) {
1386 velocity_free_td_ring_entry(vptr, j, i);
1387
1388 }
1389 kfree(vptr->td_infos[j]);
1390 vptr->td_infos[j] = NULL;
1391 }
1392}
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static int velocity_rx_srv(struct velocity_info *vptr, int status)
1405{
1406 struct net_device_stats *stats = &vptr->stats;
1407 int rd_curr = vptr->rd_curr;
1408 int works = 0;
1409
1410 do {
1411 struct rx_desc *rd = vptr->rd_ring + rd_curr;
1412
1413 if (!vptr->rd_info[rd_curr].skb)
1414 break;
1415
1416 if (rd->rdesc0.owner == OWNED_BY_NIC)
1417 break;
1418
1419 rmb();
1420
1421
1422
1423
1424 if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) {
1425 if (velocity_receive_frame(vptr, rd_curr) < 0)
1426 stats->rx_dropped++;
1427 } else {
1428 if (rd->rdesc0.RSR & RSR_CRC)
1429 stats->rx_crc_errors++;
1430 if (rd->rdesc0.RSR & RSR_FAE)
1431 stats->rx_frame_errors++;
1432
1433 stats->rx_dropped++;
1434 }
1435
1436 rd->inten = 1;
1437
1438 vptr->dev->last_rx = jiffies;
1439
1440 rd_curr++;
1441 if (rd_curr >= vptr->options.numrx)
1442 rd_curr = 0;
1443 } while (++works <= 15);
1444
1445 vptr->rd_curr = rd_curr;
1446
1447 if (works > 0 && velocity_rx_refill(vptr) < 0) {
1448 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1449 "%s: rx buf allocation failure\n", vptr->dev->name);
1450 }
1451
1452 VAR_USED(stats);
1453 return works;
1454}
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1466{
1467 skb->ip_summed = CHECKSUM_NONE;
1468
1469 if (rd->rdesc1.CSM & CSM_IPKT) {
1470 if (rd->rdesc1.CSM & CSM_IPOK) {
1471 if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1472 (rd->rdesc1.CSM & CSM_UDPKT)) {
1473 if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
1474 return;
1475 }
1476 }
1477 skb->ip_summed = CHECKSUM_UNNECESSARY;
1478 }
1479 }
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494static inline int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1495 struct velocity_info *vptr)
1496{
1497 int ret = -1;
1498
1499 if (pkt_size < rx_copybreak) {
1500 struct sk_buff *new_skb;
1501
1502 new_skb = dev_alloc_skb(pkt_size + 2);
1503 if (new_skb) {
1504 new_skb->dev = vptr->dev;
1505 new_skb->ip_summed = rx_skb[0]->ip_summed;
1506
1507 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN)
1508 skb_reserve(new_skb, 2);
1509
1510 skb_copy_from_linear_data(rx_skb[0], new_skb->data,
1511 pkt_size);
1512 *rx_skb = new_skb;
1513 ret = 0;
1514 }
1515
1516 }
1517 return ret;
1518}
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529static inline void velocity_iph_realign(struct velocity_info *vptr,
1530 struct sk_buff *skb, int pkt_size)
1531{
1532
1533 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
1534 int i;
1535
1536 for (i = pkt_size; i >= 0; i--)
1537 *(skb->data + i + 2) = *(skb->data + i);
1538 skb_reserve(skb, 2);
1539 }
1540}
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551static int velocity_receive_frame(struct velocity_info *vptr, int idx)
1552{
1553 void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
1554 struct net_device_stats *stats = &vptr->stats;
1555 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
1556 struct rx_desc *rd = &(vptr->rd_ring[idx]);
1557 int pkt_len = rd->rdesc0.len;
1558 struct sk_buff *skb;
1559
1560 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
1561 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
1562 stats->rx_length_errors++;
1563 return -EINVAL;
1564 }
1565
1566 if (rd->rdesc0.RSR & RSR_MAR)
1567 vptr->stats.multicast++;
1568
1569 skb = rd_info->skb;
1570
1571 pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
1572 vptr->rx_buf_sz, PCI_DMA_FROMDEVICE);
1573
1574
1575
1576
1577
1578 if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
1579 if (rd->rdesc0.RSR & RSR_RL) {
1580 stats->rx_length_errors++;
1581 return -EINVAL;
1582 }
1583 }
1584
1585 pci_action = pci_dma_sync_single_for_device;
1586
1587 velocity_rx_csum(rd, skb);
1588
1589 if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
1590 velocity_iph_realign(vptr, skb, pkt_len);
1591 pci_action = pci_unmap_single;
1592 rd_info->skb = NULL;
1593 }
1594
1595 pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx_buf_sz,
1596 PCI_DMA_FROMDEVICE);
1597
1598 skb_put(skb, pkt_len - 4);
1599 skb->protocol = eth_type_trans(skb, vptr->dev);
1600
1601 stats->rx_bytes += pkt_len;
1602 netif_rx(skb);
1603
1604 return 0;
1605}
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1619{
1620 struct rx_desc *rd = &(vptr->rd_ring[idx]);
1621 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
1622
1623 rd_info->skb = dev_alloc_skb(vptr->rx_buf_sz + 64);
1624 if (rd_info->skb == NULL)
1625 return -ENOMEM;
1626
1627
1628
1629
1630
1631 skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63);
1632 rd_info->skb->dev = vptr->dev;
1633 rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data, vptr->rx_buf_sz, PCI_DMA_FROMDEVICE);
1634
1635
1636
1637
1638
1639 *((u32 *) & (rd->rdesc0)) = 0;
1640 rd->len = cpu_to_le32(vptr->rx_buf_sz);
1641 rd->inten = 1;
1642 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1643 rd->pa_high = 0;
1644 return 0;
1645}
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657static int velocity_tx_srv(struct velocity_info *vptr, u32 status)
1658{
1659 struct tx_desc *td;
1660 int qnum;
1661 int full = 0;
1662 int idx;
1663 int works = 0;
1664 struct velocity_td_info *tdinfo;
1665 struct net_device_stats *stats = &vptr->stats;
1666
1667 for (qnum = 0; qnum < vptr->num_txq; qnum++) {
1668 for (idx = vptr->td_tail[qnum]; vptr->td_used[qnum] > 0;
1669 idx = (idx + 1) % vptr->options.numtx) {
1670
1671
1672
1673
1674 td = &(vptr->td_rings[qnum][idx]);
1675 tdinfo = &(vptr->td_infos[qnum][idx]);
1676
1677 if (td->tdesc0.owner == OWNED_BY_NIC)
1678 break;
1679
1680 if ((works++ > 15))
1681 break;
1682
1683 if (td->tdesc0.TSR & TSR0_TERR) {
1684 stats->tx_errors++;
1685 stats->tx_dropped++;
1686 if (td->tdesc0.TSR & TSR0_CDH)
1687 stats->tx_heartbeat_errors++;
1688 if (td->tdesc0.TSR & TSR0_CRS)
1689 stats->tx_carrier_errors++;
1690 if (td->tdesc0.TSR & TSR0_ABT)
1691 stats->tx_aborted_errors++;
1692 if (td->tdesc0.TSR & TSR0_OWC)
1693 stats->tx_window_errors++;
1694 } else {
1695 stats->tx_packets++;
1696 stats->tx_bytes += tdinfo->skb->len;
1697 }
1698 velocity_free_tx_buf(vptr, tdinfo);
1699 vptr->td_used[qnum]--;
1700 }
1701 vptr->td_tail[qnum] = idx;
1702
1703 if (AVAIL_TD(vptr, qnum) < 1) {
1704 full = 1;
1705 }
1706 }
1707
1708
1709
1710
1711 if (netif_queue_stopped(vptr->dev) && (full == 0)
1712 && (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1713 netif_wake_queue(vptr->dev);
1714 }
1715 return works;
1716}
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727static void velocity_print_link_status(struct velocity_info *vptr)
1728{
1729
1730 if (vptr->mii_status & VELOCITY_LINK_FAIL) {
1731 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
1732 } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1733 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
1734
1735 if (vptr->mii_status & VELOCITY_SPEED_1000)
1736 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
1737 else if (vptr->mii_status & VELOCITY_SPEED_100)
1738 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
1739 else
1740 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
1741
1742 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1743 VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
1744 else
1745 VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
1746 } else {
1747 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
1748 switch (vptr->options.spd_dpx) {
1749 case SPD_DPX_100_HALF:
1750 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
1751 break;
1752 case SPD_DPX_100_FULL:
1753 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
1754 break;
1755 case SPD_DPX_10_HALF:
1756 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
1757 break;
1758 case SPD_DPX_10_FULL:
1759 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
1760 break;
1761 default:
1762 break;
1763 }
1764 }
1765}
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779static void velocity_error(struct velocity_info *vptr, int status)
1780{
1781
1782 if (status & ISR_TXSTLI) {
1783 struct mac_regs __iomem * regs = vptr->mac_regs;
1784
1785 printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(®s->TDIdx[0]));
1786 BYTE_REG_BITS_ON(TXESR_TDSTR, ®s->TXESR);
1787 writew(TRDCSR_RUN, ®s->TDCSRClr);
1788 netif_stop_queue(vptr->dev);
1789
1790
1791
1792 }
1793
1794 if (status & ISR_SRCI) {
1795 struct mac_regs __iomem * regs = vptr->mac_regs;
1796 int linked;
1797
1798 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1799 vptr->mii_status = check_connection_type(regs);
1800
1801
1802
1803
1804
1805
1806 if (vptr->rev_id < REV_ID_VT3216_A0) {
1807 if (vptr->mii_status | VELOCITY_DUPLEX_FULL)
1808 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
1809 else
1810 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
1811 }
1812
1813
1814
1815 if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10)) {
1816 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
1817 } else {
1818 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
1819 }
1820 }
1821
1822
1823
1824 linked = readb(®s->PHYSR0) & PHYSR0_LINKGD;
1825
1826 if (linked) {
1827 vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1828 netif_carrier_on(vptr->dev);
1829 } else {
1830 vptr->mii_status |= VELOCITY_LINK_FAIL;
1831 netif_carrier_off(vptr->dev);
1832 }
1833
1834 velocity_print_link_status(vptr);
1835 enable_flow_control_ability(vptr);
1836
1837
1838
1839
1840
1841
1842 enable_mii_autopoll(regs);
1843
1844 if (vptr->mii_status & VELOCITY_LINK_FAIL)
1845 netif_stop_queue(vptr->dev);
1846 else
1847 netif_wake_queue(vptr->dev);
1848
1849 };
1850 if (status & ISR_MIBFI)
1851 velocity_update_hw_mibs(vptr);
1852 if (status & ISR_LSTEI)
1853 mac_rx_queue_wake(vptr->mac_regs);
1854}
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_info *tdinfo)
1866{
1867 struct sk_buff *skb = tdinfo->skb;
1868 int i;
1869
1870
1871
1872
1873 if (tdinfo->skb_dma && (tdinfo->skb_dma[0] != tdinfo->buf_dma)) {
1874
1875 for (i = 0; i < tdinfo->nskb_dma; i++) {
1876#ifdef VELOCITY_ZERO_COPY_SUPPORT
1877 pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], td->tdesc1.len, PCI_DMA_TODEVICE);
1878#else
1879 pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE);
1880#endif
1881 tdinfo->skb_dma[i] = 0;
1882 }
1883 }
1884 dev_kfree_skb_irq(skb);
1885 tdinfo->skb = NULL;
1886}
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899static int velocity_open(struct net_device *dev)
1900{
1901 struct velocity_info *vptr = netdev_priv(dev);
1902 int ret;
1903
1904 ret = velocity_init_rings(vptr);
1905 if (ret < 0)
1906 goto out;
1907
1908 ret = velocity_init_rd_ring(vptr);
1909 if (ret < 0)
1910 goto err_free_desc_rings;
1911
1912 ret = velocity_init_td_ring(vptr);
1913 if (ret < 0)
1914 goto err_free_rd_ring;
1915
1916
1917 pci_set_power_state(vptr->pdev, PCI_D0);
1918
1919 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
1920
1921 ret = request_irq(vptr->pdev->irq, &velocity_intr, IRQF_SHARED,
1922 dev->name, dev);
1923 if (ret < 0) {
1924
1925 pci_set_power_state(vptr->pdev, PCI_D3hot);
1926 goto err_free_td_ring;
1927 }
1928
1929 mac_enable_int(vptr->mac_regs);
1930 netif_start_queue(dev);
1931 vptr->flags |= VELOCITY_FLAGS_OPENED;
1932out:
1933 return ret;
1934
1935err_free_td_ring:
1936 velocity_free_td_ring(vptr);
1937err_free_rd_ring:
1938 velocity_free_rd_ring(vptr);
1939err_free_desc_rings:
1940 velocity_free_rings(vptr);
1941 goto out;
1942}
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954static int velocity_change_mtu(struct net_device *dev, int new_mtu)
1955{
1956 struct velocity_info *vptr = netdev_priv(dev);
1957 unsigned long flags;
1958 int oldmtu = dev->mtu;
1959 int ret = 0;
1960
1961 if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
1962 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
1963 vptr->dev->name);
1964 return -EINVAL;
1965 }
1966
1967 if (!netif_running(dev)) {
1968 dev->mtu = new_mtu;
1969 return 0;
1970 }
1971
1972 if (new_mtu != oldmtu) {
1973 spin_lock_irqsave(&vptr->lock, flags);
1974
1975 netif_stop_queue(dev);
1976 velocity_shutdown(vptr);
1977
1978 velocity_free_td_ring(vptr);
1979 velocity_free_rd_ring(vptr);
1980
1981 dev->mtu = new_mtu;
1982
1983 ret = velocity_init_rd_ring(vptr);
1984 if (ret < 0)
1985 goto out_unlock;
1986
1987 ret = velocity_init_td_ring(vptr);
1988 if (ret < 0)
1989 goto out_unlock;
1990
1991 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
1992
1993 mac_enable_int(vptr->mac_regs);
1994 netif_start_queue(dev);
1995out_unlock:
1996 spin_unlock_irqrestore(&vptr->lock, flags);
1997 }
1998
1999 return ret;
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010static void velocity_shutdown(struct velocity_info *vptr)
2011{
2012 struct mac_regs __iomem * regs = vptr->mac_regs;
2013 mac_disable_int(regs);
2014 writel(CR0_STOP, ®s->CR0Set);
2015 writew(0xFFFF, ®s->TDCSRClr);
2016 writeb(0xFF, ®s->RDCSRClr);
2017 safe_disable_mii_autopoll(regs);
2018 mac_clear_isr(regs);
2019}
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029static int velocity_close(struct net_device *dev)
2030{
2031 struct velocity_info *vptr = netdev_priv(dev);
2032
2033 netif_stop_queue(dev);
2034 velocity_shutdown(vptr);
2035
2036 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2037 velocity_get_ip(vptr);
2038 if (dev->irq != 0)
2039 free_irq(dev->irq, dev);
2040
2041
2042 pci_set_power_state(vptr->pdev, PCI_D3hot);
2043
2044
2045 velocity_free_td_ring(vptr);
2046 velocity_free_rd_ring(vptr);
2047 velocity_free_rings(vptr);
2048
2049 vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2050 return 0;
2051}
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
2063{
2064 struct velocity_info *vptr = netdev_priv(dev);
2065 int qnum = 0;
2066 struct tx_desc *td_ptr;
2067 struct velocity_td_info *tdinfo;
2068 unsigned long flags;
2069 int index;
2070
2071 int pktlen = skb->len;
2072
2073#ifdef VELOCITY_ZERO_COPY_SUPPORT
2074 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
2075 kfree_skb(skb);
2076 return 0;
2077 }
2078#endif
2079
2080 spin_lock_irqsave(&vptr->lock, flags);
2081
2082 index = vptr->td_curr[qnum];
2083 td_ptr = &(vptr->td_rings[qnum][index]);
2084 tdinfo = &(vptr->td_infos[qnum][index]);
2085
2086 td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;
2087 td_ptr->tdesc1.TCR = TCR0_TIC;
2088 td_ptr->td_buf[0].queue = 0;
2089
2090
2091
2092
2093 if (pktlen < ETH_ZLEN) {
2094
2095 pktlen = ETH_ZLEN;
2096 skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
2097 memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
2098 tdinfo->skb = skb;
2099 tdinfo->skb_dma[0] = tdinfo->buf_dma;
2100 td_ptr->tdesc0.pktsize = pktlen;
2101 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2102 td_ptr->td_buf[0].pa_high = 0;
2103 td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
2104 tdinfo->nskb_dma = 1;
2105 td_ptr->tdesc1.CMDZ = 2;
2106 } else
2107#ifdef VELOCITY_ZERO_COPY_SUPPORT
2108 if (skb_shinfo(skb)->nr_frags > 0) {
2109 int nfrags = skb_shinfo(skb)->nr_frags;
2110 tdinfo->skb = skb;
2111 if (nfrags > 6) {
2112 skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
2113 tdinfo->skb_dma[0] = tdinfo->buf_dma;
2114 td_ptr->tdesc0.pktsize =
2115 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2116 td_ptr->td_buf[0].pa_high = 0;
2117 td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
2118 tdinfo->nskb_dma = 1;
2119 td_ptr->tdesc1.CMDZ = 2;
2120 } else {
2121 int i = 0;
2122 tdinfo->nskb_dma = 0;
2123 tdinfo->skb_dma[i] = pci_map_single(vptr->pdev, skb->data, skb->len - skb->data_len, PCI_DMA_TODEVICE);
2124
2125 td_ptr->tdesc0.pktsize = pktlen;
2126
2127
2128 td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma);
2129 td_ptr->td_buf[i].pa_high = 0;
2130 td_ptr->td_buf[i].bufsize = skb->len->skb->data_len;
2131
2132 for (i = 0; i < nfrags; i++) {
2133 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2134 void *addr = ((void *) page_address(frag->page + frag->page_offset));
2135
2136 tdinfo->skb_dma[i + 1] = pci_map_single(vptr->pdev, addr, frag->size, PCI_DMA_TODEVICE);
2137
2138 td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
2139 td_ptr->td_buf[i + 1].pa_high = 0;
2140 td_ptr->td_buf[i + 1].bufsize = frag->size;
2141 }
2142 tdinfo->nskb_dma = i - 1;
2143 td_ptr->tdesc1.CMDZ = i;
2144 }
2145
2146 } else
2147#endif
2148 {
2149
2150
2151
2152
2153 tdinfo->skb = skb;
2154 tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
2155 td_ptr->tdesc0.pktsize = pktlen;
2156 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2157 td_ptr->td_buf[0].pa_high = 0;
2158 td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
2159 tdinfo->nskb_dma = 1;
2160 td_ptr->tdesc1.CMDZ = 2;
2161 }
2162
2163 if (vptr->vlgrp && vlan_tx_tag_present(skb)) {
2164 td_ptr->tdesc1.pqinf.VID = vlan_tx_tag_get(skb);
2165 td_ptr->tdesc1.pqinf.priority = 0;
2166 td_ptr->tdesc1.pqinf.CFI = 0;
2167 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2168 }
2169
2170
2171
2172
2173 if ((vptr->flags & VELOCITY_FLAGS_TX_CSUM)
2174 && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2175 const struct iphdr *ip = ip_hdr(skb);
2176 if (ip->protocol == IPPROTO_TCP)
2177 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2178 else if (ip->protocol == IPPROTO_UDP)
2179 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2180 td_ptr->tdesc1.TCR |= TCR0_IPCK;
2181 }
2182 {
2183
2184 int prev = index - 1;
2185
2186 if (prev < 0)
2187 prev = vptr->options.numtx - 1;
2188 td_ptr->tdesc0.owner = OWNED_BY_NIC;
2189 vptr->td_used[qnum]++;
2190 vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx;
2191
2192 if (AVAIL_TD(vptr, qnum) < 1)
2193 netif_stop_queue(dev);
2194
2195 td_ptr = &(vptr->td_rings[qnum][prev]);
2196 td_ptr->td_buf[0].queue = 1;
2197 mac_tx_queue_wake(vptr->mac_regs, qnum);
2198 }
2199 dev->trans_start = jiffies;
2200 spin_unlock_irqrestore(&vptr->lock, flags);
2201 return 0;
2202}
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215static int velocity_intr(int irq, void *dev_instance)
2216{
2217 struct net_device *dev = dev_instance;
2218 struct velocity_info *vptr = netdev_priv(dev);
2219 u32 isr_status;
2220 int max_count = 0;
2221
2222
2223 spin_lock(&vptr->lock);
2224 isr_status = mac_read_isr(vptr->mac_regs);
2225
2226
2227 if (isr_status == 0) {
2228 spin_unlock(&vptr->lock);
2229 return IRQ_NONE;
2230 }
2231
2232 mac_disable_int(vptr->mac_regs);
2233
2234
2235
2236
2237
2238
2239 while (isr_status != 0) {
2240 mac_write_isr(vptr->mac_regs, isr_status);
2241 if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2242 velocity_error(vptr, isr_status);
2243 if (isr_status & (ISR_PRXI | ISR_PPRXI))
2244 max_count += velocity_rx_srv(vptr, isr_status);
2245 if (isr_status & (ISR_PTXI | ISR_PPTXI))
2246 max_count += velocity_tx_srv(vptr, isr_status);
2247 isr_status = mac_read_isr(vptr->mac_regs);
2248 if (max_count > vptr->options.int_works)
2249 {
2250 printk(KERN_WARNING "%s: excessive work at interrupt.\n",
2251 dev->name);
2252 max_count = 0;
2253 }
2254 }
2255 spin_unlock(&vptr->lock);
2256 mac_enable_int(vptr->mac_regs);
2257 return IRQ_HANDLED;
2258
2259}
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271static void velocity_set_multi(struct net_device *dev)
2272{
2273 struct velocity_info *vptr = netdev_priv(dev);
2274 struct mac_regs __iomem * regs = vptr->mac_regs;
2275 u8 rx_mode;
2276 int i;
2277 struct dev_mc_list *mclist;
2278
2279 if (dev->flags & IFF_PROMISC) {
2280 writel(0xffffffff, ®s->MARCAM[0]);
2281 writel(0xffffffff, ®s->MARCAM[4]);
2282 rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
2283 } else if ((dev->mc_count > vptr->multicast_limit)
2284 || (dev->flags & IFF_ALLMULTI)) {
2285 writel(0xffffffff, ®s->MARCAM[0]);
2286 writel(0xffffffff, ®s->MARCAM[4]);
2287 rx_mode = (RCR_AM | RCR_AB);
2288 } else {
2289 int offset = MCAM_SIZE - vptr->multicast_limit;
2290 mac_get_cam_mask(regs, vptr->mCAMmask);
2291
2292 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next) {
2293 mac_set_cam(regs, i + offset, mclist->dmi_addr);
2294 vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
2295 }
2296
2297 mac_set_cam_mask(regs, vptr->mCAMmask);
2298 rx_mode = (RCR_AM | RCR_AB);
2299 }
2300 if (dev->mtu > 1500)
2301 rx_mode |= RCR_AL;
2302
2303 BYTE_REG_BITS_ON(rx_mode, ®s->RCR);
2304
2305}
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2319{
2320 struct velocity_info *vptr = netdev_priv(dev);
2321
2322
2323 if(!netif_running(dev))
2324 return &vptr->stats;
2325
2326 spin_lock_irq(&vptr->lock);
2327 velocity_update_hw_mibs(vptr);
2328 spin_unlock_irq(&vptr->lock);
2329
2330 vptr->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2331 vptr->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2332 vptr->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2333
2334
2335 vptr->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2336
2337
2338
2339 vptr->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2340
2341
2342
2343
2344
2345
2346
2347 return &vptr->stats;
2348}
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2362{
2363 struct velocity_info *vptr = netdev_priv(dev);
2364 int ret;
2365
2366
2367
2368
2369 if (!netif_running(dev))
2370 pci_set_power_state(vptr->pdev, PCI_D0);
2371
2372 switch (cmd) {
2373 case SIOCGMIIPHY:
2374 case SIOCGMIIREG:
2375 case SIOCSMIIREG:
2376 ret = velocity_mii_ioctl(dev, rq, cmd);
2377 break;
2378
2379 default:
2380 ret = -EOPNOTSUPP;
2381 }
2382 if (!netif_running(dev))
2383 pci_set_power_state(vptr->pdev, PCI_D3hot);
2384
2385
2386 return ret;
2387}
2388
2389
2390
2391
2392
2393
2394static struct pci_driver velocity_driver = {
2395 .name = VELOCITY_NAME,
2396 .id_table = velocity_id_table,
2397 .probe = velocity_found1,
2398 .remove = __devexit_p(velocity_remove1),
2399#ifdef CONFIG_PM
2400 .suspend = velocity_suspend,
2401 .resume = velocity_resume,
2402#endif
2403};
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414static int __init velocity_init_module(void)
2415{
2416 int ret;
2417
2418 velocity_register_notifier();
2419 ret = pci_register_driver(&velocity_driver);
2420 if (ret < 0)
2421 velocity_unregister_notifier();
2422 return ret;
2423}
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434static void __exit velocity_cleanup_module(void)
2435{
2436 velocity_unregister_notifier();
2437 pci_unregister_driver(&velocity_driver);
2438}
2439
2440module_init(velocity_init_module);
2441module_exit(velocity_cleanup_module);
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457static void mii_init(struct velocity_info *vptr, u32 mii_status)
2458{
2459 u16 BMCR;
2460
2461 switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
2462 case PHYID_CICADA_CS8201:
2463
2464
2465
2466 MII_REG_BITS_OFF((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
2467
2468
2469
2470
2471
2472 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
2473 MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
2474 else
2475 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
2476
2477
2478
2479 MII_REG_BITS_ON(PLED_LALBE, MII_REG_PLED, vptr->mac_regs);
2480 break;
2481 case PHYID_VT3216_32BIT:
2482 case PHYID_VT3216_64BIT:
2483
2484
2485
2486 MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
2487
2488
2489
2490
2491
2492 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
2493 MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
2494 else
2495 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
2496 break;
2497
2498 case PHYID_MARVELL_1000:
2499 case PHYID_MARVELL_1000S:
2500
2501
2502
2503 MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
2504
2505
2506
2507 MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
2508 break;
2509 default:
2510 ;
2511 }
2512 velocity_mii_read(vptr->mac_regs, MII_REG_BMCR, &BMCR);
2513 if (BMCR & BMCR_ISO) {
2514 BMCR &= ~BMCR_ISO;
2515 velocity_mii_write(vptr->mac_regs, MII_REG_BMCR, BMCR);
2516 }
2517}
2518
2519
2520
2521
2522
2523
2524
2525
2526static void safe_disable_mii_autopoll(struct mac_regs __iomem * regs)
2527{
2528 u16 ww;
2529
2530
2531 writeb(0, ®s->MIICR);
2532 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2533 udelay(1);
2534 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
2535 break;
2536 }
2537}
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547static void enable_mii_autopoll(struct mac_regs __iomem * regs)
2548{
2549 int ii;
2550
2551 writeb(0, &(regs->MIICR));
2552 writeb(MIIADR_SWMPL, ®s->MIIADR);
2553
2554 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
2555 udelay(1);
2556 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
2557 break;
2558 }
2559
2560 writeb(MIICR_MAUTO, ®s->MIICR);
2561
2562 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
2563 udelay(1);
2564 if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
2565 break;
2566 }
2567
2568}
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
2581{
2582 u16 ww;
2583
2584
2585
2586
2587 safe_disable_mii_autopoll(regs);
2588
2589 writeb(index, ®s->MIIADR);
2590
2591 BYTE_REG_BITS_ON(MIICR_RCMD, ®s->MIICR);
2592
2593 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2594 if (!(readb(®s->MIICR) & MIICR_RCMD))
2595 break;
2596 }
2597
2598 *data = readw(®s->MIIDATA);
2599
2600 enable_mii_autopoll(regs);
2601 if (ww == W_MAX_TIMEOUT)
2602 return -ETIMEDOUT;
2603 return 0;
2604}
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
2617{
2618 u16 ww;
2619
2620
2621
2622
2623 safe_disable_mii_autopoll(regs);
2624
2625
2626 writeb(mii_addr, ®s->MIIADR);
2627
2628 writew(data, ®s->MIIDATA);
2629
2630
2631 BYTE_REG_BITS_ON(MIICR_WCMD, ®s->MIICR);
2632
2633
2634 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2635 udelay(5);
2636 if (!(readb(®s->MIICR) & MIICR_WCMD))
2637 break;
2638 }
2639 enable_mii_autopoll(regs);
2640
2641 if (ww == W_MAX_TIMEOUT)
2642 return -ETIMEDOUT;
2643 return 0;
2644}
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
2656{
2657 u32 status = 0;
2658
2659 switch (vptr->options.spd_dpx) {
2660 case SPD_DPX_AUTO:
2661 status = VELOCITY_AUTONEG_ENABLE;
2662 break;
2663 case SPD_DPX_100_FULL:
2664 status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
2665 break;
2666 case SPD_DPX_10_FULL:
2667 status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
2668 break;
2669 case SPD_DPX_100_HALF:
2670 status = VELOCITY_SPEED_100;
2671 break;
2672 case SPD_DPX_10_HALF:
2673 status = VELOCITY_SPEED_10;
2674 break;
2675 }
2676 vptr->mii_status = status;
2677 return status;
2678}
2679
2680
2681
2682
2683
2684
2685
2686
2687static void mii_set_auto_on(struct velocity_info *vptr)
2688{
2689 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs))
2690 MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
2691 else
2692 MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs);
2693}
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711static void set_mii_flow_control(struct velocity_info *vptr)
2712{
2713
2714 switch (vptr->options.flow_cntl) {
2715 case FLOW_CNTL_TX:
2716 MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
2717 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
2718 break;
2719
2720 case FLOW_CNTL_RX:
2721 MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
2722 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
2723 break;
2724
2725 case FLOW_CNTL_TX_RX:
2726 MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
2727 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
2728 break;
2729
2730 case FLOW_CNTL_DISABLE:
2731 MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
2732 MII_REG_BITS_OFF(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
2733 break;
2734 default:
2735 break;
2736 }
2737}
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
2749{
2750 u32 curr_status;
2751 struct mac_regs __iomem * regs = vptr->mac_regs;
2752
2753 vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
2754 curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
2755
2756
2757 set_mii_flow_control(vptr);
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201) {
2771 MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
2772 }
2773
2774
2775
2776
2777 if (mii_status & VELOCITY_AUTONEG_ENABLE) {
2778 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
2779
2780 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
2781
2782 MII_REG_BITS_ON(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10, MII_REG_ANAR, vptr->mac_regs);
2783 MII_REG_BITS_ON(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
2784 MII_REG_BITS_ON(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs);
2785
2786
2787 mii_set_auto_on(vptr);
2788 } else {
2789 u16 ANAR;
2790 u8 CHIPGCR;
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
2801
2802 CHIPGCR = readb(®s->CHIPGCR);
2803 CHIPGCR &= ~CHIPGCR_FCGMII;
2804
2805 if (mii_status & VELOCITY_DUPLEX_FULL) {
2806 CHIPGCR |= CHIPGCR_FCFDX;
2807 writeb(CHIPGCR, ®s->CHIPGCR);
2808 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
2809 if (vptr->rev_id < REV_ID_VT3216_A0)
2810 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
2811 } else {
2812 CHIPGCR &= ~CHIPGCR_FCFDX;
2813 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
2814 writeb(CHIPGCR, ®s->CHIPGCR);
2815 if (vptr->rev_id < REV_ID_VT3216_A0)
2816 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
2817 }
2818
2819 MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
2820
2821 if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10)) {
2822 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
2823 } else {
2824 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
2825 }
2826
2827 velocity_mii_read(vptr->mac_regs, MII_REG_ANAR, &ANAR);
2828 ANAR &= (~(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10));
2829 if (mii_status & VELOCITY_SPEED_100) {
2830 if (mii_status & VELOCITY_DUPLEX_FULL)
2831 ANAR |= ANAR_TXFD;
2832 else
2833 ANAR |= ANAR_TX;
2834 } else {
2835 if (mii_status & VELOCITY_DUPLEX_FULL)
2836 ANAR |= ANAR_10FD;
2837 else
2838 ANAR |= ANAR_10;
2839 }
2840 velocity_mii_write(vptr->mac_regs, MII_REG_ANAR, ANAR);
2841
2842 mii_set_auto_on(vptr);
2843
2844 }
2845
2846
2847 return VELOCITY_LINK_CHANGE;
2848}
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858static u32 mii_check_media_mode(struct mac_regs __iomem * regs)
2859{
2860 u32 status = 0;
2861 u16 ANAR;
2862
2863 if (!MII_REG_BITS_IS_ON(BMSR_LNK, MII_REG_BMSR, regs))
2864 status |= VELOCITY_LINK_FAIL;
2865
2866 if (MII_REG_BITS_IS_ON(G1000CR_1000FD, MII_REG_G1000CR, regs))
2867 status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
2868 else if (MII_REG_BITS_IS_ON(G1000CR_1000, MII_REG_G1000CR, regs))
2869 status |= (VELOCITY_SPEED_1000);
2870 else {
2871 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
2872 if (ANAR & ANAR_TXFD)
2873 status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
2874 else if (ANAR & ANAR_TX)
2875 status |= VELOCITY_SPEED_100;
2876 else if (ANAR & ANAR_10FD)
2877 status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
2878 else
2879 status |= (VELOCITY_SPEED_10);
2880 }
2881
2882 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
2883 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
2884 if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
2885 == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
2886 if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
2887 status |= VELOCITY_AUTONEG_ENABLE;
2888 }
2889 }
2890
2891 return status;
2892}
2893
2894static u32 check_connection_type(struct mac_regs __iomem * regs)
2895{
2896 u32 status = 0;
2897 u8 PHYSR0;
2898 u16 ANAR;
2899 PHYSR0 = readb(®s->PHYSR0);
2900
2901
2902
2903
2904
2905
2906 if (PHYSR0 & PHYSR0_FDPX)
2907 status |= VELOCITY_DUPLEX_FULL;
2908
2909 if (PHYSR0 & PHYSR0_SPDG)
2910 status |= VELOCITY_SPEED_1000;
2911 else if (PHYSR0 & PHYSR0_SPD10)
2912 status |= VELOCITY_SPEED_10;
2913 else
2914 status |= VELOCITY_SPEED_100;
2915
2916 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
2917 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
2918 if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
2919 == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
2920 if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
2921 status |= VELOCITY_AUTONEG_ENABLE;
2922 }
2923 }
2924
2925 return status;
2926}
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936static void enable_flow_control_ability(struct velocity_info *vptr)
2937{
2938
2939 struct mac_regs __iomem * regs = vptr->mac_regs;
2940
2941 switch (vptr->options.flow_cntl) {
2942
2943 case FLOW_CNTL_DEFAULT:
2944 if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, ®s->PHYSR0))
2945 writel(CR0_FDXRFCEN, ®s->CR0Set);
2946 else
2947 writel(CR0_FDXRFCEN, ®s->CR0Clr);
2948
2949 if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, ®s->PHYSR0))
2950 writel(CR0_FDXTFCEN, ®s->CR0Set);
2951 else
2952 writel(CR0_FDXTFCEN, ®s->CR0Clr);
2953 break;
2954
2955 case FLOW_CNTL_TX:
2956 writel(CR0_FDXTFCEN, ®s->CR0Set);
2957 writel(CR0_FDXRFCEN, ®s->CR0Clr);
2958 break;
2959
2960 case FLOW_CNTL_RX:
2961 writel(CR0_FDXRFCEN, ®s->CR0Set);
2962 writel(CR0_FDXTFCEN, ®s->CR0Clr);
2963 break;
2964
2965 case FLOW_CNTL_TX_RX:
2966 writel(CR0_FDXTFCEN, ®s->CR0Set);
2967 writel(CR0_FDXRFCEN, ®s->CR0Set);
2968 break;
2969
2970 case FLOW_CNTL_DISABLE:
2971 writel(CR0_FDXRFCEN, ®s->CR0Clr);
2972 writel(CR0_FDXTFCEN, ®s->CR0Clr);
2973 break;
2974
2975 default:
2976 break;
2977 }
2978
2979}
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990static int velocity_ethtool_up(struct net_device *dev)
2991{
2992 struct velocity_info *vptr = netdev_priv(dev);
2993 if (!netif_running(dev))
2994 pci_set_power_state(vptr->pdev, PCI_D0);
2995 return 0;
2996}
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006static void velocity_ethtool_down(struct net_device *dev)
3007{
3008 struct velocity_info *vptr = netdev_priv(dev);
3009 if (!netif_running(dev))
3010 pci_set_power_state(vptr->pdev, PCI_D3hot);
3011}
3012
3013static int velocity_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3014{
3015 struct velocity_info *vptr = netdev_priv(dev);
3016 struct mac_regs __iomem * regs = vptr->mac_regs;
3017 u32 status;
3018 status = check_connection_type(vptr->mac_regs);
3019
3020 cmd->supported = SUPPORTED_TP |
3021 SUPPORTED_Autoneg |
3022 SUPPORTED_10baseT_Half |
3023 SUPPORTED_10baseT_Full |
3024 SUPPORTED_100baseT_Half |
3025 SUPPORTED_100baseT_Full |
3026 SUPPORTED_1000baseT_Half |
3027 SUPPORTED_1000baseT_Full;
3028 if (status & VELOCITY_SPEED_1000)
3029 cmd->speed = SPEED_1000;
3030 else if (status & VELOCITY_SPEED_100)
3031 cmd->speed = SPEED_100;
3032 else
3033 cmd->speed = SPEED_10;
3034 cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3035 cmd->port = PORT_TP;
3036 cmd->transceiver = XCVR_INTERNAL;
3037 cmd->phy_address = readb(®s->MIIADR) & 0x1F;
3038
3039 if (status & VELOCITY_DUPLEX_FULL)
3040 cmd->duplex = DUPLEX_FULL;
3041 else
3042 cmd->duplex = DUPLEX_HALF;
3043
3044 return 0;
3045}
3046
3047static int velocity_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3048{
3049 struct velocity_info *vptr = netdev_priv(dev);
3050 u32 curr_status;
3051 u32 new_status = 0;
3052 int ret = 0;
3053
3054 curr_status = check_connection_type(vptr->mac_regs);
3055 curr_status &= (~VELOCITY_LINK_FAIL);
3056
3057 new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3058 new_status |= ((cmd->speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3059 new_status |= ((cmd->speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3060 new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
3061
3062 if ((new_status & VELOCITY_AUTONEG_ENABLE) && (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE)))
3063 ret = -EINVAL;
3064 else
3065 velocity_set_media_mode(vptr, new_status);
3066
3067 return ret;
3068}
3069
3070static u32 velocity_get_link(struct net_device *dev)
3071{
3072 struct velocity_info *vptr = netdev_priv(dev);
3073 struct mac_regs __iomem * regs = vptr->mac_regs;
3074 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, ®s->PHYSR0) ? 1 : 0;
3075}
3076
3077static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3078{
3079 struct velocity_info *vptr = netdev_priv(dev);
3080 strcpy(info->driver, VELOCITY_NAME);
3081 strcpy(info->version, VELOCITY_VERSION);
3082 strcpy(info->bus_info, pci_name(vptr->pdev));
3083}
3084
3085static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3086{
3087 struct velocity_info *vptr = netdev_priv(dev);
3088 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3089 wol->wolopts |= WAKE_MAGIC;
3090
3091
3092
3093
3094 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3095 wol->wolopts |= WAKE_UCAST;
3096 if (vptr->wol_opts & VELOCITY_WOL_ARP)
3097 wol->wolopts |= WAKE_ARP;
3098 memcpy(&wol->sopass, vptr->wol_passwd, 6);
3099}
3100
3101static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3102{
3103 struct velocity_info *vptr = netdev_priv(dev);
3104
3105 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3106 return -EFAULT;
3107 vptr->wol_opts = VELOCITY_WOL_MAGIC;
3108
3109
3110
3111
3112
3113
3114
3115
3116 if (wol->wolopts & WAKE_MAGIC) {
3117 vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3118 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3119 }
3120 if (wol->wolopts & WAKE_UCAST) {
3121 vptr->wol_opts |= VELOCITY_WOL_UCAST;
3122 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3123 }
3124 if (wol->wolopts & WAKE_ARP) {
3125 vptr->wol_opts |= VELOCITY_WOL_ARP;
3126 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3127 }
3128 memcpy(vptr->wol_passwd, wol->sopass, 6);
3129 return 0;
3130}
3131
3132static u32 velocity_get_msglevel(struct net_device *dev)
3133{
3134 return msglevel;
3135}
3136
3137static void velocity_set_msglevel(struct net_device *dev, u32 value)
3138{
3139 msglevel = value;
3140}
3141
3142static const struct ethtool_ops velocity_ethtool_ops = {
3143 .get_settings = velocity_get_settings,
3144 .set_settings = velocity_set_settings,
3145 .get_drvinfo = velocity_get_drvinfo,
3146 .get_wol = velocity_ethtool_get_wol,
3147 .set_wol = velocity_ethtool_set_wol,
3148 .get_msglevel = velocity_get_msglevel,
3149 .set_msglevel = velocity_set_msglevel,
3150 .get_link = velocity_get_link,
3151 .begin = velocity_ethtool_up,
3152 .complete = velocity_ethtool_down
3153};
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3167{
3168 struct velocity_info *vptr = netdev_priv(dev);
3169 struct mac_regs __iomem * regs = vptr->mac_regs;
3170 unsigned long flags;
3171 struct mii_ioctl_data *miidata = if_mii(ifr);
3172 int err;
3173
3174 switch (cmd) {
3175 case SIOCGMIIPHY:
3176 miidata->phy_id = readb(®s->MIIADR) & 0x1f;
3177 break;
3178 case SIOCGMIIREG:
3179 if (!capable(CAP_NET_ADMIN))
3180 return -EPERM;
3181 if(velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
3182 return -ETIMEDOUT;
3183 break;
3184 case SIOCSMIIREG:
3185 if (!capable(CAP_NET_ADMIN))
3186 return -EPERM;
3187 spin_lock_irqsave(&vptr->lock, flags);
3188 err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
3189 spin_unlock_irqrestore(&vptr->lock, flags);
3190 check_connection_type(vptr->mac_regs);
3191 if(err)
3192 return err;
3193 break;
3194 default:
3195 return -EOPNOTSUPP;
3196 }
3197 return 0;
3198}
3199
3200#ifdef CONFIG_PM
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213static void velocity_save_context(struct velocity_info *vptr, struct velocity_context * context)
3214{
3215 struct mac_regs __iomem * regs = vptr->mac_regs;
3216 u16 i;
3217 u8 __iomem *ptr = (u8 __iomem *)regs;
3218
3219 for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
3220 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3221
3222 for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
3223 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3224
3225 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3226 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3227
3228}
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
3240{
3241 struct mac_regs __iomem * regs = vptr->mac_regs;
3242 int i;
3243 u8 __iomem *ptr = (u8 __iomem *)regs;
3244
3245 for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4) {
3246 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3247 }
3248
3249
3250 for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3251
3252 writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3253
3254 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3255 }
3256
3257 for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4) {
3258 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3259 }
3260
3261 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4) {
3262 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3263 }
3264
3265 for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++) {
3266 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3267 }
3268
3269}
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280static u16 wol_calc_crc(int size, u8 * pattern, u8 *mask_pattern)
3281{
3282 u16 crc = 0xFFFF;
3283 u8 mask;
3284 int i, j;
3285
3286 for (i = 0; i < size; i++) {
3287 mask = mask_pattern[i];
3288
3289
3290 if (mask == 0x00)
3291 continue;
3292
3293 for (j = 0; j < 8; j++) {
3294 if ((mask & 0x01) == 0) {
3295 mask >>= 1;
3296 continue;
3297 }
3298 mask >>= 1;
3299 crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
3300 }
3301 }
3302
3303 crc = ~crc;
3304 return bitrev32(crc) >> 16;
3305}
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317static int velocity_set_wol(struct velocity_info *vptr)
3318{
3319 struct mac_regs __iomem * regs = vptr->mac_regs;
3320 static u8 buf[256];
3321 int i;
3322
3323 static u32 mask_pattern[2][4] = {
3324 {0x00203000, 0x000003C0, 0x00000000, 0x0000000},
3325 {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}
3326 };
3327
3328 writew(0xFFFF, ®s->WOLCRClr);
3329 writeb(WOLCFG_SAB | WOLCFG_SAM, ®s->WOLCFGSet);
3330 writew(WOLCR_MAGIC_EN, ®s->WOLCRSet);
3331
3332
3333
3334
3335
3336
3337 if (vptr->wol_opts & VELOCITY_WOL_UCAST) {
3338 writew(WOLCR_UNICAST_EN, ®s->WOLCRSet);
3339 }
3340
3341 if (vptr->wol_opts & VELOCITY_WOL_ARP) {
3342 struct arp_packet *arp = (struct arp_packet *) buf;
3343 u16 crc;
3344 memset(buf, 0, sizeof(struct arp_packet) + 7);
3345
3346 for (i = 0; i < 4; i++)
3347 writel(mask_pattern[0][i], ®s->ByteMask[0][i]);
3348
3349 arp->type = htons(ETH_P_ARP);
3350 arp->ar_op = htons(1);
3351
3352 memcpy(arp->ar_tip, vptr->ip_addr, 4);
3353
3354 crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
3355 (u8 *) & mask_pattern[0][0]);
3356
3357 writew(crc, ®s->PatternCRC[0]);
3358 writew(WOLCR_ARP_EN, ®s->WOLCRSet);
3359 }
3360
3361 BYTE_REG_BITS_ON(PWCFG_WOLTYPE, ®s->PWCFGSet);
3362 BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, ®s->PWCFGSet);
3363
3364 writew(0x0FFF, ®s->WOLSRClr);
3365
3366 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
3367 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
3368 MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
3369
3370 MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
3371 }
3372
3373 if (vptr->mii_status & VELOCITY_SPEED_1000)
3374 MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
3375
3376 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
3377
3378 {
3379 u8 GCR;
3380 GCR = readb(®s->CHIPGCR);
3381 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
3382 writeb(GCR, ®s->CHIPGCR);
3383 }
3384
3385 BYTE_REG_BITS_OFF(ISR_PWEI, ®s->ISR);
3386
3387 BYTE_REG_BITS_ON(STICKHW_SWPTAG, ®s->STICKHW);
3388
3389 BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
3390
3391 return 0;
3392}
3393
3394static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
3395{
3396 struct net_device *dev = pci_get_drvdata(pdev);
3397 struct velocity_info *vptr = netdev_priv(dev);
3398 unsigned long flags;
3399
3400 if(!netif_running(vptr->dev))
3401 return 0;
3402
3403 netif_device_detach(vptr->dev);
3404
3405 spin_lock_irqsave(&vptr->lock, flags);
3406 pci_save_state(pdev);
3407#ifdef ETHTOOL_GWOL
3408 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
3409 velocity_get_ip(vptr);
3410 velocity_save_context(vptr, &vptr->context);
3411 velocity_shutdown(vptr);
3412 velocity_set_wol(vptr);
3413 pci_enable_wake(pdev, 3, 1);
3414 pci_set_power_state(pdev, PCI_D3hot);
3415 } else {
3416 velocity_save_context(vptr, &vptr->context);
3417 velocity_shutdown(vptr);
3418 pci_disable_device(pdev);
3419 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3420 }
3421#else
3422 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3423#endif
3424 spin_unlock_irqrestore(&vptr->lock, flags);
3425 return 0;
3426}
3427
3428static int velocity_resume(struct pci_dev *pdev)
3429{
3430 struct net_device *dev = pci_get_drvdata(pdev);
3431 struct velocity_info *vptr = netdev_priv(dev);
3432 unsigned long flags;
3433 int i;
3434
3435 if(!netif_running(vptr->dev))
3436 return 0;
3437
3438 pci_set_power_state(pdev, PCI_D0);
3439 pci_enable_wake(pdev, 0, 0);
3440 pci_restore_state(pdev);
3441
3442 mac_wol_reset(vptr->mac_regs);
3443
3444 spin_lock_irqsave(&vptr->lock, flags);
3445 velocity_restore_context(vptr, &vptr->context);
3446 velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3447 mac_disable_int(vptr->mac_regs);
3448
3449 velocity_tx_srv(vptr, 0);
3450
3451 for (i = 0; i < vptr->num_txq; i++) {
3452 if (vptr->td_used[i]) {
3453 mac_tx_queue_wake(vptr->mac_regs, i);
3454 }
3455 }
3456
3457 mac_enable_int(vptr->mac_regs);
3458 spin_unlock_irqrestore(&vptr->lock, flags);
3459 netif_device_attach(vptr->dev);
3460
3461 return 0;
3462}
3463
3464#ifdef CONFIG_INET
3465
3466static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3467{
3468 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3469
3470 if (ifa) {
3471 struct net_device *dev = ifa->ifa_dev->dev;
3472 struct velocity_info *vptr;
3473 unsigned long flags;
3474
3475 spin_lock_irqsave(&velocity_dev_list_lock, flags);
3476 list_for_each_entry(vptr, &velocity_dev_list, list) {
3477 if (vptr->dev == dev) {
3478 velocity_get_ip(vptr);
3479 break;
3480 }
3481 }
3482 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
3483 }
3484 return NOTIFY_DONE;
3485}
3486
3487#endif
3488#endif
3489