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38#include <linux/module.h>
39#include <linux/kernel.h>
40#include <linux/mm.h>
41#include <linux/net.h>
42#include <linux/skbuff.h>
43#include <linux/netdevice.h>
44#include <linux/if_arp.h>
45#include <linux/delay.h>
46#include <linux/ioport.h>
47#include <linux/init.h>
48#include <asm/dma.h>
49#include <asm/io.h>
50#define RT_LOCK
51#define RT_UNLOCK
52#include <linux/spinlock.h>
53
54#include <net/syncppp.h>
55#include "z85230.h"
56
57
58
59
60
61
62
63
64
65
66
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68
69
70
71
72
73
74static inline int z8530_read_port(unsigned long p)
75{
76 u8 r=inb(Z8530_PORT_OF(p));
77 if(p&Z8530_PORT_SLEEP)
78 udelay(5);
79 return r;
80}
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98static inline void z8530_write_port(unsigned long p, u8 d)
99{
100 outb(d,Z8530_PORT_OF(p));
101 if(p&Z8530_PORT_SLEEP)
102 udelay(5);
103}
104
105
106
107static void z8530_rx_done(struct z8530_channel *c);
108static void z8530_tx_done(struct z8530_channel *c);
109
110
111
112
113
114
115
116
117
118
119
120
121
122static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
123{
124 if(reg)
125 z8530_write_port(c->ctrlio, reg);
126 return z8530_read_port(c->ctrlio);
127}
128
129
130
131
132
133
134
135
136
137static inline u8 read_zsdata(struct z8530_channel *c)
138{
139 u8 r;
140 r=z8530_read_port(c->dataio);
141 return r;
142}
143
144
145
146
147
148
149
150
151
152
153
154
155
156static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
157{
158 if(reg)
159 z8530_write_port(c->ctrlio, reg);
160 z8530_write_port(c->ctrlio, val);
161
162}
163
164
165
166
167
168
169
170
171
172static inline void write_zsctrl(struct z8530_channel *c, u8 val)
173{
174 z8530_write_port(c->ctrlio, val);
175}
176
177
178
179
180
181
182
183
184
185
186static inline void write_zsdata(struct z8530_channel *c, u8 val)
187{
188 z8530_write_port(c->dataio, val);
189}
190
191
192
193
194
195u8 z8530_dead_port[]=
196{
197 255
198};
199
200EXPORT_SYMBOL(z8530_dead_port);
201
202
203
204
205
206
207
208
209
210
211
212u8 z8530_hdlc_kilostream[]=
213{
214 4, SYNC_ENAB|SDLC|X1CLK,
215 2, 0,
216 1, 0,
217 3, ENT_HM|RxCRC_ENAB|Rx8,
218 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
219 9, 0,
220 6, 0xFF,
221 7, FLAG,
222 10, ABUNDER|NRZ|CRCPS,
223 11, TCTRxCP,
224 14, DISDPLL,
225 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
226 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
227 9, NV|MIE|NORESET,
228 255
229};
230
231EXPORT_SYMBOL(z8530_hdlc_kilostream);
232
233
234
235
236
237u8 z8530_hdlc_kilostream_85230[]=
238{
239 4, SYNC_ENAB|SDLC|X1CLK,
240 2, 0,
241 1, 0,
242 3, ENT_HM|RxCRC_ENAB|Rx8,
243 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
244 9, 0,
245 6, 0xFF,
246 7, FLAG,
247 10, ABUNDER|NRZ|CRCPS,
248 11, TCTRxCP,
249 14, DISDPLL,
250 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
251 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
252 9, NV|MIE|NORESET,
253 23, 3,
254
255 255
256};
257
258EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
259
260
261
262
263
264
265
266
267
268
269
270
271
272static void z8530_flush_fifo(struct z8530_channel *c)
273{
274 read_zsreg(c, R1);
275 read_zsreg(c, R1);
276 read_zsreg(c, R1);
277 read_zsreg(c, R1);
278 if(c->dev->type==Z85230)
279 {
280 read_zsreg(c, R1);
281 read_zsreg(c, R1);
282 read_zsreg(c, R1);
283 read_zsreg(c, R1);
284 }
285}
286
287
288
289
290
291
292
293
294
295
296
297
298static void z8530_rtsdtr(struct z8530_channel *c, int set)
299{
300 if (set)
301 c->regs[5] |= (RTS | DTR);
302 else
303 c->regs[5] &= ~(RTS | DTR);
304 write_zsreg(c, R5, c->regs[5]);
305}
306
307
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330
331static void z8530_rx(struct z8530_channel *c)
332{
333 u8 ch,stat;
334
335 while(1)
336 {
337
338 if(!(read_zsreg(c, R0)&1))
339 break;
340 ch=read_zsdata(c);
341 stat=read_zsreg(c, R1);
342
343
344
345
346 if(c->count < c->max)
347 {
348 *c->dptr++=ch;
349 c->count++;
350 }
351
352 if(stat&END_FR)
353 {
354
355
356
357
358 if(stat&(Rx_OVR|CRC_ERR))
359 {
360
361 if(c->skb)
362 c->dptr=c->skb->data;
363 c->count=0;
364 if(stat&Rx_OVR)
365 {
366 printk(KERN_WARNING "%s: overrun\n", c->dev->name);
367 c->rx_overrun++;
368 }
369 if(stat&CRC_ERR)
370 {
371 c->rx_crc_err++;
372
373 }
374
375 }
376 else
377 {
378
379
380
381
382 z8530_rx_done(c);
383 write_zsctrl(c, RES_Rx_CRC);
384 }
385 }
386 }
387
388
389
390 write_zsctrl(c, ERR_RES);
391 write_zsctrl(c, RES_H_IUS);
392}
393
394
395
396
397
398
399
400
401
402
403
404
405static void z8530_tx(struct z8530_channel *c)
406{
407 while(c->txcount) {
408
409 if(!(read_zsreg(c, R0)&4))
410 return;
411 c->txcount--;
412
413
414
415 write_zsreg(c, R8, *c->tx_ptr++);
416 write_zsctrl(c, RES_H_IUS);
417
418 if(c->txcount==0)
419 {
420 write_zsctrl(c, RES_EOM_L);
421 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
422 }
423 }
424
425
426
427
428
429
430 write_zsctrl(c, RES_Tx_P);
431
432 z8530_tx_done(c);
433 write_zsctrl(c, RES_H_IUS);
434}
435
436
437
438
439
440
441
442
443
444
445
446
447static void z8530_status(struct z8530_channel *chan)
448{
449 u8 status, altered;
450
451 status=read_zsreg(chan, R0);
452 altered=chan->status^status;
453
454 chan->status=status;
455
456 if(status&TxEOM)
457 {
458
459 chan->stats.tx_fifo_errors++;
460 write_zsctrl(chan, ERR_RES);
461 z8530_tx_done(chan);
462 }
463
464 if(altered&chan->dcdcheck)
465 {
466 if(status&chan->dcdcheck)
467 {
468 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
469 write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
470 if(chan->netdevice &&
471 ((chan->netdevice->type == ARPHRD_HDLC) ||
472 (chan->netdevice->type == ARPHRD_PPP)))
473 sppp_reopen(chan->netdevice);
474 }
475 else
476 {
477 printk(KERN_INFO "%s: DCD lost\n", chan->dev->name);
478 write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
479 z8530_flush_fifo(chan);
480 }
481
482 }
483 write_zsctrl(chan, RES_EXT_INT);
484 write_zsctrl(chan, RES_H_IUS);
485}
486
487struct z8530_irqhandler z8530_sync=
488{
489 z8530_rx,
490 z8530_tx,
491 z8530_status
492};
493
494EXPORT_SYMBOL(z8530_sync);
495
496
497
498
499
500
501
502
503
504
505
506static void z8530_dma_rx(struct z8530_channel *chan)
507{
508 if(chan->rxdma_on)
509 {
510
511 u8 status;
512
513 read_zsreg(chan, R7);
514 read_zsreg(chan, R6);
515
516 status=read_zsreg(chan, R1);
517
518 if(status&END_FR)
519 {
520 z8530_rx_done(chan);
521 }
522 write_zsctrl(chan, ERR_RES);
523 write_zsctrl(chan, RES_H_IUS);
524 }
525 else
526 {
527
528 z8530_rx(chan);
529 }
530}
531
532
533
534
535
536
537
538
539
540static void z8530_dma_tx(struct z8530_channel *chan)
541{
542 if(!chan->dma_tx)
543 {
544 printk(KERN_WARNING "Hey who turned the DMA off?\n");
545 z8530_tx(chan);
546 return;
547 }
548
549 printk(KERN_ERR "DMA tx - bogus event!\n");
550 z8530_tx(chan);
551}
552
553
554
555
556
557
558
559
560
561
562
563
564static void z8530_dma_status(struct z8530_channel *chan)
565{
566 u8 status, altered;
567
568 status=read_zsreg(chan, R0);
569 altered=chan->status^status;
570
571 chan->status=status;
572
573
574 if(chan->dma_tx)
575 {
576 if(status&TxEOM)
577 {
578 unsigned long flags;
579
580 flags=claim_dma_lock();
581 disable_dma(chan->txdma);
582 clear_dma_ff(chan->txdma);
583 chan->txdma_on=0;
584 release_dma_lock(flags);
585 z8530_tx_done(chan);
586 }
587 }
588
589 if(altered&chan->dcdcheck)
590 {
591 if(status&chan->dcdcheck)
592 {
593 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
594 write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
595 if(chan->netdevice &&
596 ((chan->netdevice->type == ARPHRD_HDLC) ||
597 (chan->netdevice->type == ARPHRD_PPP)))
598 sppp_reopen(chan->netdevice);
599 }
600 else
601 {
602 printk(KERN_INFO "%s:DCD lost\n", chan->dev->name);
603 write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
604 z8530_flush_fifo(chan);
605 }
606 }
607
608 write_zsctrl(chan, RES_EXT_INT);
609 write_zsctrl(chan, RES_H_IUS);
610}
611
612struct z8530_irqhandler z8530_dma_sync=
613{
614 z8530_dma_rx,
615 z8530_dma_tx,
616 z8530_dma_status
617};
618
619EXPORT_SYMBOL(z8530_dma_sync);
620
621struct z8530_irqhandler z8530_txdma_sync=
622{
623 z8530_rx,
624 z8530_dma_tx,
625 z8530_dma_status
626};
627
628EXPORT_SYMBOL(z8530_txdma_sync);
629
630
631
632
633
634
635
636
637
638
639
640static void z8530_rx_clear(struct z8530_channel *c)
641{
642
643
644
645 u8 stat;
646
647 read_zsdata(c);
648 stat=read_zsreg(c, R1);
649
650 if(stat&END_FR)
651 write_zsctrl(c, RES_Rx_CRC);
652
653
654
655 write_zsctrl(c, ERR_RES);
656 write_zsctrl(c, RES_H_IUS);
657}
658
659
660
661
662
663
664
665
666
667
668static void z8530_tx_clear(struct z8530_channel *c)
669{
670 write_zsctrl(c, RES_Tx_P);
671 write_zsctrl(c, RES_H_IUS);
672}
673
674
675
676
677
678
679
680
681
682
683static void z8530_status_clear(struct z8530_channel *chan)
684{
685 u8 status=read_zsreg(chan, R0);
686 if(status&TxEOM)
687 write_zsctrl(chan, ERR_RES);
688 write_zsctrl(chan, RES_EXT_INT);
689 write_zsctrl(chan, RES_H_IUS);
690}
691
692struct z8530_irqhandler z8530_nop=
693{
694 z8530_rx_clear,
695 z8530_tx_clear,
696 z8530_status_clear
697};
698
699
700EXPORT_SYMBOL(z8530_nop);
701
702
703
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706
707
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710
711
712
713
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717
718
719irqreturn_t z8530_interrupt(int irq, void *dev_id)
720{
721 struct z8530_dev *dev=dev_id;
722 u8 intr;
723 static volatile int locker=0;
724 int work=0;
725 struct z8530_irqhandler *irqs;
726
727 if(locker)
728 {
729 printk(KERN_ERR "IRQ re-enter\n");
730 return IRQ_NONE;
731 }
732 locker=1;
733
734 spin_lock(&dev->lock);
735
736 while(++work<5000)
737 {
738
739 intr = read_zsreg(&dev->chanA, R3);
740 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
741 break;
742
743
744
745
746
747
748
749 irqs=dev->chanA.irqs;
750
751 if(intr & (CHARxIP|CHATxIP|CHAEXT))
752 {
753 if(intr&CHARxIP)
754 irqs->rx(&dev->chanA);
755 if(intr&CHATxIP)
756 irqs->tx(&dev->chanA);
757 if(intr&CHAEXT)
758 irqs->status(&dev->chanA);
759 }
760
761 irqs=dev->chanB.irqs;
762
763 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
764 {
765 if(intr&CHBRxIP)
766 irqs->rx(&dev->chanB);
767 if(intr&CHBTxIP)
768 irqs->tx(&dev->chanB);
769 if(intr&CHBEXT)
770 irqs->status(&dev->chanB);
771 }
772 }
773 spin_unlock(&dev->lock);
774 if(work==5000)
775 printk(KERN_ERR "%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr);
776
777 locker=0;
778 return IRQ_HANDLED;
779}
780
781EXPORT_SYMBOL(z8530_interrupt);
782
783static char reg_init[16]=
784{
785 0,0,0,0,
786 0,0,0,0,
787 0,0,0,0,
788 0x55,0,0,0
789};
790
791
792
793
794
795
796
797
798
799
800
801int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
802{
803 unsigned long flags;
804
805 spin_lock_irqsave(c->lock, flags);
806
807 c->sync = 1;
808 c->mtu = dev->mtu+64;
809 c->count = 0;
810 c->skb = NULL;
811 c->skb2 = NULL;
812 c->irqs = &z8530_sync;
813
814
815 z8530_rx_done(c);
816 z8530_rx_done(c);
817 z8530_rtsdtr(c,1);
818 c->dma_tx = 0;
819 c->regs[R1]|=TxINT_ENAB;
820 write_zsreg(c, R1, c->regs[R1]);
821 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
822
823 spin_unlock_irqrestore(c->lock, flags);
824 return 0;
825}
826
827
828EXPORT_SYMBOL(z8530_sync_open);
829
830
831
832
833
834
835
836
837
838
839int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
840{
841 u8 chk;
842 unsigned long flags;
843
844 spin_lock_irqsave(c->lock, flags);
845 c->irqs = &z8530_nop;
846 c->max = 0;
847 c->sync = 0;
848
849 chk=read_zsreg(c,R0);
850 write_zsreg(c, R3, c->regs[R3]);
851 z8530_rtsdtr(c,0);
852
853 spin_unlock_irqrestore(c->lock, flags);
854 return 0;
855}
856
857EXPORT_SYMBOL(z8530_sync_close);
858
859
860
861
862
863
864
865
866
867
868
869int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
870{
871 unsigned long cflags, dflags;
872
873 c->sync = 1;
874 c->mtu = dev->mtu+64;
875 c->count = 0;
876 c->skb = NULL;
877 c->skb2 = NULL;
878
879
880
881 c->rxdma_on = 0;
882 c->txdma_on = 0;
883
884
885
886
887
888
889
890 if(c->mtu > PAGE_SIZE/2)
891 return -EMSGSIZE;
892
893 c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
894 if(c->rx_buf[0]==NULL)
895 return -ENOBUFS;
896 c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
897
898 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
899 if(c->tx_dma_buf[0]==NULL)
900 {
901 free_page((unsigned long)c->rx_buf[0]);
902 c->rx_buf[0]=NULL;
903 return -ENOBUFS;
904 }
905 c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
906
907 c->tx_dma_used=0;
908 c->dma_tx = 1;
909 c->dma_num=0;
910 c->dma_ready=1;
911
912
913
914
915
916 spin_lock_irqsave(c->lock, cflags);
917
918
919
920
921
922 c->regs[R14]|= DTRREQ;
923 write_zsreg(c, R14, c->regs[R14]);
924
925 c->regs[R1]&= ~TxINT_ENAB;
926 write_zsreg(c, R1, c->regs[R1]);
927
928
929
930
931
932 c->regs[R1]|= WT_FN_RDYFN;
933 c->regs[R1]|= WT_RDY_RT;
934 c->regs[R1]|= INT_ERR_Rx;
935 c->regs[R1]&= ~TxINT_ENAB;
936 write_zsreg(c, R1, c->regs[R1]);
937 c->regs[R1]|= WT_RDY_ENAB;
938 write_zsreg(c, R1, c->regs[R1]);
939
940
941
942
943
944
945
946
947
948 dflags=claim_dma_lock();
949
950 disable_dma(c->rxdma);
951 clear_dma_ff(c->rxdma);
952 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
953 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
954 set_dma_count(c->rxdma, c->mtu);
955 enable_dma(c->rxdma);
956
957 disable_dma(c->txdma);
958 clear_dma_ff(c->txdma);
959 set_dma_mode(c->txdma, DMA_MODE_WRITE);
960 disable_dma(c->txdma);
961
962 release_dma_lock(dflags);
963
964
965
966
967
968 c->rxdma_on = 1;
969 c->txdma_on = 1;
970 c->tx_dma_used = 1;
971
972 c->irqs = &z8530_dma_sync;
973 z8530_rtsdtr(c,1);
974 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
975
976 spin_unlock_irqrestore(c->lock, cflags);
977
978 return 0;
979}
980
981EXPORT_SYMBOL(z8530_sync_dma_open);
982
983
984
985
986
987
988
989
990
991
992int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
993{
994 u8 chk;
995 unsigned long flags;
996
997 c->irqs = &z8530_nop;
998 c->max = 0;
999 c->sync = 0;
1000
1001
1002
1003
1004
1005 flags=claim_dma_lock();
1006 disable_dma(c->rxdma);
1007 clear_dma_ff(c->rxdma);
1008
1009 c->rxdma_on = 0;
1010
1011 disable_dma(c->txdma);
1012 clear_dma_ff(c->txdma);
1013 release_dma_lock(flags);
1014
1015 c->txdma_on = 0;
1016 c->tx_dma_used = 0;
1017
1018 spin_lock_irqsave(c->lock, flags);
1019
1020
1021
1022
1023
1024 c->regs[R1]&= ~WT_RDY_ENAB;
1025 write_zsreg(c, R1, c->regs[R1]);
1026 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1027 c->regs[R1]|= INT_ALL_Rx;
1028 write_zsreg(c, R1, c->regs[R1]);
1029 c->regs[R14]&= ~DTRREQ;
1030 write_zsreg(c, R14, c->regs[R14]);
1031
1032 if(c->rx_buf[0])
1033 {
1034 free_page((unsigned long)c->rx_buf[0]);
1035 c->rx_buf[0]=NULL;
1036 }
1037 if(c->tx_dma_buf[0])
1038 {
1039 free_page((unsigned long)c->tx_dma_buf[0]);
1040 c->tx_dma_buf[0]=NULL;
1041 }
1042 chk=read_zsreg(c,R0);
1043 write_zsreg(c, R3, c->regs[R3]);
1044 z8530_rtsdtr(c,0);
1045
1046 spin_unlock_irqrestore(c->lock, flags);
1047
1048 return 0;
1049}
1050
1051EXPORT_SYMBOL(z8530_sync_dma_close);
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
1064{
1065 unsigned long cflags, dflags;
1066
1067 printk("Opening sync interface for TX-DMA\n");
1068 c->sync = 1;
1069 c->mtu = dev->mtu+64;
1070 c->count = 0;
1071 c->skb = NULL;
1072 c->skb2 = NULL;
1073
1074
1075
1076
1077
1078
1079
1080 if(c->mtu > PAGE_SIZE/2)
1081 return -EMSGSIZE;
1082
1083 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
1084 if(c->tx_dma_buf[0]==NULL)
1085 return -ENOBUFS;
1086
1087 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
1088
1089
1090 spin_lock_irqsave(c->lock, cflags);
1091
1092
1093
1094
1095
1096 z8530_rx_done(c);
1097 z8530_rx_done(c);
1098
1099
1100
1101
1102
1103 c->rxdma_on = 0;
1104 c->txdma_on = 0;
1105
1106 c->tx_dma_used=0;
1107 c->dma_num=0;
1108 c->dma_ready=1;
1109 c->dma_tx = 1;
1110
1111
1112
1113
1114
1115
1116
1117
1118 c->regs[R14]|= DTRREQ;
1119 write_zsreg(c, R14, c->regs[R14]);
1120
1121 c->regs[R1]&= ~TxINT_ENAB;
1122 write_zsreg(c, R1, c->regs[R1]);
1123
1124
1125
1126
1127
1128 dflags = claim_dma_lock();
1129
1130 disable_dma(c->txdma);
1131 clear_dma_ff(c->txdma);
1132 set_dma_mode(c->txdma, DMA_MODE_WRITE);
1133 disable_dma(c->txdma);
1134
1135 release_dma_lock(dflags);
1136
1137
1138
1139
1140
1141 c->rxdma_on = 0;
1142 c->txdma_on = 1;
1143 c->tx_dma_used = 1;
1144
1145 c->irqs = &z8530_txdma_sync;
1146 z8530_rtsdtr(c,1);
1147 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1148 spin_unlock_irqrestore(c->lock, cflags);
1149
1150 return 0;
1151}
1152
1153EXPORT_SYMBOL(z8530_sync_txdma_open);
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
1165{
1166 unsigned long dflags, cflags;
1167 u8 chk;
1168
1169
1170 spin_lock_irqsave(c->lock, cflags);
1171
1172 c->irqs = &z8530_nop;
1173 c->max = 0;
1174 c->sync = 0;
1175
1176
1177
1178
1179
1180 dflags = claim_dma_lock();
1181
1182 disable_dma(c->txdma);
1183 clear_dma_ff(c->txdma);
1184 c->txdma_on = 0;
1185 c->tx_dma_used = 0;
1186
1187 release_dma_lock(dflags);
1188
1189
1190
1191
1192
1193 c->regs[R1]&= ~WT_RDY_ENAB;
1194 write_zsreg(c, R1, c->regs[R1]);
1195 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1196 c->regs[R1]|= INT_ALL_Rx;
1197 write_zsreg(c, R1, c->regs[R1]);
1198 c->regs[R14]&= ~DTRREQ;
1199 write_zsreg(c, R14, c->regs[R14]);
1200
1201 if(c->tx_dma_buf[0])
1202 {
1203 free_page((unsigned long)c->tx_dma_buf[0]);
1204 c->tx_dma_buf[0]=NULL;
1205 }
1206 chk=read_zsreg(c,R0);
1207 write_zsreg(c, R3, c->regs[R3]);
1208 z8530_rtsdtr(c,0);
1209
1210 spin_unlock_irqrestore(c->lock, cflags);
1211 return 0;
1212}
1213
1214
1215EXPORT_SYMBOL(z8530_sync_txdma_close);
1216
1217
1218
1219
1220
1221
1222
1223static char *z8530_type_name[]={
1224 "Z8530",
1225 "Z85C30",
1226 "Z85230"
1227};
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io)
1241{
1242 printk(KERN_INFO "%s: %s found at %s 0x%lX, IRQ %d.\n",
1243 dev->name,
1244 z8530_type_name[dev->type],
1245 mapping,
1246 Z8530_PORT_OF(io),
1247 dev->irq);
1248}
1249
1250EXPORT_SYMBOL(z8530_describe);
1251
1252
1253
1254
1255
1256static inline int do_z8530_init(struct z8530_dev *dev)
1257{
1258
1259
1260 dev->chanA.irqs=&z8530_nop;
1261 dev->chanB.irqs=&z8530_nop;
1262 dev->chanA.dcdcheck=DCD;
1263 dev->chanB.dcdcheck=DCD;
1264
1265
1266 write_zsreg(&dev->chanA, R9, 0xC0);
1267 udelay(200);
1268
1269 write_zsreg(&dev->chanA, R12, 0xAA);
1270 if(read_zsreg(&dev->chanA, R12)!=0xAA)
1271 return -ENODEV;
1272 write_zsreg(&dev->chanA, R12, 0x55);
1273 if(read_zsreg(&dev->chanA, R12)!=0x55)
1274 return -ENODEV;
1275
1276 dev->type=Z8530;
1277
1278
1279
1280
1281
1282 write_zsreg(&dev->chanA, R15, 0x01);
1283
1284
1285
1286
1287
1288
1289 if(read_zsreg(&dev->chanA, R15)==0x01)
1290 {
1291
1292
1293 write_zsreg(&dev->chanA, R8, 0);
1294 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1295 dev->type = Z85230;
1296 else
1297 dev->type = Z85C30;
1298 }
1299
1300
1301
1302
1303
1304
1305
1306 write_zsreg(&dev->chanA, R15, 0);
1307
1308
1309
1310
1311
1312 memcpy(dev->chanA.regs, reg_init, 16);
1313 memcpy(dev->chanB.regs, reg_init ,16);
1314
1315 return 0;
1316}
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335int z8530_init(struct z8530_dev *dev)
1336{
1337 unsigned long flags;
1338 int ret;
1339
1340
1341 spin_lock_init(&dev->lock);
1342 dev->chanA.lock = &dev->lock;
1343 dev->chanB.lock = &dev->lock;
1344
1345 spin_lock_irqsave(&dev->lock, flags);
1346 ret = do_z8530_init(dev);
1347 spin_unlock_irqrestore(&dev->lock, flags);
1348
1349 return ret;
1350}
1351
1352
1353EXPORT_SYMBOL(z8530_init);
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366int z8530_shutdown(struct z8530_dev *dev)
1367{
1368 unsigned long flags;
1369
1370
1371 spin_lock_irqsave(&dev->lock, flags);
1372 dev->chanA.irqs=&z8530_nop;
1373 dev->chanB.irqs=&z8530_nop;
1374 write_zsreg(&dev->chanA, R9, 0xC0);
1375
1376 udelay(100);
1377 spin_unlock_irqrestore(&dev->lock, flags);
1378 return 0;
1379}
1380
1381EXPORT_SYMBOL(z8530_shutdown);
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1395{
1396 unsigned long flags;
1397
1398 spin_lock_irqsave(c->lock, flags);
1399
1400 while(*rtable!=255)
1401 {
1402 int reg=*rtable++;
1403 if(reg>0x0F)
1404 write_zsreg(c, R15, c->regs[15]|1);
1405 write_zsreg(c, reg&0x0F, *rtable);
1406 if(reg>0x0F)
1407 write_zsreg(c, R15, c->regs[15]&~1);
1408 c->regs[reg]=*rtable++;
1409 }
1410 c->rx_function=z8530_null_rx;
1411 c->skb=NULL;
1412 c->tx_skb=NULL;
1413 c->tx_next_skb=NULL;
1414 c->mtu=1500;
1415 c->max=0;
1416 c->count=0;
1417 c->status=read_zsreg(c, R0);
1418 c->sync=1;
1419 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1420
1421 spin_unlock_irqrestore(c->lock, flags);
1422 return 0;
1423}
1424
1425EXPORT_SYMBOL(z8530_channel_load);
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442static void z8530_tx_begin(struct z8530_channel *c)
1443{
1444 unsigned long flags;
1445 if(c->tx_skb)
1446 return;
1447
1448 c->tx_skb=c->tx_next_skb;
1449 c->tx_next_skb=NULL;
1450 c->tx_ptr=c->tx_next_ptr;
1451
1452 if(c->tx_skb==NULL)
1453 {
1454
1455 if(c->dma_tx)
1456 {
1457 flags=claim_dma_lock();
1458 disable_dma(c->txdma);
1459
1460
1461
1462 if(get_dma_residue(c->txdma))
1463 {
1464 c->stats.tx_dropped++;
1465 c->stats.tx_fifo_errors++;
1466 }
1467 release_dma_lock(flags);
1468 }
1469 c->txcount=0;
1470 }
1471 else
1472 {
1473 c->txcount=c->tx_skb->len;
1474
1475
1476 if(c->dma_tx)
1477 {
1478
1479
1480
1481
1482
1483
1484
1485 flags=claim_dma_lock();
1486 disable_dma(c->txdma);
1487
1488
1489
1490
1491
1492
1493 if(c->dev->type!=Z85230)
1494 {
1495 write_zsctrl(c, RES_Tx_CRC);
1496 write_zsctrl(c, RES_EOM_L);
1497 }
1498 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1499 clear_dma_ff(c->txdma);
1500 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1501 set_dma_count(c->txdma, c->txcount);
1502 enable_dma(c->txdma);
1503 release_dma_lock(flags);
1504 write_zsctrl(c, RES_EOM_L);
1505 write_zsreg(c, R5, c->regs[R5]|TxENAB);
1506 }
1507 else
1508 {
1509
1510
1511 write_zsreg(c, R10, c->regs[10]);
1512 write_zsctrl(c, RES_Tx_CRC);
1513
1514 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1515 {
1516 write_zsreg(c, R8, *c->tx_ptr++);
1517 c->txcount--;
1518 }
1519
1520 }
1521 }
1522
1523
1524
1525 netif_wake_queue(c->netdevice);
1526}
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539static void z8530_tx_done(struct z8530_channel *c)
1540{
1541 struct sk_buff *skb;
1542
1543
1544 if(c->tx_skb==NULL)
1545 return;
1546
1547 skb=c->tx_skb;
1548 c->tx_skb=NULL;
1549 z8530_tx_begin(c);
1550 c->stats.tx_packets++;
1551 c->stats.tx_bytes+=skb->len;
1552 dev_kfree_skb_irq(skb);
1553}
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1565{
1566 dev_kfree_skb_any(skb);
1567}
1568
1569EXPORT_SYMBOL(z8530_null_rx);
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584static void z8530_rx_done(struct z8530_channel *c)
1585{
1586 struct sk_buff *skb;
1587 int ct;
1588
1589
1590
1591
1592
1593 if(c->rxdma_on)
1594 {
1595
1596
1597
1598
1599
1600 int ready=c->dma_ready;
1601 unsigned char *rxb=c->rx_buf[c->dma_num];
1602 unsigned long flags;
1603
1604
1605
1606
1607
1608 flags=claim_dma_lock();
1609
1610 disable_dma(c->rxdma);
1611 clear_dma_ff(c->rxdma);
1612 c->rxdma_on=0;
1613 ct=c->mtu-get_dma_residue(c->rxdma);
1614 if(ct<0)
1615 ct=2;
1616 c->dma_ready=0;
1617
1618
1619
1620
1621
1622
1623 if(ready)
1624 {
1625 c->dma_num^=1;
1626 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1627 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1628 set_dma_count(c->rxdma, c->mtu);
1629 c->rxdma_on = 1;
1630 enable_dma(c->rxdma);
1631
1632
1633 write_zsreg(c, R0, RES_Rx_CRC);
1634 }
1635 else
1636
1637
1638 printk(KERN_WARNING "%s: DMA flip overrun!\n", c->netdevice->name);
1639
1640 release_dma_lock(flags);
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650 skb=dev_alloc_skb(ct);
1651 if(skb==NULL)
1652 {
1653 c->stats.rx_dropped++;
1654 printk(KERN_WARNING "%s: Memory squeeze.\n", c->netdevice->name);
1655 }
1656 else
1657 {
1658 skb_put(skb, ct);
1659 skb_copy_to_linear_data(skb, rxb, ct);
1660 c->stats.rx_packets++;
1661 c->stats.rx_bytes+=ct;
1662 }
1663 c->dma_ready=1;
1664 }
1665 else
1666 {
1667 RT_LOCK;
1668 skb=c->skb;
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682 ct=c->count;
1683
1684 c->skb = c->skb2;
1685 c->count = 0;
1686 c->max = c->mtu;
1687 if(c->skb)
1688 {
1689 c->dptr = c->skb->data;
1690 c->max = c->mtu;
1691 }
1692 else
1693 {
1694 c->count= 0;
1695 c->max = 0;
1696 }
1697 RT_UNLOCK;
1698
1699 c->skb2 = dev_alloc_skb(c->mtu);
1700 if(c->skb2==NULL)
1701 printk(KERN_WARNING "%s: memory squeeze.\n",
1702 c->netdevice->name);
1703 else
1704 {
1705 skb_put(c->skb2,c->mtu);
1706 }
1707 c->stats.rx_packets++;
1708 c->stats.rx_bytes+=ct;
1709
1710 }
1711
1712
1713
1714 if(skb)
1715 {
1716 skb_trim(skb, ct);
1717 c->rx_function(c,skb);
1718 }
1719 else
1720 {
1721 c->stats.rx_dropped++;
1722 printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name);
1723 }
1724}
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734static inline int spans_boundary(struct sk_buff *skb)
1735{
1736 unsigned long a=(unsigned long)skb->data;
1737 a^=(a+skb->len);
1738 if(a&0x00010000)
1739 return 1;
1740 return 0;
1741}
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1758{
1759 unsigned long flags;
1760
1761 netif_stop_queue(c->netdevice);
1762 if(c->tx_next_skb)
1763 {
1764 return 1;
1765 }
1766
1767
1768
1769
1770
1771
1772
1773
1774 if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1775 {
1776
1777
1778
1779
1780
1781
1782
1783 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1784 c->tx_dma_used^=1;
1785 skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len);
1786 }
1787 else
1788 c->tx_next_ptr=skb->data;
1789 RT_LOCK;
1790 c->tx_next_skb=skb;
1791 RT_UNLOCK;
1792
1793 spin_lock_irqsave(c->lock, flags);
1794 z8530_tx_begin(c);
1795 spin_unlock_irqrestore(c->lock, flags);
1796
1797 return 0;
1798}
1799
1800EXPORT_SYMBOL(z8530_queue_xmit);
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813struct net_device_stats *z8530_get_stats(struct z8530_channel *c)
1814{
1815 return &c->stats;
1816}
1817
1818EXPORT_SYMBOL(z8530_get_stats);
1819
1820
1821
1822
1823static char banner[] __initdata = KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";
1824
1825static int __init z85230_init_driver(void)
1826{
1827 printk(banner);
1828 return 0;
1829}
1830module_init(z85230_init_driver);
1831
1832static void __exit z85230_cleanup_driver(void)
1833{
1834}
1835module_exit(z85230_cleanup_driver);
1836
1837MODULE_AUTHOR("Red Hat Inc.");
1838MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1839MODULE_LICENSE("GPL");
1840