LXR linux/drivers/net/wireless/prism54/isl

   1/*
   2 *  Copyright (C) 2002 Intersil Americas Inc.
   3 *
   4 *  This program is free software; you can redistribute it and/or modify
   5 *  it under the terms of the GNU General Public License as published by
   6 *  the Free Software Foundation; either version 2 of the License
   7 *
   8 *  This program is distributed in the hope that it will be useful,
   9 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 *  GNU General Public License for more details.
  12 *
  13 *  You should have received a copy of the GNU General Public License
  14 *  along with this program; if not, write to the Free Software
  15 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  16 *
  17 */
  18
  19#ifndef _ISL_38XX_H
  20#define _ISL_38XX_H
  21
  22#include <asm/io.h>
  23#include <asm/byteorder.h>
  24
  25#define ISL38XX_CB_RX_QSIZE                     8
  26#define ISL38XX_CB_TX_QSIZE                     32
  27
  28/* ISL38XX Access Point Specific definitions */
  29#define ISL38XX_MAX_WDS_LINKS                   8
  30
  31/* ISL38xx Client Specific definitions */
  32#define ISL38XX_PSM_ACTIVE_STATE                0
  33#define ISL38XX_PSM_POWERSAVE_STATE             1
  34
  35/* ISL38XX Host Interface Definitions */
  36#define ISL38XX_PCI_MEM_SIZE                    0x02000
  37#define ISL38XX_MEMORY_WINDOW_SIZE              0x01000
  38#define ISL38XX_DEV_FIRMWARE_ADDRES             0x20000
  39#define ISL38XX_WRITEIO_DELAY                   10      /* in us */
  40#define ISL38XX_RESET_DELAY                     50      /* in ms */
  41#define ISL38XX_WAIT_CYCLE                      10      /* in 10ms */
  42#define ISL38XX_MAX_WAIT_CYCLES                 10
  43
  44/* PCI Memory Area */
  45#define ISL38XX_HARDWARE_REG                    0x0000
  46#define ISL38XX_CARDBUS_CIS                     0x0800
  47#define ISL38XX_DIRECT_MEM_WIN                  0x1000
  48
  49/* Hardware registers */
  50#define ISL38XX_DEV_INT_REG                     0x0000
  51#define ISL38XX_INT_IDENT_REG                   0x0010
  52#define ISL38XX_INT_ACK_REG                     0x0014
  53#define ISL38XX_INT_EN_REG                      0x0018
  54#define ISL38XX_GEN_PURP_COM_REG_1              0x0020
  55#define ISL38XX_GEN_PURP_COM_REG_2              0x0024
  56#define ISL38XX_CTRL_BLK_BASE_REG               ISL38XX_GEN_PURP_COM_REG_1
  57#define ISL38XX_DIR_MEM_BASE_REG                0x0030
  58#define ISL38XX_CTRL_STAT_REG                   0x0078
  59
  60/* High end mobos queue up pci writes, the following
  61 * is used to "read" from after a write to force flush */
  62#define ISL38XX_PCI_POSTING_FLUSH               ISL38XX_INT_EN_REG
  63
  64/**
  65 * isl38xx_w32_flush - PCI iomem write helper
  66 * @base: (host) memory base address of the device
  67 * @val: 32bit value (host order) to write
  68 * @offset: byte offset into @base to write value to
  69 *
  70 *  This helper takes care of writing a 32bit datum to the
  71 *  specified offset into the device's pci memory space, and making sure
  72 *  the pci memory buffers get flushed by performing one harmless read
  73 *  from the %ISL38XX_PCI_POSTING_FLUSH offset.
  74 */
  75static inline void
  76isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
  77{
  78        writel(val, base + offset);
  79        (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
  80}
  81
  82/* Device Interrupt register bits */
  83#define ISL38XX_DEV_INT_RESET                   0x0001
  84#define ISL38XX_DEV_INT_UPDATE                  0x0002
  85#define ISL38XX_DEV_INT_WAKEUP                  0x0008
  86#define ISL38XX_DEV_INT_SLEEP                   0x0010
  87
  88/* Interrupt Identification/Acknowledge/Enable register bits */
  89#define ISL38XX_INT_IDENT_UPDATE                0x0002
  90#define ISL38XX_INT_IDENT_INIT                  0x0004
  91#define ISL38XX_INT_IDENT_WAKEUP                0x0008
  92#define ISL38XX_INT_IDENT_SLEEP                 0x0010
  93#define ISL38XX_INT_SOURCES                     0x001E
  94
  95/* Control/Status register bits */
  96/* Looks like there are other meaningful bits
  97    0x20004400 seen in normal operation,
  98    0x200044db at 'timeout waiting for mgmt response'
  99*/
 100#define ISL38XX_CTRL_STAT_SLEEPMODE             0x00000200
 101#define ISL38XX_CTRL_STAT_CLKRUN                0x00800000
 102#define ISL38XX_CTRL_STAT_RESET                 0x10000000
 103#define ISL38XX_CTRL_STAT_RAMBOOT               0x20000000
 104#define ISL38XX_CTRL_STAT_STARTHALTED           0x40000000
 105#define ISL38XX_CTRL_STAT_HOST_OVERRIDE         0x80000000
 106
 107/* Control Block definitions */
 108#define ISL38XX_CB_RX_DATA_LQ                   0
 109#define ISL38XX_CB_TX_DATA_LQ                   1
 110#define ISL38XX_CB_RX_DATA_HQ                   2
 111#define ISL38XX_CB_TX_DATA_HQ                   3
 112#define ISL38XX_CB_RX_MGMTQ                     4
 113#define ISL38XX_CB_TX_MGMTQ                     5
 114#define ISL38XX_CB_QCOUNT                       6
 115#define ISL38XX_CB_MGMT_QSIZE                   4
 116#define ISL38XX_MIN_QTHRESHOLD                  4       /* fragments */
 117
 118/* Memory Manager definitions */
 119#define MGMT_FRAME_SIZE                         1500    /* >= size struct obj_bsslist */
 120#define MGMT_TX_FRAME_COUNT                     24      /* max 4 + spare 4 + 8 init */
 121#define MGMT_RX_FRAME_COUNT                     24      /* 4*4 + spare 8 */
 122#define MGMT_FRAME_COUNT                        (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
 123#define CONTROL_BLOCK_SIZE                      1024    /* should be enough */
 124#define PSM_FRAME_SIZE                          1536
 125#define PSM_MINIMAL_STATION_COUNT               64
 126#define PSM_FRAME_COUNT                         PSM_MINIMAL_STATION_COUNT
 127#define PSM_BUFFER_SIZE                         PSM_FRAME_SIZE * PSM_FRAME_COUNT
 128#define MAX_TRAP_RX_QUEUE                       4
 129#define HOST_MEM_BLOCK                          CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
 130
 131/* Fragment package definitions */
 132#define FRAGMENT_FLAG_MF                        0x0001
 133#define MAX_FRAGMENT_SIZE                       1536
 134
 135/* In monitor mode frames have a header. I don't know exactly how big those
 136 * frame can be but I've never seen any frame bigger than 1584... :
 137 */
 138#define MAX_FRAGMENT_SIZE_RX                    1600
 139
 140typedef struct {
 141        u32 address;            /* physical address on host */
 142        u16 size;               /* packet size */
 143        u16 flags;              /* set of bit-wise flags */
 144} isl38xx_fragment;
 145
 146struct isl38xx_cb {
 147        u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
 148        u32 device_curr_frag[ISL38XX_CB_QCOUNT];
 149        isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
 150        isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
 151        isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
 152        isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
 153        isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 154        isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 155};
 156
 157typedef struct isl38xx_cb isl38xx_control_block;
 158
 159/* determine number of entries currently in queue */
 160int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
 161
 162void isl38xx_disable_interrupts(void __iomem *);
 163void isl38xx_enable_common_interrupts(void __iomem *);
 164
 165void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
 166                                  void __iomem *);
 167void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
 168void isl38xx_trigger_device(int, void __iomem *);
 169void isl38xx_interface_reset(void __iomem *, dma_addr_t);
 170
 171#endif                          /* _ISL_38XX_H */
 172