linux/drivers/pci/hotplug/shpchp_hpc.c
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   1/*
   2 * Standard PCI Hot Plug Driver
   3 *
   4 * Copyright (C) 1995,2001 Compaq Computer Corporation
   5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6 * Copyright (C) 2001 IBM Corp.
   7 * Copyright (C) 2003-2004 Intel Corporation
   8 *
   9 * All rights reserved.
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or (at
  14 * your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19 * NON INFRINGEMENT.  See the GNU General Public License for more
  20 * details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25 *
  26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27 *
  28 */
  29
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/types.h>
  33#include <linux/pci.h>
  34#include <linux/interrupt.h>
  35
  36#include "shpchp.h"
  37
  38/* Slot Available Register I field definition */
  39#define SLOT_33MHZ              0x0000001f
  40#define SLOT_66MHZ_PCIX         0x00001f00
  41#define SLOT_100MHZ_PCIX        0x001f0000
  42#define SLOT_133MHZ_PCIX        0x1f000000
  43
  44/* Slot Available Register II field definition */
  45#define SLOT_66MHZ              0x0000001f
  46#define SLOT_66MHZ_PCIX_266     0x00000f00
  47#define SLOT_100MHZ_PCIX_266    0x0000f000
  48#define SLOT_133MHZ_PCIX_266    0x000f0000
  49#define SLOT_66MHZ_PCIX_533     0x00f00000
  50#define SLOT_100MHZ_PCIX_533    0x0f000000
  51#define SLOT_133MHZ_PCIX_533    0xf0000000
  52
  53/* Slot Configuration */
  54#define SLOT_NUM                0x0000001F
  55#define FIRST_DEV_NUM           0x00001F00
  56#define PSN                     0x07FF0000
  57#define UPDOWN                  0x20000000
  58#define MRLSENSOR               0x40000000
  59#define ATTN_BUTTON             0x80000000
  60
  61/*
  62 * Interrupt Locator Register definitions
  63 */
  64#define CMD_INTR_PENDING        (1 << 0)
  65#define SLOT_INTR_PENDING(i)    (1 << (i + 1))
  66
  67/*
  68 * Controller SERR-INT Register
  69 */
  70#define GLOBAL_INTR_MASK        (1 << 0)
  71#define GLOBAL_SERR_MASK        (1 << 1)
  72#define COMMAND_INTR_MASK       (1 << 2)
  73#define ARBITER_SERR_MASK       (1 << 3)
  74#define COMMAND_DETECTED        (1 << 16)
  75#define ARBITER_DETECTED        (1 << 17)
  76#define SERR_INTR_RSVDZ_MASK    0xfffc0000
  77
  78/*
  79 * Logical Slot Register definitions
  80 */
  81#define SLOT_REG(i)             (SLOT1 + (4 * i))
  82
  83#define SLOT_STATE_SHIFT        (0)
  84#define SLOT_STATE_MASK         (3 << 0)
  85#define SLOT_STATE_PWRONLY      (1)
  86#define SLOT_STATE_ENABLED      (2)
  87#define SLOT_STATE_DISABLED     (3)
  88#define PWR_LED_STATE_SHIFT     (2)
  89#define PWR_LED_STATE_MASK      (3 << 2)
  90#define ATN_LED_STATE_SHIFT     (4)
  91#define ATN_LED_STATE_MASK      (3 << 4)
  92#define ATN_LED_STATE_ON        (1)
  93#define ATN_LED_STATE_BLINK     (2)
  94#define ATN_LED_STATE_OFF       (3)
  95#define POWER_FAULT             (1 << 6)
  96#define ATN_BUTTON              (1 << 7)
  97#define MRL_SENSOR              (1 << 8)
  98#define MHZ66_CAP               (1 << 9)
  99#define PRSNT_SHIFT             (10)
 100#define PRSNT_MASK              (3 << 10)
 101#define PCIX_CAP_SHIFT          (12)
 102#define PCIX_CAP_MASK_PI1       (3 << 12)
 103#define PCIX_CAP_MASK_PI2       (7 << 12)
 104#define PRSNT_CHANGE_DETECTED   (1 << 16)
 105#define ISO_PFAULT_DETECTED     (1 << 17)
 106#define BUTTON_PRESS_DETECTED   (1 << 18)
 107#define MRL_CHANGE_DETECTED     (1 << 19)
 108#define CON_PFAULT_DETECTED     (1 << 20)
 109#define PRSNT_CHANGE_INTR_MASK  (1 << 24)
 110#define ISO_PFAULT_INTR_MASK    (1 << 25)
 111#define BUTTON_PRESS_INTR_MASK  (1 << 26)
 112#define MRL_CHANGE_INTR_MASK    (1 << 27)
 113#define CON_PFAULT_INTR_MASK    (1 << 28)
 114#define MRL_CHANGE_SERR_MASK    (1 << 29)
 115#define CON_PFAULT_SERR_MASK    (1 << 30)
 116#define SLOT_REG_RSVDZ_MASK     (1 << 15) | (7 << 21)
 117
 118/*
 119 * SHPC Command Code definitnions
 120 *
 121 *     Slot Operation                           00h - 3Fh
 122 *     Set Bus Segment Speed/Mode A             40h - 47h
 123 *     Power-Only All Slots                     48h
 124 *     Enable All Slots                         49h
 125 *     Set Bus Segment Speed/Mode B (PI=2)      50h - 5Fh
 126 *     Reserved Command Codes                   60h - BFh
 127 *     Vendor Specific Commands                 C0h - FFh
 128 */
 129#define SET_SLOT_PWR            0x01    /* Slot Operation */
 130#define SET_SLOT_ENABLE         0x02
 131#define SET_SLOT_DISABLE        0x03
 132#define SET_PWR_ON              0x04
 133#define SET_PWR_BLINK           0x08
 134#define SET_PWR_OFF             0x0c
 135#define SET_ATTN_ON             0x10
 136#define SET_ATTN_BLINK          0x20
 137#define SET_ATTN_OFF            0x30
 138#define SETA_PCI_33MHZ          0x40    /* Set Bus Segment Speed/Mode A */
 139#define SETA_PCI_66MHZ          0x41
 140#define SETA_PCIX_66MHZ         0x42
 141#define SETA_PCIX_100MHZ        0x43
 142#define SETA_PCIX_133MHZ        0x44
 143#define SETA_RESERVED1          0x45
 144#define SETA_RESERVED2          0x46
 145#define SETA_RESERVED3          0x47
 146#define SET_PWR_ONLY_ALL        0x48    /* Power-Only All Slots */
 147#define SET_ENABLE_ALL          0x49    /* Enable All Slots */
 148#define SETB_PCI_33MHZ          0x50    /* Set Bus Segment Speed/Mode B */
 149#define SETB_PCI_66MHZ          0x51
 150#define SETB_PCIX_66MHZ_PM      0x52
 151#define SETB_PCIX_100MHZ_PM     0x53
 152#define SETB_PCIX_133MHZ_PM     0x54
 153#define SETB_PCIX_66MHZ_EM      0x55
 154#define SETB_PCIX_100MHZ_EM     0x56
 155#define SETB_PCIX_133MHZ_EM     0x57
 156#define SETB_PCIX_66MHZ_266     0x58
 157#define SETB_PCIX_100MHZ_266    0x59
 158#define SETB_PCIX_133MHZ_266    0x5a
 159#define SETB_PCIX_66MHZ_533     0x5b
 160#define SETB_PCIX_100MHZ_533    0x5c
 161#define SETB_PCIX_133MHZ_533    0x5d
 162#define SETB_RESERVED1          0x5e
 163#define SETB_RESERVED2          0x5f
 164
 165/*
 166 * SHPC controller command error code
 167 */
 168#define SWITCH_OPEN             0x1
 169#define INVALID_CMD             0x2
 170#define INVALID_SPEED_MODE      0x4
 171
 172/*
 173 * For accessing SHPC Working Register Set via PCI Configuration Space
 174 */
 175#define DWORD_SELECT            0x2
 176#define DWORD_DATA              0x4
 177
 178/* Field Offset in Logical Slot Register - byte boundary */
 179#define SLOT_EVENT_LATCH        0x2
 180#define SLOT_SERR_INT_MASK      0x3
 181
 182static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
 183
 184static irqreturn_t shpc_isr(int irq, void *dev_id);
 185static void start_int_poll_timer(struct controller *ctrl, int sec);
 186static int hpc_check_cmd_status(struct controller *ctrl);
 187
 188static inline u8 shpc_readb(struct controller *ctrl, int reg)
 189{
 190        return readb(ctrl->creg + reg);
 191}
 192
 193static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
 194{
 195        writeb(val, ctrl->creg + reg);
 196}
 197
 198static inline u16 shpc_readw(struct controller *ctrl, int reg)
 199{
 200        return readw(ctrl->creg + reg);
 201}
 202
 203static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
 204{
 205        writew(val, ctrl->creg + reg);
 206}
 207
 208static inline u32 shpc_readl(struct controller *ctrl, int reg)
 209{
 210        return readl(ctrl->creg + reg);
 211}
 212
 213static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
 214{
 215        writel(val, ctrl->creg + reg);
 216}
 217
 218static inline int shpc_indirect_read(struct controller *ctrl, int index,
 219                                     u32 *value)
 220{
 221        int rc;
 222        u32 cap_offset = ctrl->cap_offset;
 223        struct pci_dev *pdev = ctrl->pci_dev;
 224
 225        rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
 226        if (rc)
 227                return rc;
 228        return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
 229}
 230
 231/*
 232 * This is the interrupt polling timeout function.
 233 */
 234static void int_poll_timeout(unsigned long data)
 235{
 236        struct controller *ctrl = (struct controller *)data;
 237
 238        /* Poll for interrupt events.  regs == NULL => polling */
 239        shpc_isr(0, ctrl);
 240
 241        init_timer(&ctrl->poll_timer);
 242        if (!shpchp_poll_time)
 243                shpchp_poll_time = 2; /* default polling interval is 2 sec */
 244
 245        start_int_poll_timer(ctrl, shpchp_poll_time);
 246}
 247
 248/*
 249 * This function starts the interrupt polling timer.
 250 */
 251static void start_int_poll_timer(struct controller *ctrl, int sec)
 252{
 253        /* Clamp to sane value */
 254        if ((sec <= 0) || (sec > 60))
 255                sec = 2;
 256
 257        ctrl->poll_timer.function = &int_poll_timeout;
 258        ctrl->poll_timer.data = (unsigned long)ctrl;
 259        ctrl->poll_timer.expires = jiffies + sec * HZ;
 260        add_timer(&ctrl->poll_timer);
 261}
 262
 263static inline int is_ctrl_busy(struct controller *ctrl)
 264{
 265        u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
 266        return cmd_status & 0x1;
 267}
 268
 269/*
 270 * Returns 1 if SHPC finishes executing a command within 1 sec,
 271 * otherwise returns 0.
 272 */
 273static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
 274{
 275        int i;
 276
 277        if (!is_ctrl_busy(ctrl))
 278                return 1;
 279
 280        /* Check every 0.1 sec for a total of 1 sec */
 281        for (i = 0; i < 10; i++) {
 282                msleep(100);
 283                if (!is_ctrl_busy(ctrl))
 284                        return 1;
 285        }
 286
 287        return 0;
 288}
 289
 290static inline int shpc_wait_cmd(struct controller *ctrl)
 291{
 292        int retval = 0;
 293        unsigned long timeout = msecs_to_jiffies(1000);
 294        int rc;
 295
 296        if (shpchp_poll_mode)
 297                rc = shpc_poll_ctrl_busy(ctrl);
 298        else
 299                rc = wait_event_interruptible_timeout(ctrl->queue,
 300                                                !is_ctrl_busy(ctrl), timeout);
 301        if (!rc && is_ctrl_busy(ctrl)) {
 302                retval = -EIO;
 303                err("Command not completed in 1000 msec\n");
 304        } else if (rc < 0) {
 305                retval = -EINTR;
 306                info("Command was interrupted by a signal\n");
 307        }
 308
 309        return retval;
 310}
 311
 312static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
 313{
 314        struct controller *ctrl = slot->ctrl;
 315        u16 cmd_status;
 316        int retval = 0;
 317        u16 temp_word;
 318
 319        mutex_lock(&slot->ctrl->cmd_lock);
 320
 321        if (!shpc_poll_ctrl_busy(ctrl)) {
 322                /* After 1 sec and and the controller is still busy */
 323                err("%s : Controller is still busy after 1 sec.\n",
 324                    __FUNCTION__);
 325                retval = -EBUSY;
 326                goto out;
 327        }
 328
 329        ++t_slot;
 330        temp_word =  (t_slot << 8) | (cmd & 0xFF);
 331        dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
 332
 333        /* To make sure the Controller Busy bit is 0 before we send out the
 334         * command.
 335         */
 336        shpc_writew(ctrl, CMD, temp_word);
 337
 338        /*
 339         * Wait for command completion.
 340         */
 341        retval = shpc_wait_cmd(slot->ctrl);
 342        if (retval)
 343                goto out;
 344
 345        cmd_status = hpc_check_cmd_status(slot->ctrl);
 346        if (cmd_status) {
 347                err("%s: Failed to issued command 0x%x (error code = %d)\n",
 348                    __FUNCTION__, cmd, cmd_status);
 349                retval = -EIO;
 350        }
 351 out:
 352        mutex_unlock(&slot->ctrl->cmd_lock);
 353        return retval;
 354}
 355
 356static int hpc_check_cmd_status(struct controller *ctrl)
 357{
 358        int retval = 0;
 359        u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
 360
 361        switch (cmd_status >> 1) {
 362        case 0:
 363                retval = 0;
 364                break;
 365        case 1:
 366                retval = SWITCH_OPEN;
 367                err("%s: Switch opened!\n", __FUNCTION__);
 368                break;
 369        case 2:
 370                retval = INVALID_CMD;
 371                err("%s: Invalid HPC command!\n", __FUNCTION__);
 372                break;
 373        case 4:
 374                retval = INVALID_SPEED_MODE;
 375                err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
 376                break;
 377        default:
 378                retval = cmd_status;
 379        }
 380
 381        return retval;
 382}
 383
 384
 385static int hpc_get_attention_status(struct slot *slot, u8 *status)
 386{
 387        struct controller *ctrl = slot->ctrl;
 388        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 389        u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
 390
 391        switch (state) {
 392        case ATN_LED_STATE_ON:
 393                *status = 1;    /* On */
 394                break;
 395        case ATN_LED_STATE_BLINK:
 396                *status = 2;    /* Blink */
 397                break;
 398        case ATN_LED_STATE_OFF:
 399                *status = 0;    /* Off */
 400                break;
 401        default:
 402                *status = 0xFF; /* Reserved */
 403                break;
 404        }
 405
 406        return 0;
 407}
 408
 409static int hpc_get_power_status(struct slot * slot, u8 *status)
 410{
 411        struct controller *ctrl = slot->ctrl;
 412        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 413        u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
 414
 415        switch (state) {
 416        case SLOT_STATE_PWRONLY:
 417                *status = 2;    /* Powered only */
 418                break;
 419        case SLOT_STATE_ENABLED:
 420                *status = 1;    /* Enabled */
 421                break;
 422        case SLOT_STATE_DISABLED:
 423                *status = 0;    /* Disabled */
 424                break;
 425        default:
 426                *status = 0xFF; /* Reserved */
 427                break;
 428        }
 429
 430        return 0;
 431}
 432
 433
 434static int hpc_get_latch_status(struct slot *slot, u8 *status)
 435{
 436        struct controller *ctrl = slot->ctrl;
 437        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 438
 439        *status = !!(slot_reg & MRL_SENSOR);    /* 0 -> close; 1 -> open */
 440
 441        return 0;
 442}
 443
 444static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 445{
 446        struct controller *ctrl = slot->ctrl;
 447        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 448        u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
 449
 450        *status = (state != 0x3) ? 1 : 0;
 451
 452        return 0;
 453}
 454
 455static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
 456{
 457        struct controller *ctrl = slot->ctrl;
 458
 459        *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
 460
 461        return 0;
 462}
 463
 464static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
 465{
 466        int retval = 0;
 467        struct controller *ctrl = slot->ctrl;
 468        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 469        u8 m66_cap  = !!(slot_reg & MHZ66_CAP);
 470        u8 pi, pcix_cap;
 471
 472        if ((retval = hpc_get_prog_int(slot, &pi)))
 473                return retval;
 474
 475        switch (pi) {
 476        case 1:
 477                pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
 478                break;
 479        case 2:
 480                pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
 481                break;
 482        default:
 483                return -ENODEV;
 484        }
 485
 486        dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
 487            __FUNCTION__, slot_reg, pcix_cap, m66_cap);
 488
 489        switch (pcix_cap) {
 490        case 0x0:
 491                *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
 492                break;
 493        case 0x1:
 494                *value = PCI_SPEED_66MHz_PCIX;
 495                break;
 496        case 0x3:
 497                *value = PCI_SPEED_133MHz_PCIX;
 498                break;
 499        case 0x4:
 500                *value = PCI_SPEED_133MHz_PCIX_266;
 501                break;
 502        case 0x5:
 503                *value = PCI_SPEED_133MHz_PCIX_533;
 504                break;
 505        case 0x2:
 506        default:
 507                *value = PCI_SPEED_UNKNOWN;
 508                retval = -ENODEV;
 509                break;
 510        }
 511
 512        dbg("Adapter speed = %d\n", *value);
 513        return retval;
 514}
 515
 516static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
 517{
 518        int retval = 0;
 519        struct controller *ctrl = slot->ctrl;
 520        u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
 521        u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
 522
 523        if (pi == 2) {
 524                *mode = (sec_bus_status & 0x0100) >> 8;
 525        } else {
 526                retval = -1;
 527        }
 528
 529        dbg("Mode 1 ECC cap = %d\n", *mode);
 530        return retval;
 531}
 532
 533static int hpc_query_power_fault(struct slot * slot)
 534{
 535        struct controller *ctrl = slot->ctrl;
 536        u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
 537
 538        /* Note: Logic 0 => fault */
 539        return !(slot_reg & POWER_FAULT);
 540}
 541
 542static int hpc_set_attention_status(struct slot *slot, u8 value)
 543{
 544        u8 slot_cmd = 0;
 545
 546        switch (value) {
 547                case 0 :
 548                        slot_cmd = SET_ATTN_OFF;        /* OFF */
 549                        break;
 550                case 1:
 551                        slot_cmd = SET_ATTN_ON;         /* ON */
 552                        break;
 553                case 2:
 554                        slot_cmd = SET_ATTN_BLINK;      /* BLINK */
 555                        break;
 556                default:
 557                        return -1;
 558        }
 559
 560        return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 561}
 562
 563
 564static void hpc_set_green_led_on(struct slot *slot)
 565{
 566        shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
 567}
 568
 569static void hpc_set_green_led_off(struct slot *slot)
 570{
 571        shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
 572}
 573
 574static void hpc_set_green_led_blink(struct slot *slot)
 575{
 576        shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
 577}
 578
 579static void hpc_release_ctlr(struct controller *ctrl)
 580{
 581        int i;
 582        u32 slot_reg, serr_int;
 583
 584        /*
 585         * Mask event interrupts and SERRs of all slots
 586         */
 587        for (i = 0; i < ctrl->num_slots; i++) {
 588                slot_reg = shpc_readl(ctrl, SLOT_REG(i));
 589                slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
 590                             BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
 591                             CON_PFAULT_INTR_MASK   | MRL_CHANGE_SERR_MASK |
 592                             CON_PFAULT_SERR_MASK);
 593                slot_reg &= ~SLOT_REG_RSVDZ_MASK;
 594                shpc_writel(ctrl, SLOT_REG(i), slot_reg);
 595        }
 596
 597        cleanup_slots(ctrl);
 598
 599        /*
 600         * Mask SERR and System Interrut generation
 601         */
 602        serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
 603        serr_int |= (GLOBAL_INTR_MASK  | GLOBAL_SERR_MASK |
 604                     COMMAND_INTR_MASK | ARBITER_SERR_MASK);
 605        serr_int &= ~SERR_INTR_RSVDZ_MASK;
 606        shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
 607
 608        if (shpchp_poll_mode)
 609                del_timer(&ctrl->poll_timer);
 610        else {
 611                free_irq(ctrl->pci_dev->irq, ctrl);
 612                pci_disable_msi(ctrl->pci_dev);
 613        }
 614
 615        iounmap(ctrl->creg);
 616        release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
 617
 618        /*
 619         * If this is the last controller to be released, destroy the
 620         * shpchpd work queue
 621         */
 622        if (atomic_dec_and_test(&shpchp_num_controllers))
 623                destroy_workqueue(shpchp_wq);
 624}
 625
 626static int hpc_power_on_slot(struct slot * slot)
 627{
 628        int retval;
 629
 630        retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
 631        if (retval)
 632                err("%s: Write command failed!\n", __FUNCTION__);
 633
 634        return retval;
 635}
 636
 637static int hpc_slot_enable(struct slot * slot)
 638{
 639        int retval;
 640
 641        /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
 642        retval = shpc_write_cmd(slot, slot->hp_slot,
 643                        SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
 644        if (retval)
 645                err("%s: Write command failed!\n", __FUNCTION__);
 646
 647        return retval;
 648}
 649
 650static int hpc_slot_disable(struct slot * slot)
 651{
 652        int retval;
 653
 654        /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
 655        retval = shpc_write_cmd(slot, slot->hp_slot,
 656                        SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
 657        if (retval)
 658                err("%s: Write command failed!\n", __FUNCTION__);
 659
 660        return retval;
 661}
 662
 663static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
 664{
 665        int retval;
 666        struct controller *ctrl = slot->ctrl;
 667        u8 pi, cmd;
 668
 669        pi = shpc_readb(ctrl, PROG_INTERFACE);
 670        if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
 671                return -EINVAL;
 672
 673        switch (value) {
 674        case PCI_SPEED_33MHz:
 675                cmd = SETA_PCI_33MHZ;
 676                break;
 677        case PCI_SPEED_66MHz:
 678                cmd = SETA_PCI_66MHZ;
 679                break;
 680        case PCI_SPEED_66MHz_PCIX:
 681                cmd = SETA_PCIX_66MHZ;
 682                break;
 683        case PCI_SPEED_100MHz_PCIX:
 684                cmd = SETA_PCIX_100MHZ;
 685                break;
 686        case PCI_SPEED_133MHz_PCIX:
 687                cmd = SETA_PCIX_133MHZ;
 688                break;
 689        case PCI_SPEED_66MHz_PCIX_ECC:
 690                cmd = SETB_PCIX_66MHZ_EM;
 691                break;
 692        case PCI_SPEED_100MHz_PCIX_ECC:
 693                cmd = SETB_PCIX_100MHZ_EM;
 694                break;
 695        case PCI_SPEED_133MHz_PCIX_ECC:
 696                cmd = SETB_PCIX_133MHZ_EM;
 697                break;
 698        case PCI_SPEED_66MHz_PCIX_266:
 699                cmd = SETB_PCIX_66MHZ_266;
 700                break;
 701        case PCI_SPEED_100MHz_PCIX_266:
 702                cmd = SETB_PCIX_100MHZ_266;
 703                break;
 704        case PCI_SPEED_133MHz_PCIX_266:
 705                cmd = SETB_PCIX_133MHZ_266;
 706                break;
 707        case PCI_SPEED_66MHz_PCIX_533:
 708                cmd = SETB_PCIX_66MHZ_533;
 709                break;
 710        case PCI_SPEED_100MHz_PCIX_533:
 711                cmd = SETB_PCIX_100MHZ_533;
 712                break;
 713        case PCI_SPEED_133MHz_PCIX_533:
 714                cmd = SETB_PCIX_133MHZ_533;
 715                break;
 716        default:
 717                return -EINVAL;
 718        }
 719
 720        retval = shpc_write_cmd(slot, 0, cmd);
 721        if (retval)
 722                err("%s: Write command failed!\n", __FUNCTION__);
 723
 724        return retval;
 725}
 726
 727static irqreturn_t shpc_isr(int irq, void *dev_id)
 728{
 729        struct controller *ctrl = (struct controller *)dev_id;
 730        u32 serr_int, slot_reg, intr_loc, intr_loc2;
 731        int hp_slot;
 732
 733        /* Check to see if it was our interrupt */
 734        intr_loc = shpc_readl(ctrl, INTR_LOC);
 735        if (!intr_loc)
 736                return IRQ_NONE;
 737
 738        dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
 739
 740        if(!shpchp_poll_mode) {
 741                /*
 742                 * Mask Global Interrupt Mask - see implementation
 743                 * note on p. 139 of SHPC spec rev 1.0
 744                 */
 745                serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
 746                serr_int |= GLOBAL_INTR_MASK;
 747                serr_int &= ~SERR_INTR_RSVDZ_MASK;
 748                shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
 749
 750                intr_loc2 = shpc_readl(ctrl, INTR_LOC);
 751                dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
 752        }
 753
 754        if (intr_loc & CMD_INTR_PENDING) {
 755                /*
 756                 * Command Complete Interrupt Pending
 757                 * RO only - clear by writing 1 to the Command Completion
 758                 * Detect bit in Controller SERR-INT register
 759                 */
 760                serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
 761                serr_int &= ~SERR_INTR_RSVDZ_MASK;
 762                shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
 763
 764                wake_up_interruptible(&ctrl->queue);
 765        }
 766
 767        if (!(intr_loc & ~CMD_INTR_PENDING))
 768                goto out;
 769
 770        for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
 771                /* To find out which slot has interrupt pending */
 772                if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
 773                        continue;
 774
 775                slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
 776                dbg("%s: Slot %x with intr, slot register = %x\n",
 777                    __FUNCTION__, hp_slot, slot_reg);
 778
 779                if (slot_reg & MRL_CHANGE_DETECTED)
 780                        shpchp_handle_switch_change(hp_slot, ctrl);
 781
 782                if (slot_reg & BUTTON_PRESS_DETECTED)
 783                        shpchp_handle_attention_button(hp_slot, ctrl);
 784
 785                if (slot_reg & PRSNT_CHANGE_DETECTED)
 786                        shpchp_handle_presence_change(hp_slot, ctrl);
 787
 788                if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
 789                        shpchp_handle_power_fault(hp_slot, ctrl);
 790
 791                /* Clear all slot events */
 792                slot_reg &= ~SLOT_REG_RSVDZ_MASK;
 793                shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
 794        }
 795 out:
 796        if (!shpchp_poll_mode) {
 797                /* Unmask Global Interrupt Mask */
 798                serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
 799                serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
 800                shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
 801        }
 802
 803        return IRQ_HANDLED;
 804}
 805
 806static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
 807{
 808        int retval = 0;
 809        struct controller *ctrl = slot->ctrl;
 810        enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
 811        u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
 812        u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
 813        u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
 814
 815        if (pi == 2) {
 816                if (slot_avail2 & SLOT_133MHZ_PCIX_533)
 817                        bus_speed = PCI_SPEED_133MHz_PCIX_533;
 818                else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
 819                        bus_speed = PCI_SPEED_100MHz_PCIX_533;
 820                else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
 821                        bus_speed = PCI_SPEED_66MHz_PCIX_533;
 822                else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
 823                        bus_speed = PCI_SPEED_133MHz_PCIX_266;
 824                else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
 825                        bus_speed = PCI_SPEED_100MHz_PCIX_266;
 826                else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
 827                        bus_speed = PCI_SPEED_66MHz_PCIX_266;
 828        }
 829
 830        if (bus_speed == PCI_SPEED_UNKNOWN) {
 831                if (slot_avail1 & SLOT_133MHZ_PCIX)
 832                        bus_speed = PCI_SPEED_133MHz_PCIX;
 833                else if (slot_avail1 & SLOT_100MHZ_PCIX)
 834                        bus_speed = PCI_SPEED_100MHz_PCIX;
 835                else if (slot_avail1 & SLOT_66MHZ_PCIX)
 836                        bus_speed = PCI_SPEED_66MHz_PCIX;
 837                else if (slot_avail2 & SLOT_66MHZ)
 838                        bus_speed = PCI_SPEED_66MHz;
 839                else if (slot_avail1 & SLOT_33MHZ)
 840                        bus_speed = PCI_SPEED_33MHz;
 841                else
 842                        retval = -ENODEV;
 843        }
 844
 845        *value = bus_speed;
 846        dbg("Max bus speed = %d\n", bus_speed);
 847
 848        return retval;
 849}
 850
 851static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
 852{
 853        int retval = 0;
 854        struct controller *ctrl = slot->ctrl;
 855        enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
 856        u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
 857        u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
 858        u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
 859
 860        if ((pi == 1) && (speed_mode > 4)) {
 861                *value = PCI_SPEED_UNKNOWN;
 862                return -ENODEV;
 863        }
 864
 865        switch (speed_mode) {
 866        case 0x0:
 867                *value = PCI_SPEED_33MHz;
 868                break;
 869        case 0x1:
 870                *value = PCI_SPEED_66MHz;
 871                break;
 872        case 0x2:
 873                *value = PCI_SPEED_66MHz_PCIX;
 874                break;
 875        case 0x3:
 876                *value = PCI_SPEED_100MHz_PCIX;
 877                break;
 878        case 0x4:
 879                *value = PCI_SPEED_133MHz_PCIX;
 880                break;
 881        case 0x5:
 882                *value = PCI_SPEED_66MHz_PCIX_ECC;
 883                break;
 884        case 0x6:
 885                *value = PCI_SPEED_100MHz_PCIX_ECC;
 886                break;
 887        case 0x7:
 888                *value = PCI_SPEED_133MHz_PCIX_ECC;
 889                break;
 890        case 0x8:
 891                *value = PCI_SPEED_66MHz_PCIX_266;
 892                break;
 893        case 0x9:
 894                *value = PCI_SPEED_100MHz_PCIX_266;
 895                break;
 896        case 0xa:
 897                *value = PCI_SPEED_133MHz_PCIX_266;
 898                break;
 899        case 0xb:
 900                *value = PCI_SPEED_66MHz_PCIX_533;
 901                break;
 902        case 0xc:
 903                *value = PCI_SPEED_100MHz_PCIX_533;
 904                break;
 905        case 0xd:
 906                *value = PCI_SPEED_133MHz_PCIX_533;
 907                break;
 908        default:
 909                *value = PCI_SPEED_UNKNOWN;
 910                retval = -ENODEV;
 911                break;
 912        }
 913
 914        dbg("Current bus speed = %d\n", bus_speed);
 915        return retval;
 916}
 917
 918static struct hpc_ops shpchp_hpc_ops = {
 919        .power_on_slot                  = hpc_power_on_slot,
 920        .slot_enable                    = hpc_slot_enable,
 921        .slot_disable                   = hpc_slot_disable,
 922        .set_bus_speed_mode             = hpc_set_bus_speed_mode,
 923        .set_attention_status   = hpc_set_attention_status,
 924        .get_power_status               = hpc_get_power_status,
 925        .get_attention_status   = hpc_get_attention_status,
 926        .get_latch_status               = hpc_get_latch_status,
 927        .get_adapter_status             = hpc_get_adapter_status,
 928
 929        .get_max_bus_speed              = hpc_get_max_bus_speed,
 930        .get_cur_bus_speed              = hpc_get_cur_bus_speed,
 931        .get_adapter_speed              = hpc_get_adapter_speed,
 932        .get_mode1_ECC_cap              = hpc_get_mode1_ECC_cap,
 933        .get_prog_int                   = hpc_get_prog_int,
 934
 935        .query_power_fault              = hpc_query_power_fault,
 936        .green_led_on                   = hpc_set_green_led_on,
 937        .green_led_off                  = hpc_set_green_led_off,
 938        .green_led_blink                = hpc_set_green_led_blink,
 939
 940        .release_ctlr                   = hpc_release_ctlr,
 941};
 942
 943int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
 944{
 945        int rc = -1, num_slots = 0;
 946        u8 hp_slot;
 947        u32 shpc_base_offset;
 948        u32 tempdword, slot_reg, slot_config;
 949        u8 i;
 950
 951        ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */
 952
 953        if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
 954                                PCI_DEVICE_ID_AMD_GOLAM_7450)) {
 955                /* amd shpc driver doesn't use Base Offset; assume 0 */
 956                ctrl->mmio_base = pci_resource_start(pdev, 0);
 957                ctrl->mmio_size = pci_resource_len(pdev, 0);
 958        } else {
 959                ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
 960                if (!ctrl->cap_offset) {
 961                        err("%s : cap_offset == 0\n", __FUNCTION__);
 962                        goto abort;
 963                }
 964                dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
 965
 966                rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
 967                if (rc) {
 968                        err("%s: cannot read base_offset\n", __FUNCTION__);
 969                        goto abort;
 970                }
 971
 972                rc = shpc_indirect_read(ctrl, 3, &tempdword);
 973                if (rc) {
 974                        err("%s: cannot read slot config\n", __FUNCTION__);
 975                        goto abort;
 976                }
 977                num_slots = tempdword & SLOT_NUM;
 978                dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
 979
 980                for (i = 0; i < 9 + num_slots; i++) {
 981                        rc = shpc_indirect_read(ctrl, i, &tempdword);
 982                        if (rc) {
 983                                err("%s: cannot read creg (index = %d)\n",
 984                                    __FUNCTION__, i);
 985                                goto abort;
 986                        }
 987                        dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
 988                                        tempdword);
 989                }
 990
 991                ctrl->mmio_base =
 992                        pci_resource_start(pdev, 0) + shpc_base_offset;
 993                ctrl->mmio_size = 0x24 + 0x4 * num_slots;
 994        }
 995
 996        info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
 997                pdev->subsystem_device);
 998
 999        rc = pci_enable_device(pdev);
1000        if (rc) {
1001                err("%s: pci_enable_device failed\n", __FUNCTION__);
1002                goto abort;
1003        }
1004
1005        if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1006                err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1007                rc = -1;
1008                goto abort;
1009        }
1010
1011        ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1012        if (!ctrl->creg) {
1013                err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1014                    ctrl->mmio_size, ctrl->mmio_base);
1015                release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1016                rc = -1;
1017                goto abort;
1018        }
1019        dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg);
1020
1021        mutex_init(&ctrl->crit_sect);
1022        mutex_init(&ctrl->cmd_lock);
1023
1024        /* Setup wait queue */
1025        init_waitqueue_head(&ctrl->queue);
1026
1027        ctrl->hpc_ops = &shpchp_hpc_ops;
1028
1029        /* Return PCI Controller Info */
1030        slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1031        ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1032        ctrl->num_slots = slot_config & SLOT_NUM;
1033        ctrl->first_slot = (slot_config & PSN) >> 16;
1034        ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1035
1036        /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1037        tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038        dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1039        tempdword |= (GLOBAL_INTR_MASK  | GLOBAL_SERR_MASK |
1040                      COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1041        tempdword &= ~SERR_INTR_RSVDZ_MASK;
1042        shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1043        tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1044        dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1045
1046        /* Mask the MRL sensor SERR Mask of individual slot in
1047         * Slot SERR-INT Mask & clear all the existing event if any
1048         */
1049        for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1050                slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1051                dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1052                        hp_slot, slot_reg);
1053                slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1054                             BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1055                             CON_PFAULT_INTR_MASK   | MRL_CHANGE_SERR_MASK |
1056                             CON_PFAULT_SERR_MASK);
1057                slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1058                shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1059        }
1060
1061        if (shpchp_poll_mode) {
1062                /* Install interrupt polling timer. Start with 10 sec delay */
1063                init_timer(&ctrl->poll_timer);
1064                start_int_poll_timer(ctrl, 10);
1065        } else {
1066                /* Installs the interrupt handler */
1067                rc = pci_enable_msi(pdev);
1068                if (rc) {
1069                        info("Can't get msi for the hotplug controller\n");
1070                        info("Use INTx for the hotplug controller\n");
1071                }
1072
1073                rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1074                                 MY_NAME, (void *)ctrl);
1075                dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1076                    __FUNCTION__, ctrl->pci_dev->irq,
1077                    atomic_read(&shpchp_num_controllers), rc);
1078                if (rc) {
1079                        err("Can't get irq %d for the hotplug controller\n",
1080                            ctrl->pci_dev->irq);
1081                        goto abort_iounmap;
1082                }
1083        }
1084        dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1085                        pdev->bus->number, PCI_SLOT(pdev->devfn),
1086                        PCI_FUNC(pdev->devfn), pdev->irq);
1087        get_hp_hw_control_from_firmware(pdev);
1088
1089        /*
1090         * If this is the first controller to be initialized,
1091         * initialize the shpchpd work queue
1092         */
1093        if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1094                shpchp_wq = create_singlethread_workqueue("shpchpd");
1095                if (!shpchp_wq) {
1096                        rc = -ENOMEM;
1097                        goto abort_iounmap;
1098                }
1099        }
1100
1101        /*
1102         * Unmask all event interrupts of all slots
1103         */
1104        for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1105                slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1106                dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1107                        hp_slot, slot_reg);
1108                slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1109                              BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1110                              CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1111                shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1112        }
1113        if (!shpchp_poll_mode) {
1114                /* Unmask all general input interrupts and SERR */
1115                tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1116                tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1117                               SERR_INTR_RSVDZ_MASK);
1118                shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1119                tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1120                dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1121        }
1122
1123        return 0;
1124
1125        /* We end up here for the many possible ways to fail this API.  */
1126abort_iounmap:
1127        iounmap(ctrl->creg);
1128abort:
1129        return rc;
1130}
1131