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29#include <linux/delay.h>
30#include <linux/pci.h>
31#include <linux/module.h>
32#include <linux/firmware.h>
33#include "aic94xx_reg.h"
34#include "aic94xx_hwi.h"
35
36#include "aic94xx_seq.h"
37#include "aic94xx_dump.h"
38
39
40
41
42
43#define PAUSE_DELAY 1
44#define PAUSE_TRIES 1000
45
46static const struct firmware *sequencer_fw;
47static u16 cseq_vecs[CSEQ_NUM_VECS], lseq_vecs[LSEQ_NUM_VECS], mode2_task,
48 cseq_idle_loop, lseq_idle_loop;
49static u8 *cseq_code, *lseq_code;
50static u32 cseq_code_size, lseq_code_size;
51
52static u16 first_scb_site_no = 0xFFFF;
53static u16 last_scb_site_no;
54
55
56
57
58
59
60
61
62
63int asd_pause_cseq(struct asd_ha_struct *asd_ha)
64{
65 int count = PAUSE_TRIES;
66 u32 arp2ctl;
67
68 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
69 if (arp2ctl & PAUSED)
70 return 0;
71
72 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl | EPAUSE);
73 do {
74 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
75 if (arp2ctl & PAUSED)
76 return 0;
77 udelay(PAUSE_DELAY);
78 } while (--count > 0);
79
80 ASD_DPRINTK("couldn't pause CSEQ\n");
81 return -1;
82}
83
84
85
86
87
88
89
90int asd_unpause_cseq(struct asd_ha_struct *asd_ha)
91{
92 u32 arp2ctl;
93 int count = PAUSE_TRIES;
94
95 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
96 if (!(arp2ctl & PAUSED))
97 return 0;
98
99 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl & ~EPAUSE);
100 do {
101 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
102 if (!(arp2ctl & PAUSED))
103 return 0;
104 udelay(PAUSE_DELAY);
105 } while (--count > 0);
106
107 ASD_DPRINTK("couldn't unpause the CSEQ\n");
108 return -1;
109}
110
111
112
113
114
115
116
117
118static inline int asd_seq_pause_lseq(struct asd_ha_struct *asd_ha, int lseq)
119{
120 u32 arp2ctl;
121 int count = PAUSE_TRIES;
122
123 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
124 if (arp2ctl & PAUSED)
125 return 0;
126
127 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl | EPAUSE);
128 do {
129 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
130 if (arp2ctl & PAUSED)
131 return 0;
132 udelay(PAUSE_DELAY);
133 } while (--count > 0);
134
135 ASD_DPRINTK("couldn't pause LSEQ %d\n", lseq);
136 return -1;
137}
138
139
140
141
142
143
144
145
146int asd_pause_lseq(struct asd_ha_struct *asd_ha, u8 lseq_mask)
147{
148 int lseq;
149 int err = 0;
150
151 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
152 err = asd_seq_pause_lseq(asd_ha, lseq);
153 if (err)
154 return err;
155 }
156
157 return err;
158}
159
160
161
162
163
164
165
166
167static inline int asd_seq_unpause_lseq(struct asd_ha_struct *asd_ha, int lseq)
168{
169 u32 arp2ctl;
170 int count = PAUSE_TRIES;
171
172 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
173 if (!(arp2ctl & PAUSED))
174 return 0;
175
176 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl & ~EPAUSE);
177 do {
178 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
179 if (!(arp2ctl & PAUSED))
180 return 0;
181 udelay(PAUSE_DELAY);
182 } while (--count > 0);
183
184 ASD_DPRINTK("couldn't unpause LSEQ %d\n", lseq);
185 return 0;
186}
187
188
189
190
191
192
193
194
195
196int asd_unpause_lseq(struct asd_ha_struct *asd_ha, u8 lseq_mask)
197{
198 int lseq;
199 int err = 0;
200
201 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
202 err = asd_seq_unpause_lseq(asd_ha, lseq);
203 if (err)
204 return err;
205 }
206
207 return err;
208}
209
210
211
212static int asd_verify_cseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
213 u32 size)
214{
215 u32 addr = CSEQ_RAM_REG_BASE_ADR;
216 const u32 *prog = (u32 *) _prog;
217 u32 i;
218
219 for (i = 0; i < size; i += 4, prog++, addr += 4) {
220 u32 val = asd_read_reg_dword(asd_ha, addr);
221
222 if (le32_to_cpu(*prog) != val) {
223 asd_printk("%s: cseq verify failed at %u "
224 "read:0x%x, wanted:0x%x\n",
225 pci_name(asd_ha->pcidev),
226 i, val, le32_to_cpu(*prog));
227 return -1;
228 }
229 }
230 ASD_DPRINTK("verified %d bytes, passed\n", size);
231 return 0;
232}
233
234
235
236
237
238
239
240
241
242
243
244
245
246static int asd_verify_lseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
247 u32 size, int lseq)
248{
249#define LSEQ_CODEPAGE_SIZE 4096
250 int pages = (size + LSEQ_CODEPAGE_SIZE - 1) / LSEQ_CODEPAGE_SIZE;
251 u32 page;
252 const u32 *prog = (u32 *) _prog;
253
254 for (page = 0; page < pages; page++) {
255 u32 i;
256
257 asd_write_reg_dword(asd_ha, LmBISTCTL1(lseq),
258 page << LmRAMPAGE_LSHIFT);
259 for (i = 0; size > 0 && i < LSEQ_CODEPAGE_SIZE;
260 i += 4, prog++, size-=4) {
261
262 u32 val = asd_read_reg_dword(asd_ha, LmSEQRAM(lseq)+i);
263
264 if (le32_to_cpu(*prog) != val) {
265 asd_printk("%s: LSEQ%d verify failed "
266 "page:%d, offs:%d\n",
267 pci_name(asd_ha->pcidev),
268 lseq, page, i);
269 return -1;
270 }
271 }
272 }
273 ASD_DPRINTK("LSEQ%d verified %d bytes, passed\n", lseq,
274 (int)((u8 *)prog-_prog));
275 return 0;
276}
277
278
279
280
281
282
283
284
285
286
287static int asd_verify_seq(struct asd_ha_struct *asd_ha, const u8 *prog,
288 u32 size, u8 lseq_mask)
289{
290 if (lseq_mask == 0)
291 return asd_verify_cseq(asd_ha, prog, size);
292 else {
293 int lseq, err;
294
295 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
296 err = asd_verify_lseq(asd_ha, prog, size, lseq);
297 if (err)
298 return err;
299 }
300 }
301
302 return 0;
303}
304#define ASD_DMA_MODE_DOWNLOAD
305#ifdef ASD_DMA_MODE_DOWNLOAD
306
307#define MAX_DMA_OVLY_COUNT ((1U << 14)-1)
308static int asd_download_seq(struct asd_ha_struct *asd_ha,
309 const u8 * const prog, u32 size, u8 lseq_mask)
310{
311 u32 comstaten;
312 u32 reg;
313 int page;
314 const int pages = (size + MAX_DMA_OVLY_COUNT - 1) / MAX_DMA_OVLY_COUNT;
315 struct asd_dma_tok *token;
316 int err = 0;
317
318 if (size % 4) {
319 asd_printk("sequencer program not multiple of 4\n");
320 return -1;
321 }
322
323 asd_pause_cseq(asd_ha);
324 asd_pause_lseq(asd_ha, 0xFF);
325
326
327 comstaten = asd_read_reg_dword(asd_ha, COMSTATEN);
328 asd_write_reg_dword(asd_ha, COMSTATEN, 0);
329 asd_write_reg_dword(asd_ha, COMSTAT, COMSTAT_MASK);
330
331 asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
332 asd_write_reg_dword(asd_ha, CHIMINT, CHIMINT_MASK);
333
334 token = asd_alloc_coherent(asd_ha, MAX_DMA_OVLY_COUNT, GFP_KERNEL);
335 if (!token) {
336 asd_printk("out of memory for dma SEQ download\n");
337 err = -ENOMEM;
338 goto out;
339 }
340 ASD_DPRINTK("dma-ing %d bytes\n", size);
341
342 for (page = 0; page < pages; page++) {
343 int i;
344 u32 left = min(size-page*MAX_DMA_OVLY_COUNT,
345 (u32)MAX_DMA_OVLY_COUNT);
346
347 memcpy(token->vaddr, prog + page*MAX_DMA_OVLY_COUNT, left);
348 asd_write_reg_addr(asd_ha, OVLYDMAADR, token->dma_handle);
349 asd_write_reg_dword(asd_ha, OVLYDMACNT, left);
350 reg = !page ? RESETOVLYDMA : 0;
351 reg |= (STARTOVLYDMA | OVLYHALTERR);
352 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
353
354 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
355
356 for (i = PAUSE_TRIES*100; i > 0; i--) {
357 u32 dmadone = asd_read_reg_dword(asd_ha, OVLYDMACTL);
358 if (!(dmadone & OVLYDMAACT))
359 break;
360 udelay(PAUSE_DELAY);
361 }
362 }
363
364 reg = asd_read_reg_dword(asd_ha, COMSTAT);
365 if (!(reg & OVLYDMADONE) || (reg & OVLYERR)
366 || (asd_read_reg_dword(asd_ha, CHIMINT) & DEVEXCEPT_MASK)){
367 asd_printk("%s: error DMA-ing sequencer code\n",
368 pci_name(asd_ha->pcidev));
369 err = -ENODEV;
370 }
371
372 asd_free_coherent(asd_ha, token);
373 out:
374 asd_write_reg_dword(asd_ha, COMSTATEN, comstaten);
375
376 return err ? : asd_verify_seq(asd_ha, prog, size, lseq_mask);
377}
378#else
379static int asd_download_seq(struct asd_ha_struct *asd_ha, const u8 *_prog,
380 u32 size, u8 lseq_mask)
381{
382 int i;
383 u32 reg = 0;
384 const u32 *prog = (u32 *) _prog;
385
386 if (size % 4) {
387 asd_printk("sequencer program not multiple of 4\n");
388 return -1;
389 }
390
391 asd_pause_cseq(asd_ha);
392 asd_pause_lseq(asd_ha, 0xFF);
393
394 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
395 reg |= PIOCMODE;
396
397 asd_write_reg_dword(asd_ha, OVLYDMACNT, size);
398 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
399
400 ASD_DPRINTK("downloading %s sequencer%s in PIO mode...\n",
401 lseq_mask ? "LSEQ" : "CSEQ", lseq_mask ? "s" : "");
402
403 for (i = 0; i < size; i += 4, prog++)
404 asd_write_reg_dword(asd_ha, SPIODATA, *prog);
405
406 reg = (reg & ~PIOCMODE) | OVLYHALTERR;
407 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
408
409 return asd_verify_seq(asd_ha, _prog, size, lseq_mask);
410}
411#endif
412
413
414
415
416
417
418
419static int asd_seq_download_seqs(struct asd_ha_struct *asd_ha)
420{
421 int err;
422
423 if (!asd_ha->hw_prof.enabled_phys) {
424 asd_printk("%s: no enabled phys!\n", pci_name(asd_ha->pcidev));
425 return -ENODEV;
426 }
427
428
429 ASD_DPRINTK("downloading CSEQ...\n");
430 err = asd_download_seq(asd_ha, cseq_code, cseq_code_size, 0);
431 if (err) {
432 asd_printk("CSEQ download failed:%d\n", err);
433 return err;
434 }
435
436
437
438
439 ASD_DPRINTK("downloading LSEQs...\n");
440 err = asd_download_seq(asd_ha, lseq_code, lseq_code_size,
441 asd_ha->hw_prof.enabled_phys);
442 if (err) {
443
444 u8 lseq;
445 u8 lseq_mask = asd_ha->hw_prof.enabled_phys;
446
447 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
448 err = asd_download_seq(asd_ha, lseq_code,
449 lseq_code_size, 1<<lseq);
450 if (err)
451 break;
452 }
453 }
454 if (err)
455 asd_printk("LSEQs download failed:%d\n", err);
456
457 return err;
458}
459
460
461
462
463
464
465
466static void asd_init_cseq_mip(struct asd_ha_struct *asd_ha)
467{
468
469 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_HEAD, 0xFFFF);
470 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_TAIL, 0xFFFF);
471 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_HEAD, 0xFFFF);
472 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_TAIL, 0xFFFF);
473 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_HEAD, 0xFFFF);
474 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_TAIL, 0xFFFF);
475 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_HEAD, 0xFFFF);
476 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_TAIL, 0xFFFF);
477 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_HEAD, 0xFFFF);
478 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_TAIL, 0xFFFF);
479 asd_write_reg_word(asd_ha, CSEQ_REG0, 0);
480 asd_write_reg_word(asd_ha, CSEQ_REG1, 0);
481 asd_write_reg_dword(asd_ha, CSEQ_REG2, 0);
482 asd_write_reg_byte(asd_ha, CSEQ_LINK_CTL_Q_MAP, 0);
483 {
484 u8 con = asd_read_reg_byte(asd_ha, CCONEXIST);
485 u8 val = hweight8(con);
486 asd_write_reg_byte(asd_ha, CSEQ_MAX_CSEQ_MODE, (val<<4)|val);
487 }
488 asd_write_reg_word(asd_ha, CSEQ_FREE_LIST_HACK_COUNT, 0);
489
490
491 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE, 0);
492 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE+4, 0);
493 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT, 0);
494 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT+4, 0);
495 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_HEAD, 0xFFFF);
496 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_TAIL, 0xFFFF);
497 asd_write_reg_word(asd_ha, CSEQ_NEED_EST_NEXUS_SCB, 0);
498 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_HEAD, 0);
499 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_TAIL, 0);
500 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_SCB_OFFSET, 0);
501
502
503 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR0, 0);
504 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR1, 0);
505 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_SCBPTR, 0);
506 asd_write_reg_byte(asd_ha, CSEQ_INT_ROUT_MODE, 0);
507 asd_write_reg_byte(asd_ha, CSEQ_ISR_SCRATCH_FLAGS, 0);
508 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_SINDEX, 0);
509 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_DINDEX, 0);
510 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_HEAD, 0xFFFF);
511 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_TAIL, 0xFFFF);
512
513 {
514 u16 cmdctx = asd_get_cmdctx_size(asd_ha);
515 cmdctx = (~((cmdctx/128)-1)) >> 8;
516 asd_write_reg_byte(asd_ha, CSEQ_FREE_SCB_MASK, (u8)cmdctx);
517 }
518 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_HEAD,
519 first_scb_site_no);
520 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_TAIL,
521 last_scb_site_no);
522 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_HEAD, 0xFFFF);
523 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_TAIL, 0xFFFF);
524
525
526 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE, 0);
527 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE+4, 0);
528 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT, 0);
529 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT+4, 0);
530 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_HEAD, 0xFFFF);
531 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_TAIL, 0xFFFF);
532 asd_write_reg_word(asd_ha, CSEQ_NEED_EMPTY_SCB, 0);
533 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_HEAD, 0);
534 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_TAIL, 0);
535 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_SCB_OFFSET, 0);
536 asd_write_reg_word(asd_ha, CSEQ_PRIMITIVE_DATA, 0);
537 asd_write_reg_dword(asd_ha, CSEQ_TIMEOUT_CONST, 0);
538}
539
540
541
542
543
544static void asd_init_cseq_mdp(struct asd_ha_struct *asd_ha)
545{
546 int i;
547 int moffs;
548
549 moffs = CSEQ_PAGE_SIZE * 2;
550
551
552 for (i = 0; i < 8; i++) {
553 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SINDEX, 0);
554 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCBPTR, 0);
555 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_HEAD, 0xFFFF);
556 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_TAIL, 0xFFFF);
557 asd_write_reg_byte(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCRPAGE, 0);
558 }
559
560
561
562
563 asd_write_reg_word(asd_ha, CSEQ_RET_ADDR, 0xFFFF);
564 asd_write_reg_word(asd_ha, CSEQ_RET_SCBPTR, 0);
565 asd_write_reg_word(asd_ha, CSEQ_SAVE_SCBPTR, 0);
566 asd_write_reg_word(asd_ha, CSEQ_EMPTY_TRANS_CTX, 0);
567 asd_write_reg_word(asd_ha, CSEQ_RESP_LEN, 0);
568 asd_write_reg_word(asd_ha, CSEQ_TMF_SCBPTR, 0);
569 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_PREV_SCB, 0);
570 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_HEAD, 0);
571 asd_write_reg_word(asd_ha, CSEQ_CLEAR_LU_HEAD, 0);
572 asd_write_reg_byte(asd_ha, CSEQ_TMF_OPCODE, 0);
573 asd_write_reg_byte(asd_ha, CSEQ_SCRATCH_FLAGS, 0);
574 asd_write_reg_word(asd_ha, CSEQ_HSB_SITE, 0);
575 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_SCB_SITE,
576 (u16)last_scb_site_no+1);
577 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_DDB_SITE,
578 (u16)asd_ha->hw_prof.max_ddbs);
579
580
581 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR, 0);
582 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR + 4, 0);
583 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK, 0);
584 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK + 4, 0);
585
586
587
588 asd_write_reg_addr(asd_ha, CSEQ_HQ_NEW_POINTER,
589 asd_ha->seq.next_scb.dma_handle);
590 ASD_DPRINTK("First SCB dma_handle: 0x%llx\n",
591 (unsigned long long)asd_ha->seq.next_scb.dma_handle);
592
593
594 asd_write_reg_addr(asd_ha, CSEQ_HQ_DONE_BASE,
595 asd_ha->seq.actual_dl->dma_handle);
596
597
598
599 asd_write_reg_dword(asd_ha, CSEQ_HQ_DONE_POINTER,
600 ASD_BUSADDR_LO(asd_ha->seq.actual_dl->dma_handle));
601
602 asd_write_reg_byte(asd_ha, CSEQ_HQ_DONE_PASS, ASD_DEF_DL_TOGGLE);
603
604
605}
606
607
608
609
610
611
612
613
614static void asd_init_cseq_scratch(struct asd_ha_struct *asd_ha)
615{
616 asd_init_cseq_mip(asd_ha);
617 asd_init_cseq_mdp(asd_ha);
618}
619
620
621
622
623
624static void asd_init_lseq_mip(struct asd_ha_struct *asd_ha, u8 lseq)
625{
626 int i;
627
628
629 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_HEAD(lseq), 0xFFFF);
630 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_TAIL(lseq), 0xFFFF);
631 asd_write_reg_byte(asd_ha, LmSEQ_LINK_NUMBER(lseq), lseq);
632 asd_write_reg_byte(asd_ha, LmSEQ_SCRATCH_FLAGS(lseq),
633 ASD_NOTIFY_ENABLE_SPINUP);
634 asd_write_reg_dword(asd_ha, LmSEQ_CONNECTION_STATE(lseq),0x08000000);
635 asd_write_reg_word(asd_ha, LmSEQ_CONCTL(lseq), 0);
636 asd_write_reg_byte(asd_ha, LmSEQ_CONSTAT(lseq), 0);
637 asd_write_reg_byte(asd_ha, LmSEQ_CONNECTION_MODES(lseq), 0);
638 asd_write_reg_word(asd_ha, LmSEQ_REG1_ISR(lseq), 0);
639 asd_write_reg_word(asd_ha, LmSEQ_REG2_ISR(lseq), 0);
640 asd_write_reg_word(asd_ha, LmSEQ_REG3_ISR(lseq), 0);
641 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq), 0);
642 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq)+4, 0);
643
644
645 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR0(lseq), 0xFFFF);
646 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR1(lseq), 0xFFFF);
647 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR2(lseq), 0xFFFF);
648 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR3(lseq), 0xFFFF);
649 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE0(lseq), 0);
650 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE1(lseq), 0);
651 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE2(lseq), 0);
652 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE3(lseq), 0);
653 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_HEAD(lseq), 0);
654 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_TAIL(lseq), 0);
655 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_BUF_AVAIL(lseq), 0);
656 asd_write_reg_dword(asd_ha, LmSEQ_TIMEOUT_CONST(lseq), 0);
657 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_SINDEX(lseq), 0);
658 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_DINDEX(lseq), 0);
659
660
661 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR0(lseq), 0xFFFF);
662 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR1(lseq), 0xFFFF);
663 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR2(lseq), 0xFFFF);
664 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR3(lseq), 0xFFFF);
665 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD0(lseq), 0);
666 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD1(lseq), 0);
667 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD2(lseq), 0);
668 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD3(lseq), 0);
669 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_HEAD(lseq), 0);
670 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_TAIL(lseq), 0);
671 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_BUFS_AVAIL(lseq), 0);
672 for (i = 0; i < 12; i += 4)
673 asd_write_reg_dword(asd_ha, LmSEQ_ATA_SCR_REGS(lseq) + i, 0);
674
675
676
677
678 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TMR_TOUT_CONST(lseq),
679 ASD_DEV_PRESENT_TIMEOUT);
680
681
682 asd_write_reg_dword(asd_ha, LmSEQ_SATA_INTERLOCK_TIMEOUT(lseq),
683 ASD_SATA_INTERLOCK_TIMEOUT);
684
685
686
687 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMEOUT(lseq),
688 ASD_STP_SHUTDOWN_TIMEOUT);
689
690 asd_write_reg_dword(asd_ha, LmSEQ_SRST_ASSERT_TIMEOUT(lseq),
691 ASD_SRST_ASSERT_TIMEOUT);
692
693 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMEOUT(lseq),
694 ASD_RCV_FIS_TIMEOUT);
695
696 asd_write_reg_dword(asd_ha, LmSEQ_ONE_MILLISEC_TIMEOUT(lseq),
697 ASD_ONE_MILLISEC_TIMEOUT);
698
699
700 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(lseq),
701 ASD_TEN_MILLISEC_TIMEOUT);
702
703 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMEOUT(lseq),
704 ASD_SMP_RCV_TIMEOUT);
705}
706
707
708
709
710
711static void asd_init_lseq_mdp(struct asd_ha_struct *asd_ha, int lseq)
712{
713 int i;
714 u32 moffs;
715 u16 ret_addr[] = {
716 0xFFFF,
717 0xFFFF,
718 mode2_task,
719 0,
720 0xFFFF,
721 0xFFFF,
722 };
723
724
725
726
727
728 for (i = 0; i < 3; i++) {
729 moffs = i * LSEQ_MODE_SCRATCH_SIZE;
730 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR(lseq)+moffs,
731 ret_addr[i]);
732 asd_write_reg_word(asd_ha, LmSEQ_REG0_MODE(lseq)+moffs, 0);
733 asd_write_reg_word(asd_ha, LmSEQ_MODE_FLAGS(lseq)+moffs, 0);
734 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR2(lseq)+moffs,0xFFFF);
735 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR1(lseq)+moffs,0xFFFF);
736 asd_write_reg_byte(asd_ha, LmSEQ_OPCODE_TO_CSEQ(lseq)+moffs,0);
737 asd_write_reg_word(asd_ha, LmSEQ_DATA_TO_CSEQ(lseq)+moffs,0);
738 }
739
740
741
742 asd_write_reg_word(asd_ha,
743 LmSEQ_RET_ADDR(lseq)+LSEQ_MODE5_PAGE0_OFFSET,
744 ret_addr[5]);
745 asd_write_reg_word(asd_ha,
746 LmSEQ_REG0_MODE(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
747 asd_write_reg_word(asd_ha,
748 LmSEQ_MODE_FLAGS(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
749 asd_write_reg_word(asd_ha,
750 LmSEQ_RET_ADDR2(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
751 asd_write_reg_word(asd_ha,
752 LmSEQ_RET_ADDR1(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
753 asd_write_reg_byte(asd_ha,
754 LmSEQ_OPCODE_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
755 asd_write_reg_word(asd_ha,
756 LmSEQ_DATA_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
757
758
759 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_DDB_SITE(lseq),
760 (u16)asd_ha->hw_prof.max_ddbs);
761 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_TRANS_CTX(lseq), 0);
762 asd_write_reg_word(asd_ha, LmSEQ_RESP_LEN(lseq), 0);
763 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_SCB_SITE(lseq),
764 (u16)last_scb_site_no+1);
765 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq),
766 (u16) ((LmM0INTEN_MASK & 0xFFFF0000) >> 16));
767 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq) + 2,
768 (u16) LmM0INTEN_MASK & 0xFFFF);
769 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_FRM_LEN(lseq), 0);
770 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_PROTOCOL(lseq), 0);
771 asd_write_reg_byte(asd_ha, LmSEQ_RESP_STATUS(lseq), 0);
772 asd_write_reg_byte(asd_ha, LmSEQ_LAST_LOADED_SGE(lseq), 0);
773 asd_write_reg_word(asd_ha, LmSEQ_SAVE_SCBPTR(lseq), 0);
774
775
776 asd_write_reg_word(asd_ha, LmSEQ_Q_XMIT_HEAD(lseq), 0xFFFF);
777 asd_write_reg_word(asd_ha, LmSEQ_M1_EMPTY_TRANS_CTX(lseq), 0);
778 asd_write_reg_word(asd_ha, LmSEQ_INI_CONN_TAG(lseq), 0);
779 asd_write_reg_byte(asd_ha, LmSEQ_FAILED_OPEN_STATUS(lseq), 0);
780 asd_write_reg_byte(asd_ha, LmSEQ_XMIT_REQUEST_TYPE(lseq), 0);
781 asd_write_reg_byte(asd_ha, LmSEQ_M1_RESP_STATUS(lseq), 0);
782 asd_write_reg_byte(asd_ha, LmSEQ_M1_LAST_LOADED_SGE(lseq), 0);
783 asd_write_reg_word(asd_ha, LmSEQ_M1_SAVE_SCBPTR(lseq), 0);
784
785
786 asd_write_reg_word(asd_ha, LmSEQ_PORT_COUNTER(lseq), 0);
787 asd_write_reg_word(asd_ha, LmSEQ_PM_TABLE_PTR(lseq), 0);
788 asd_write_reg_word(asd_ha, LmSEQ_SATA_INTERLOCK_TMR_SAVE(lseq), 0);
789 asd_write_reg_word(asd_ha, LmSEQ_IP_BITL(lseq), 0);
790 asd_write_reg_word(asd_ha, LmSEQ_COPY_SMP_CONN_TAG(lseq), 0);
791 asd_write_reg_byte(asd_ha, LmSEQ_P0M2_OFFS1AH(lseq), 0);
792
793
794 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_STATUS(lseq), 0);
795 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_MODE(lseq), 0);
796 asd_write_reg_word(asd_ha, LmSEQ_Q_LINK_HEAD(lseq), 0xFFFF);
797 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_ERR(lseq), 0);
798 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_SIGNALS(lseq), 0);
799 asd_write_reg_byte(asd_ha, LmSEQ_SAS_RESET_MODE(lseq), 0);
800 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RESET_RETRY_COUNT(lseq), 0);
801 asd_write_reg_byte(asd_ha, LmSEQ_NUM_LINK_RESET_RETRIES(lseq), 0);
802 asd_write_reg_word(asd_ha, LmSEQ_OOB_INT_ENABLES(lseq), 0);
803
804
805
806
807 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_TIMEOUT(lseq),
808 ASD_NOTIFY_TIMEOUT - 1);
809
810 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_DOWN_COUNT(lseq),
811 ASD_NOTIFY_DOWN_COUNT);
812 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(lseq),
813 ASD_NOTIFY_DOWN_COUNT);
814
815
816 for (i = 0; i < 2; i++) {
817 int j;
818
819 moffs = LSEQ_PAGE_SIZE + i*LSEQ_MODE_SCRATCH_SIZE;
820
821 for (j = 0; j < LSEQ_PAGE_SIZE; j += 4)
822 asd_write_reg_dword(asd_ha, LmSCRATCH(lseq)+moffs+j,0);
823 }
824
825
826 asd_write_reg_dword(asd_ha, LmSEQ_INVALID_DWORD_COUNT(lseq), 0);
827 asd_write_reg_dword(asd_ha, LmSEQ_DISPARITY_ERROR_COUNT(lseq), 0);
828 asd_write_reg_dword(asd_ha, LmSEQ_LOSS_OF_SYNC_COUNT(lseq), 0);
829
830
831 for (i = 0; i < LSEQ_PAGE_SIZE; i+=4)
832 asd_write_reg_dword(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq)+i, 0);
833 asd_write_reg_byte(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq), 0xFF);
834 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq), 0xFF);
835 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+1,0xFF);
836 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+2,0xFF);
837 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq), 0xFF);
838 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+1, 0xFF);
839 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+2, 0xFF);
840 asd_write_reg_dword(asd_ha, LmSEQ_DATA_OFFSET(lseq), 0xFFFFFFFF);
841
842
843 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMER_TERM_TS(lseq), 0);
844 asd_write_reg_byte(asd_ha, LmSEQ_DEVICE_BITS(lseq), 0);
845 asd_write_reg_word(asd_ha, LmSEQ_SDB_DDB(lseq), 0);
846 asd_write_reg_byte(asd_ha, LmSEQ_SDB_NUM_TAGS(lseq), 0);
847 asd_write_reg_byte(asd_ha, LmSEQ_SDB_CURR_TAG(lseq), 0);
848
849
850 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq), 0);
851 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq)+4, 0);
852 asd_write_reg_dword(asd_ha, LmSEQ_OPEN_TIMER_TERM_TS(lseq), 0);
853 asd_write_reg_dword(asd_ha, LmSEQ_SRST_AS_TIMER_TERM_TS(lseq), 0);
854 asd_write_reg_dword(asd_ha, LmSEQ_LAST_LOADED_SG_EL(lseq), 0);
855
856
857
858
859 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(lseq),0);
860 asd_write_reg_dword(asd_ha, LmSEQ_CLOSE_TIMER_TERM_TS(lseq), 0);
861 asd_write_reg_dword(asd_ha, LmSEQ_BREAK_TIMER_TERM_TS(lseq), 0);
862 asd_write_reg_dword(asd_ha, LmSEQ_DWS_RESET_TIMER_TERM_TS(lseq), 0);
863 asd_write_reg_dword(asd_ha,LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(lseq),0);
864 asd_write_reg_dword(asd_ha, LmSEQ_MCTL_TIMER_TERM_TS(lseq), 0);
865
866
867 asd_write_reg_dword(asd_ha, LmSEQ_COMINIT_TIMER_TERM_TS(lseq), 0);
868 asd_write_reg_dword(asd_ha, LmSEQ_RCV_ID_TIMER_TERM_TS(lseq), 0);
869 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMER_TERM_TS(lseq), 0);
870 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TIMER_TERM_TS(lseq), 0);
871}
872
873
874
875
876
877static void asd_init_lseq_scratch(struct asd_ha_struct *asd_ha)
878{
879 u8 lseq;
880 u8 lseq_mask;
881
882 lseq_mask = asd_ha->hw_prof.enabled_phys;
883 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
884 asd_init_lseq_mip(asd_ha, lseq);
885 asd_init_lseq_mdp(asd_ha, lseq);
886 }
887}
888
889
890
891
892
893
894
895
896
897static void asd_init_scb_sites(struct asd_ha_struct *asd_ha)
898{
899 u16 site_no;
900 u16 max_scbs = 0;
901
902 for (site_no = asd_ha->hw_prof.max_scbs-1;
903 site_no != (u16) -1;
904 site_no--) {
905 u16 i;
906
907
908 for (i = 0; i < ASD_SCB_SIZE; i += 4)
909 asd_scbsite_write_dword(asd_ha, site_no, i, 0);
910
911
912 asd_scbsite_write_byte(asd_ha, site_no,
913 offsetof(struct scb_header, opcode),
914 0xFF);
915
916
917
918
919 asd_scbsite_write_byte(asd_ha, site_no, 0x49, 0x01);
920
921
922
923 if (!SCB_SITE_VALID(site_no))
924 continue;
925
926 if (last_scb_site_no == 0)
927 last_scb_site_no = site_no;
928
929
930
931
932
933
934 asd_scbsite_write_word(asd_ha, site_no, 0, first_scb_site_no);
935
936 first_scb_site_no = site_no;
937 max_scbs++;
938 }
939 asd_ha->hw_prof.max_scbs = max_scbs;
940 ASD_DPRINTK("max_scbs:%d\n", asd_ha->hw_prof.max_scbs);
941 ASD_DPRINTK("first_scb_site_no:0x%x\n", first_scb_site_no);
942 ASD_DPRINTK("last_scb_site_no:0x%x\n", last_scb_site_no);
943}
944
945
946
947
948
949static void asd_init_cseq_cio(struct asd_ha_struct *asd_ha)
950{
951 int i;
952
953 asd_write_reg_byte(asd_ha, CSEQCOMINTEN, 0);
954 asd_write_reg_byte(asd_ha, CSEQDLCTL, ASD_DL_SIZE_BITS);
955 asd_write_reg_byte(asd_ha, CSEQDLOFFS, 0);
956 asd_write_reg_byte(asd_ha, CSEQDLOFFS+1, 0);
957 asd_ha->seq.scbpro = 0;
958 asd_write_reg_dword(asd_ha, SCBPRO, 0);
959 asd_write_reg_dword(asd_ha, CSEQCON, 0);
960
961
962
963
964
965 asd_write_reg_word(asd_ha, CM11INTVEC0, cseq_vecs[0]);
966 asd_write_reg_word(asd_ha, CM11INTVEC1, cseq_vecs[1]);
967 asd_write_reg_word(asd_ha, CM11INTVEC2, cseq_vecs[2]);
968
969
970 asd_write_reg_byte(asd_ha, CARP2INTEN, EN_ARP2HALTC);
971
972
973 asd_write_reg_byte(asd_ha, CSCRATCHPAGE, 0x04);
974
975
976
977 for (i = 0; i < 9; i++)
978 asd_write_reg_byte(asd_ha, CMnSCRATCHPAGE(i), 0);
979
980
981 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
982
983 for (i = 0; i < 8; i++) {
984
985 asd_write_reg_dword(asd_ha, CMnINTEN(i), EN_CMnRSPMBXF);
986
987 asd_write_reg_dword(asd_ha, CMnREQMBX(i), 0);
988 }
989}
990
991
992
993
994
995static void asd_init_lseq_cio(struct asd_ha_struct *asd_ha, int lseq)
996{
997 u8 *sas_addr;
998 int i;
999
1000
1001 asd_write_reg_dword(asd_ha, LmARP2INTEN(lseq), EN_ARP2HALTC);
1002
1003 asd_write_reg_byte(asd_ha, LmSCRATCHPAGE(lseq), 0);
1004
1005
1006 for (i = 0; i < 3; i++)
1007 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, i), 0);
1008
1009
1010 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, 5), 0);
1011
1012 asd_write_reg_dword(asd_ha, LmRSPMBX(lseq), 0);
1013
1014
1015 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 0), LmM0INTEN_MASK);
1016 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 0), 0xFFFFFFFF);
1017
1018 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 1), LmM1INTEN_MASK);
1019 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 1), 0xFFFFFFFF);
1020
1021 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 2), LmM2INTEN_MASK);
1022 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 2), 0xFFFFFFFF);
1023
1024 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 5), LmM5INTEN_MASK);
1025 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 5), 0xFFFFFFFF);
1026
1027
1028 asd_write_reg_byte(asd_ha, LmHWTSTATEN(lseq), LmHWTSTATEN_MASK);
1029
1030
1031 asd_write_reg_dword(asd_ha, LmPRIMSTAT0EN(lseq), LmPRIMSTAT0EN_MASK);
1032 asd_write_reg_dword(asd_ha, LmPRIMSTAT1EN(lseq), LmPRIMSTAT1EN_MASK);
1033
1034
1035 asd_write_reg_dword(asd_ha, LmFRMERREN(lseq), LmFRMERREN_MASK);
1036 asd_write_reg_byte(asd_ha, LmMnHOLDLVL(lseq, 0), 0x50);
1037
1038
1039 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 0), LmMnXFRLVL_512);
1040
1041 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 1), LmMnXFRLVL_256);
1042
1043
1044 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1045
1046
1047 asd_write_reg_dword(asd_ha, LmMODECTL(lseq), LmBLIND48);
1048 asd_write_reg_word(asd_ha, LmM3SATATIMER(lseq),
1049 ASD_SATA_INTERLOCK_TIMEOUT);
1050
1051 (void) asd_read_reg_dword(asd_ha, LmREQMBX(lseq));
1052
1053
1054 asd_write_reg_dword(asd_ha, LmPRMSTAT0(lseq), 0xFFFFFFFF);
1055 asd_write_reg_dword(asd_ha, LmPRMSTAT1(lseq), 0xFFFFFFFF);
1056
1057
1058 asd_write_reg_byte(asd_ha, LmHWTSTAT(lseq), 0xFF);
1059
1060
1061 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 0), 0xFF);
1062 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 1), 0xFF);
1063
1064
1065 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 0), 0xFF);
1066 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 1), 0xFF);
1067
1068
1069 asd_write_reg_byte(asd_ha, LmMnBUFSTAT(lseq, 0), LmMnBUFPERR);
1070
1071
1072 asd_write_reg_dword(asd_ha, LmMnFRMERR(lseq, 0), 0xFFFFFFFF);
1073
1074
1075 asd_write_reg_byte(asd_ha, LmARP2INTCTL(lseq), RSTINTCTL);
1076
1077
1078 sas_addr = asd_ha->phys[lseq].phy_desc->sas_addr;
1079 for (i = 0; i < SAS_ADDR_SIZE; i++)
1080 asd_write_reg_byte(asd_ha, LmWWN(lseq) + i, sas_addr[i]);
1081
1082
1083 asd_write_reg_byte(asd_ha, LmMnXMTSIZE(lseq, 1), 0);
1084
1085
1086 asd_write_reg_word(asd_ha, LmBITL_TIMER(lseq), 9);
1087
1088
1089 asd_write_reg_byte(asd_ha, LmMnSATAFS(lseq, 1), 0x80);
1090
1091
1092
1093 asd_write_reg_word(asd_ha, LmM3INTVEC0(lseq), lseq_vecs[0]);
1094 asd_write_reg_word(asd_ha, LmM3INTVEC1(lseq), lseq_vecs[1]);
1095 asd_write_reg_word(asd_ha, LmM3INTVEC2(lseq), lseq_vecs[2]);
1096 asd_write_reg_word(asd_ha, LmM3INTVEC3(lseq), lseq_vecs[3]);
1097 asd_write_reg_word(asd_ha, LmM3INTVEC4(lseq), lseq_vecs[4]);
1098 asd_write_reg_word(asd_ha, LmM3INTVEC5(lseq), lseq_vecs[5]);
1099 asd_write_reg_word(asd_ha, LmM3INTVEC6(lseq), lseq_vecs[6]);
1100 asd_write_reg_word(asd_ha, LmM3INTVEC7(lseq), lseq_vecs[7]);
1101 asd_write_reg_word(asd_ha, LmM3INTVEC8(lseq), lseq_vecs[8]);
1102 asd_write_reg_word(asd_ha, LmM3INTVEC9(lseq), lseq_vecs[9]);
1103 asd_write_reg_word(asd_ha, LmM3INTVEC10(lseq), lseq_vecs[10]);
1104
1105
1106
1107
1108 asd_write_reg_dword(asd_ha, LmCONTROL(lseq),
1109 (LEDTIMER | LEDMODE_TXRX | LEDTIMERS_100ms));
1110
1111
1112 asd_write_reg_byte(asd_ha, LmM1SASALIGN(lseq), SAS_ALIGN_DEFAULT);
1113 asd_write_reg_byte(asd_ha, LmM1STPALIGN(lseq), STP_ALIGN_DEFAULT);
1114}
1115
1116
1117
1118
1119
1120
1121static void asd_post_init_cseq(struct asd_ha_struct *asd_ha)
1122{
1123 int i;
1124
1125 for (i = 0; i < 8; i++)
1126 asd_write_reg_dword(asd_ha, CMnINT(i), 0xFFFFFFFF);
1127 for (i = 0; i < 8; i++)
1128 asd_read_reg_dword(asd_ha, CMnRSPMBX(i));
1129
1130 asd_write_reg_byte(asd_ha, CARP2INTCTL, RSTINTCTL);
1131}
1132
1133
1134
1135
1136
1137
1138
1139static void asd_init_ddb_0(struct asd_ha_struct *asd_ha)
1140{
1141 int i;
1142
1143
1144 for (i = 0; i < sizeof(struct asd_ddb_seq_shared); i+=4)
1145 asd_ddbsite_write_dword(asd_ha, 0, i, 0);
1146
1147 asd_ddbsite_write_word(asd_ha, 0,
1148 offsetof(struct asd_ddb_seq_shared, q_free_ddb_head), 0);
1149 asd_ddbsite_write_word(asd_ha, 0,
1150 offsetof(struct asd_ddb_seq_shared, q_free_ddb_tail),
1151 asd_ha->hw_prof.max_ddbs-1);
1152 asd_ddbsite_write_word(asd_ha, 0,
1153 offsetof(struct asd_ddb_seq_shared, q_free_ddb_cnt), 0);
1154 asd_ddbsite_write_word(asd_ha, 0,
1155 offsetof(struct asd_ddb_seq_shared, q_used_ddb_head), 0xFFFF);
1156 asd_ddbsite_write_word(asd_ha, 0,
1157 offsetof(struct asd_ddb_seq_shared, q_used_ddb_tail), 0xFFFF);
1158 asd_ddbsite_write_word(asd_ha, 0,
1159 offsetof(struct asd_ddb_seq_shared, shared_mem_lock), 0);
1160 asd_ddbsite_write_word(asd_ha, 0,
1161 offsetof(struct asd_ddb_seq_shared, smp_conn_tag), 0);
1162 asd_ddbsite_write_word(asd_ha, 0,
1163 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_cnt), 0);
1164 asd_ddbsite_write_word(asd_ha, 0,
1165 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_thresh),
1166 asd_ha->hw_prof.num_phys * 2);
1167 asd_ddbsite_write_byte(asd_ha, 0,
1168 offsetof(struct asd_ddb_seq_shared, settable_max_contexts),0);
1169 asd_ddbsite_write_byte(asd_ha, 0,
1170 offsetof(struct asd_ddb_seq_shared, conn_not_active), 0xFF);
1171 asd_ddbsite_write_byte(asd_ha, 0,
1172 offsetof(struct asd_ddb_seq_shared, phy_is_up), 0x00);
1173
1174 set_bit(0, asd_ha->hw_prof.ddb_bitmap);
1175}
1176
1177static void asd_seq_init_ddb_sites(struct asd_ha_struct *asd_ha)
1178{
1179 unsigned int i;
1180 unsigned int ddb_site;
1181
1182 for (ddb_site = 0 ; ddb_site < ASD_MAX_DDBS; ddb_site++)
1183 for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4)
1184 asd_ddbsite_write_dword(asd_ha, ddb_site, i, 0);
1185}
1186
1187
1188
1189
1190
1191static void asd_seq_setup_seqs(struct asd_ha_struct *asd_ha)
1192{
1193 int lseq;
1194 u8 lseq_mask;
1195
1196
1197 asd_seq_init_ddb_sites(asd_ha);
1198
1199
1200
1201 asd_init_scb_sites(asd_ha);
1202
1203
1204 asd_init_cseq_scratch(asd_ha);
1205
1206
1207 asd_init_lseq_scratch(asd_ha);
1208
1209
1210 asd_init_cseq_cio(asd_ha);
1211
1212 asd_init_ddb_0(asd_ha);
1213
1214
1215 lseq_mask = asd_ha->hw_prof.enabled_phys;
1216 for_each_sequencer(lseq_mask, lseq_mask, lseq)
1217 asd_init_lseq_cio(asd_ha, lseq);
1218 asd_post_init_cseq(asd_ha);
1219}
1220
1221
1222
1223
1224
1225
1226static int asd_seq_start_cseq(struct asd_ha_struct *asd_ha)
1227{
1228
1229 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
1230
1231
1232 return asd_unpause_cseq(asd_ha);
1233}
1234
1235
1236
1237
1238
1239
1240static int asd_seq_start_lseq(struct asd_ha_struct *asd_ha, int lseq)
1241{
1242
1243 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1244
1245
1246 return asd_seq_unpause_lseq(asd_ha, lseq);
1247}
1248
1249int asd_release_firmware(void)
1250{
1251 if (sequencer_fw)
1252 release_firmware(sequencer_fw);
1253 return 0;
1254}
1255
1256static int asd_request_firmware(struct asd_ha_struct *asd_ha)
1257{
1258 int err, i;
1259 struct sequencer_file_header header, *hdr_ptr;
1260 u32 csum = 0;
1261 u16 *ptr_cseq_vecs, *ptr_lseq_vecs;
1262
1263 if (sequencer_fw)
1264
1265 return 0;
1266
1267 err = request_firmware(&sequencer_fw,
1268 SAS_RAZOR_SEQUENCER_FW_FILE,
1269 &asd_ha->pcidev->dev);
1270 if (err)
1271 return err;
1272
1273 hdr_ptr = (struct sequencer_file_header *)sequencer_fw->data;
1274
1275 header.csum = le32_to_cpu(hdr_ptr->csum);
1276 header.major = le32_to_cpu(hdr_ptr->major);
1277 header.minor = le32_to_cpu(hdr_ptr->minor);
1278 header.cseq_table_offset = le32_to_cpu(hdr_ptr->cseq_table_offset);
1279 header.cseq_table_size = le32_to_cpu(hdr_ptr->cseq_table_size);
1280 header.lseq_table_offset = le32_to_cpu(hdr_ptr->lseq_table_offset);
1281 header.lseq_table_size = le32_to_cpu(hdr_ptr->lseq_table_size);
1282 header.cseq_code_offset = le32_to_cpu(hdr_ptr->cseq_code_offset);
1283 header.cseq_code_size = le32_to_cpu(hdr_ptr->cseq_code_size);
1284 header.lseq_code_offset = le32_to_cpu(hdr_ptr->lseq_code_offset);
1285 header.lseq_code_size = le32_to_cpu(hdr_ptr->lseq_code_size);
1286 header.mode2_task = le16_to_cpu(hdr_ptr->mode2_task);
1287 header.cseq_idle_loop = le16_to_cpu(hdr_ptr->cseq_idle_loop);
1288 header.lseq_idle_loop = le16_to_cpu(hdr_ptr->lseq_idle_loop);
1289
1290 for (i = sizeof(header.csum); i < sequencer_fw->size; i++)
1291 csum += sequencer_fw->data[i];
1292
1293 if (csum != header.csum) {
1294 asd_printk("Firmware file checksum mismatch\n");
1295 return -EINVAL;
1296 }
1297
1298 if (header.cseq_table_size != CSEQ_NUM_VECS ||
1299 header.lseq_table_size != LSEQ_NUM_VECS) {
1300 asd_printk("Firmware file table size mismatch\n");
1301 return -EINVAL;
1302 }
1303
1304 asd_printk("Found sequencer Firmware version %d.%d (%s)\n",
1305 header.major, header.minor, hdr_ptr->version);
1306
1307 if (header.major != SAS_RAZOR_SEQUENCER_FW_MAJOR) {
1308 asd_printk("Firmware Major Version Mismatch;"
1309 "driver requires version %d.X",
1310 SAS_RAZOR_SEQUENCER_FW_MAJOR);
1311 return -EINVAL;
1312 }
1313
1314 ptr_cseq_vecs = (u16 *)&sequencer_fw->data[header.cseq_table_offset];
1315 ptr_lseq_vecs = (u16 *)&sequencer_fw->data[header.lseq_table_offset];
1316 mode2_task = header.mode2_task;
1317 cseq_idle_loop = header.cseq_idle_loop;
1318 lseq_idle_loop = header.lseq_idle_loop;
1319
1320 for (i = 0; i < CSEQ_NUM_VECS; i++)
1321 cseq_vecs[i] = le16_to_cpu(ptr_cseq_vecs[i]);
1322
1323 for (i = 0; i < LSEQ_NUM_VECS; i++)
1324 lseq_vecs[i] = le16_to_cpu(ptr_lseq_vecs[i]);
1325
1326 cseq_code = &sequencer_fw->data[header.cseq_code_offset];
1327 cseq_code_size = header.cseq_code_size;
1328 lseq_code = &sequencer_fw->data[header.lseq_code_offset];
1329 lseq_code_size = header.lseq_code_size;
1330
1331 return 0;
1332}
1333
1334int asd_init_seqs(struct asd_ha_struct *asd_ha)
1335{
1336 int err;
1337
1338 err = asd_request_firmware(asd_ha);
1339
1340 if (err) {
1341 asd_printk("Failed to load sequencer firmware file %s, error %d\n",
1342 SAS_RAZOR_SEQUENCER_FW_FILE, err);
1343 return err;
1344 }
1345
1346 err = asd_seq_download_seqs(asd_ha);
1347 if (err) {
1348 asd_printk("couldn't download sequencers for %s\n",
1349 pci_name(asd_ha->pcidev));
1350 return err;
1351 }
1352
1353 asd_seq_setup_seqs(asd_ha);
1354
1355 return 0;
1356}
1357
1358int asd_start_seqs(struct asd_ha_struct *asd_ha)
1359{
1360 int err;
1361 u8 lseq_mask;
1362 int lseq;
1363
1364 err = asd_seq_start_cseq(asd_ha);
1365 if (err) {
1366 asd_printk("couldn't start CSEQ for %s\n",
1367 pci_name(asd_ha->pcidev));
1368 return err;
1369 }
1370
1371 lseq_mask = asd_ha->hw_prof.enabled_phys;
1372 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
1373 err = asd_seq_start_lseq(asd_ha, lseq);
1374 if (err) {
1375 asd_printk("coudln't start LSEQ %d for %s\n", lseq,
1376 pci_name(asd_ha->pcidev));
1377 return err;
1378 }
1379 }
1380
1381 return 0;
1382}
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401void asd_update_port_links(struct asd_ha_struct *asd_ha, struct asd_phy *phy)
1402{
1403 const u8 phy_mask = (u8) phy->asd_port->phy_mask;
1404 u8 phy_is_up;
1405 u8 mask;
1406 int i, err;
1407 unsigned long flags;
1408
1409 spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
1410 for_each_phy(phy_mask, mask, i)
1411 asd_ddbsite_write_byte(asd_ha, 0,
1412 offsetof(struct asd_ddb_seq_shared,
1413 port_map_by_links)+i,phy_mask);
1414
1415 for (i = 0; i < 12; i++) {
1416 phy_is_up = asd_ddbsite_read_byte(asd_ha, 0,
1417 offsetof(struct asd_ddb_seq_shared, phy_is_up));
1418 err = asd_ddbsite_update_byte(asd_ha, 0,
1419 offsetof(struct asd_ddb_seq_shared, phy_is_up),
1420 phy_is_up,
1421 phy_is_up | phy_mask);
1422 if (!err)
1423 break;
1424 else if (err == -EFAULT) {
1425 asd_printk("phy_is_up: parity error in DDB 0\n");
1426 break;
1427 }
1428 }
1429 spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
1430
1431 if (err)
1432 asd_printk("couldn't update DDB 0:error:%d\n", err);
1433}
1434
1435MODULE_FIRMWARE(SAS_RAZOR_SEQUENCER_FW_FILE);
1436