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50#ifndef _IPS_H_
51 #define _IPS_H_
52
53#include <linux/version.h>
54#include <linux/nmi.h>
55 #include <asm/uaccess.h>
56 #include <asm/io.h>
57
58
59
60
61 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
62 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
63 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
64 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
65 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
66 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
67 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
68 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
69 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS)
70 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO)
71 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
72 (IPS_IS_TROMBONE(ha) && \
73 (ips_force_i2o))) ? 1 : 0)
74 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
75 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
76 (ips_force_memio))) ? 1 : 0)
77
78 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
79 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
80 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
81 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
82
83 #define IPS_PRINTK(level, pcidev, format, arg...) \
84 dev_printk(level , &((pcidev)->dev) , format , ## arg)
85
86 #define MDELAY(n) \
87 do { \
88 mdelay(n); \
89 touch_nmi_watchdog(); \
90 } while (0)
91
92 #ifndef min
93 #define min(x,y) ((x) < (y) ? x : y)
94 #endif
95
96 #ifndef __iomem
97 #define __iomem
98 #endif
99
100 #define pci_dma_hi32(a) ((a >> 16) >> 16)
101 #define pci_dma_lo32(a) (a & 0xffffffff)
102
103 #if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
104 #define IPS_ENABLE_DMA64 (1)
105 #else
106 #define IPS_ENABLE_DMA64 (0)
107 #endif
108
109
110
111
112 #define IPS_REG_HISR 0x08
113 #define IPS_REG_CCSAR 0x10
114 #define IPS_REG_CCCR 0x14
115 #define IPS_REG_SQHR 0x20
116 #define IPS_REG_SQTR 0x24
117 #define IPS_REG_SQER 0x28
118 #define IPS_REG_SQSR 0x2C
119 #define IPS_REG_SCPR 0x05
120 #define IPS_REG_ISPR 0x06
121 #define IPS_REG_CBSP 0x07
122 #define IPS_REG_FLAP 0x18
123 #define IPS_REG_FLDP 0x1C
124 #define IPS_REG_NDAE 0x38
125 #define IPS_REG_I2O_INMSGQ 0x40
126 #define IPS_REG_I2O_OUTMSGQ 0x44
127 #define IPS_REG_I2O_HIR 0x30
128 #define IPS_REG_I960_IDR 0x20
129 #define IPS_REG_I960_MSG0 0x18
130 #define IPS_REG_I960_MSG1 0x1C
131 #define IPS_REG_I960_OIMR 0x34
132
133
134
135
136 #define IPS_BIT_GHI 0x04
137 #define IPS_BIT_SQO 0x02
138 #define IPS_BIT_SCE 0x01
139 #define IPS_BIT_SEM 0x08
140 #define IPS_BIT_ILE 0x10
141 #define IPS_BIT_START_CMD 0x101A
142 #define IPS_BIT_START_STOP 0x0002
143 #define IPS_BIT_RST 0x80
144 #define IPS_BIT_EBM 0x02
145 #define IPS_BIT_EI 0x80
146 #define IPS_BIT_OP 0x01
147 #define IPS_BIT_I2O_OPQI 0x08
148 #define IPS_BIT_I960_MSG0I 0x01
149 #define IPS_BIT_I960_MSG1I 0x02
150
151
152
153
154 #define IPS_CMD_GET_LD_INFO 0x19
155 #define IPS_CMD_GET_SUBSYS 0x40
156 #define IPS_CMD_READ_CONF 0x38
157 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
158 #define IPS_CMD_READ 0x02
159 #define IPS_CMD_WRITE 0x03
160 #define IPS_CMD_FFDC 0xD7
161 #define IPS_CMD_ENQUIRY 0x05
162 #define IPS_CMD_FLUSH 0x0A
163 #define IPS_CMD_READ_SG 0x82
164 #define IPS_CMD_WRITE_SG 0x83
165 #define IPS_CMD_DCDB 0x04
166 #define IPS_CMD_DCDB_SG 0x84
167 #define IPS_CMD_EXTENDED_DCDB 0x95
168 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
169 #define IPS_CMD_CONFIG_SYNC 0x58
170 #define IPS_CMD_ERROR_TABLE 0x17
171 #define IPS_CMD_DOWNLOAD 0x20
172 #define IPS_CMD_RW_BIOSFW 0x22
173 #define IPS_CMD_GET_VERSION_INFO 0xC6
174 #define IPS_CMD_RESET_CHANNEL 0x1A
175
176
177
178
179 #define IPS_CSL 0xFF
180 #define IPS_POCL 0x30
181 #define IPS_NORM_STATE 0x00
182 #define IPS_MAX_ADAPTER_TYPES 3
183 #define IPS_MAX_ADAPTERS 16
184 #define IPS_MAX_IOCTL 1
185 #define IPS_MAX_IOCTL_QUEUE 8
186 #define IPS_MAX_QUEUE 128
187 #define IPS_BLKSIZE 512
188 #define IPS_MAX_SG 17
189 #define IPS_MAX_LD 8
190 #define IPS_MAX_CHANNELS 4
191 #define IPS_MAX_TARGETS 15
192 #define IPS_MAX_CHUNKS 16
193 #define IPS_MAX_CMDS 128
194 #define IPS_MAX_XFER 0x10000
195 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
196 #define IPS_MAX_POST_BYTES 0x02
197 #define IPS_MAX_CONFIG_BYTES 0x02
198 #define IPS_GOOD_POST_STATUS 0x80
199 #define IPS_SEM_TIMEOUT 2000
200 #define IPS_IOCTL_COMMAND 0x0D
201 #define IPS_INTR_ON 0
202 #define IPS_INTR_IORL 1
203 #define IPS_FFDC 99
204 #define IPS_ADAPTER_ID 0xF
205 #define IPS_VENDORID_IBM 0x1014
206 #define IPS_VENDORID_ADAPTEC 0x9005
207 #define IPS_DEVICEID_COPPERHEAD 0x002E
208 #define IPS_DEVICEID_MORPHEUS 0x01BD
209 #define IPS_DEVICEID_MARCO 0x0250
210 #define IPS_SUBDEVICEID_4M 0x01BE
211 #define IPS_SUBDEVICEID_4L 0x01BF
212 #define IPS_SUBDEVICEID_4MX 0x0208
213 #define IPS_SUBDEVICEID_4LX 0x020E
214 #define IPS_SUBDEVICEID_5I2 0x0259
215 #define IPS_SUBDEVICEID_5I1 0x0258
216 #define IPS_SUBDEVICEID_6M 0x0279
217 #define IPS_SUBDEVICEID_6I 0x028C
218 #define IPS_SUBDEVICEID_7k 0x028E
219 #define IPS_SUBDEVICEID_7M 0x028F
220 #define IPS_IOCTL_SIZE 8192
221 #define IPS_STATUS_SIZE 4
222 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
223 #define IPS_IMAGE_SIZE 500 * 1024
224 #define IPS_MEMMAP_SIZE 128
225 #define IPS_ONE_MSEC 1
226 #define IPS_ONE_SEC 1000
227
228
229
230
231 #define IPS_COMP_HEADS 128
232 #define IPS_COMP_SECTORS 32
233 #define IPS_NORM_HEADS 254
234 #define IPS_NORM_SECTORS 63
235
236
237
238
239 #define IPS_BASIC_STATUS_MASK 0xFF
240 #define IPS_GSC_STATUS_MASK 0x0F
241 #define IPS_CMD_SUCCESS 0x00
242 #define IPS_CMD_RECOVERED_ERROR 0x01
243 #define IPS_INVAL_OPCO 0x03
244 #define IPS_INVAL_CMD_BLK 0x04
245 #define IPS_INVAL_PARM_BLK 0x05
246 #define IPS_BUSY 0x08
247 #define IPS_CMD_CMPLT_WERROR 0x0C
248 #define IPS_LD_ERROR 0x0D
249 #define IPS_CMD_TIMEOUT 0x0E
250 #define IPS_PHYS_DRV_ERROR 0x0F
251
252
253
254
255 #define IPS_ERR_SEL_TO 0xF0
256 #define IPS_ERR_OU_RUN 0xF2
257 #define IPS_ERR_HOST_RESET 0xF7
258 #define IPS_ERR_DEV_RESET 0xF8
259 #define IPS_ERR_RECOVERY 0xFC
260 #define IPS_ERR_CKCOND 0xFF
261
262
263
264
265 #define IPS_OS_WINDOWS_NT 0x01
266 #define IPS_OS_NETWARE 0x02
267 #define IPS_OS_OPENSERVER 0x03
268 #define IPS_OS_UNIXWARE 0x04
269 #define IPS_OS_SOLARIS 0x05
270 #define IPS_OS_OS2 0x06
271 #define IPS_OS_LINUX 0x07
272 #define IPS_OS_FREEBSD 0x08
273
274
275
276
277 #define IPS_REVID_SERVERAID 0x02
278 #define IPS_REVID_NAVAJO 0x03
279 #define IPS_REVID_SERVERAID2 0x04
280 #define IPS_REVID_CLARINETP1 0x05
281 #define IPS_REVID_CLARINETP2 0x07
282 #define IPS_REVID_CLARINETP3 0x0D
283 #define IPS_REVID_TROMBONE32 0x0F
284 #define IPS_REVID_TROMBONE64 0x10
285
286
287
288
289 #define IPS_ADTYPE_SERVERAID 0x01
290 #define IPS_ADTYPE_SERVERAID2 0x02
291 #define IPS_ADTYPE_NAVAJO 0x03
292 #define IPS_ADTYPE_KIOWA 0x04
293 #define IPS_ADTYPE_SERVERAID3 0x05
294 #define IPS_ADTYPE_SERVERAID3L 0x06
295 #define IPS_ADTYPE_SERVERAID4H 0x07
296 #define IPS_ADTYPE_SERVERAID4M 0x08
297 #define IPS_ADTYPE_SERVERAID4L 0x09
298 #define IPS_ADTYPE_SERVERAID4MX 0x0A
299 #define IPS_ADTYPE_SERVERAID4LX 0x0B
300 #define IPS_ADTYPE_SERVERAID5I2 0x0C
301 #define IPS_ADTYPE_SERVERAID5I1 0x0D
302 #define IPS_ADTYPE_SERVERAID6M 0x0E
303 #define IPS_ADTYPE_SERVERAID6I 0x0F
304 #define IPS_ADTYPE_SERVERAID7t 0x10
305 #define IPS_ADTYPE_SERVERAID7k 0x11
306 #define IPS_ADTYPE_SERVERAID7M 0x12
307
308
309
310
311 #define IPS_SUCCESS 0x01
312 #define IPS_SUCCESS_IMM 0x02
313 #define IPS_FAILURE 0x04
314
315
316
317
318 #define IPS_LD_OFFLINE 0x02
319 #define IPS_LD_OKAY 0x03
320 #define IPS_LD_FREE 0x00
321 #define IPS_LD_SYS 0x06
322 #define IPS_LD_CRS 0x24
323
324
325
326
327 #define IPS_NO_DISCONNECT 0x00
328 #define IPS_DISCONNECT_ALLOWED 0x80
329 #define IPS_NO_AUTO_REQSEN 0x40
330 #define IPS_DATA_NONE 0x00
331 #define IPS_DATA_UNK 0x00
332 #define IPS_DATA_IN 0x01
333 #define IPS_DATA_OUT 0x02
334 #define IPS_TRANSFER64K 0x08
335 #define IPS_NOTIMEOUT 0x00
336 #define IPS_TIMEOUT10 0x10
337 #define IPS_TIMEOUT60 0x20
338 #define IPS_TIMEOUT20M 0x30
339
340
341
342
343 #define IPS_SCSI_INQ_TYPE_DASD 0x00
344 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
345 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
346 #define IPS_SCSI_INQ_RD_REV2 0x02
347 #define IPS_SCSI_INQ_REV2 0x02
348 #define IPS_SCSI_INQ_REV3 0x03
349 #define IPS_SCSI_INQ_Address16 0x01
350 #define IPS_SCSI_INQ_Address32 0x02
351 #define IPS_SCSI_INQ_MedChanger 0x08
352 #define IPS_SCSI_INQ_MultiPort 0x10
353 #define IPS_SCSI_INQ_EncServ 0x40
354 #define IPS_SCSI_INQ_SoftReset 0x01
355 #define IPS_SCSI_INQ_CmdQue 0x02
356 #define IPS_SCSI_INQ_Linked 0x08
357 #define IPS_SCSI_INQ_Sync 0x10
358 #define IPS_SCSI_INQ_WBus16 0x20
359 #define IPS_SCSI_INQ_WBus32 0x40
360 #define IPS_SCSI_INQ_RelAdr 0x80
361
362
363
364
365 #define IPS_SCSI_REQSEN_VALID 0x80
366 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
367 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
368
369
370
371
372 #define IPS_SCSI_MP3_SoftSector 0x01
373 #define IPS_SCSI_MP3_HardSector 0x02
374 #define IPS_SCSI_MP3_Removeable 0x04
375 #define IPS_SCSI_MP3_AllocateSurface 0x08
376
377
378
379
380
381 #define IPS_HA_ENH_SG 0x1
382
383
384
385
386 #define IPS_SCB_MAP_SG 0x00008
387 #define IPS_SCB_MAP_SINGLE 0X00010
388
389
390
391
392 #define IPS_COPPUSRCMD (('C'<<8) | 65)
393 #define IPS_COPPIOCCMD (('C'<<8) | 66)
394 #define IPS_NUMCTRLS (('C'<<8) | 68)
395 #define IPS_CTRLINFO (('C'<<8) | 69)
396
397
398 #define IPS_FW_IMAGE 0x00
399 #define IPS_BIOS_IMAGE 0x01
400 #define IPS_WRITE_FW 0x01
401 #define IPS_WRITE_BIOS 0x02
402 #define IPS_ERASE_BIOS 0x03
403 #define IPS_BIOS_HEADER 0xC0
404
405
406 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
407 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
408
409 #define IPS_SECS_MIN 60
410 #define IPS_SECS_HOUR 3600
411 #define IPS_SECS_8HOURS 28800
412 #define IPS_SECS_DAY 86400
413 #define IPS_DAYS_NORMAL_YEAR 365
414 #define IPS_DAYS_LEAP_YEAR 366
415 #define IPS_EPOCH_YEAR 1970
416
417
418
419
420 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
421 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
422 sector_t capacity, int geom[]);
423 static int ips_slave_configure(struct scsi_device *SDptr);
424
425
426
427
428typedef struct {
429 uint8_t op_code;
430 uint8_t command_id;
431 uint8_t log_drv;
432 uint8_t sg_count;
433 uint32_t lba;
434 uint32_t sg_addr;
435 uint16_t sector_count;
436 uint8_t segment_4G;
437 uint8_t enhanced_sg;
438 uint32_t ccsar;
439 uint32_t cccr;
440} IPS_IO_CMD, *PIPS_IO_CMD;
441
442typedef struct {
443 uint8_t op_code;
444 uint8_t command_id;
445 uint16_t reserved;
446 uint32_t reserved2;
447 uint32_t buffer_addr;
448 uint32_t reserved3;
449 uint32_t ccsar;
450 uint32_t cccr;
451} IPS_LD_CMD, *PIPS_LD_CMD;
452
453typedef struct {
454 uint8_t op_code;
455 uint8_t command_id;
456 uint8_t reserved;
457 uint8_t reserved2;
458 uint32_t reserved3;
459 uint32_t buffer_addr;
460 uint32_t reserved4;
461} IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
462
463typedef struct {
464 uint8_t op_code;
465 uint8_t command_id;
466 uint8_t channel;
467 uint8_t reserved3;
468 uint8_t reserved4;
469 uint8_t reserved5;
470 uint8_t reserved6;
471 uint8_t reserved7;
472 uint8_t reserved8;
473 uint8_t reserved9;
474 uint8_t reserved10;
475 uint8_t reserved11;
476 uint8_t reserved12;
477 uint8_t reserved13;
478 uint8_t reserved14;
479 uint8_t adapter_flag;
480} IPS_RESET_CMD, *PIPS_RESET_CMD;
481
482typedef struct {
483 uint8_t op_code;
484 uint8_t command_id;
485 uint16_t reserved;
486 uint32_t reserved2;
487 uint32_t dcdb_address;
488 uint16_t reserved3;
489 uint8_t segment_4G;
490 uint8_t enhanced_sg;
491 uint32_t ccsar;
492 uint32_t cccr;
493} IPS_DCDB_CMD, *PIPS_DCDB_CMD;
494
495typedef struct {
496 uint8_t op_code;
497 uint8_t command_id;
498 uint8_t channel;
499 uint8_t source_target;
500 uint32_t reserved;
501 uint32_t reserved2;
502 uint32_t reserved3;
503 uint32_t ccsar;
504 uint32_t cccr;
505} IPS_CS_CMD, *PIPS_CS_CMD;
506
507typedef struct {
508 uint8_t op_code;
509 uint8_t command_id;
510 uint8_t log_drv;
511 uint8_t control;
512 uint32_t reserved;
513 uint32_t reserved2;
514 uint32_t reserved3;
515 uint32_t ccsar;
516 uint32_t cccr;
517} IPS_US_CMD, *PIPS_US_CMD;
518
519typedef struct {
520 uint8_t op_code;
521 uint8_t command_id;
522 uint8_t reserved;
523 uint8_t state;
524 uint32_t reserved2;
525 uint32_t reserved3;
526 uint32_t reserved4;
527 uint32_t ccsar;
528 uint32_t cccr;
529} IPS_FC_CMD, *PIPS_FC_CMD;
530
531typedef struct {
532 uint8_t op_code;
533 uint8_t command_id;
534 uint8_t reserved;
535 uint8_t desc;
536 uint32_t reserved2;
537 uint32_t buffer_addr;
538 uint32_t reserved3;
539 uint32_t ccsar;
540 uint32_t cccr;
541} IPS_STATUS_CMD, *PIPS_STATUS_CMD;
542
543typedef struct {
544 uint8_t op_code;
545 uint8_t command_id;
546 uint8_t page;
547 uint8_t write;
548 uint32_t reserved;
549 uint32_t buffer_addr;
550 uint32_t reserved2;
551 uint32_t ccsar;
552 uint32_t cccr;
553} IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
554
555typedef struct
556{
557 uint8_t op_code;
558 uint8_t command_id;
559 uint16_t reserved;
560 uint32_t count;
561 uint32_t buffer_addr;
562 uint32_t reserved2;
563} IPS_VERSION_INFO, *PIPS_VERSION_INFO;
564
565typedef struct {
566 uint8_t op_code;
567 uint8_t command_id;
568 uint8_t reset_count;
569 uint8_t reset_type;
570 uint8_t second;
571 uint8_t minute;
572 uint8_t hour;
573 uint8_t day;
574 uint8_t reserved1[4];
575 uint8_t month;
576 uint8_t yearH;
577 uint8_t yearL;
578 uint8_t reserved2;
579} IPS_FFDC_CMD, *PIPS_FFDC_CMD;
580
581typedef struct {
582 uint8_t op_code;
583 uint8_t command_id;
584 uint8_t type;
585 uint8_t direction;
586 uint32_t count;
587 uint32_t buffer_addr;
588 uint8_t total_packets;
589 uint8_t packet_num;
590 uint16_t reserved;
591} IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
592
593typedef struct {
594 uint8_t op_code;
595 uint8_t command_id;
596 uint8_t type;
597 uint8_t direction;
598 uint32_t count;
599 uint32_t buffer_addr;
600 uint32_t offset;
601} IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
602
603typedef union {
604 IPS_IO_CMD basic_io;
605 IPS_LD_CMD logical_info;
606 IPS_IOCTL_CMD ioctl_info;
607 IPS_DCDB_CMD dcdb;
608 IPS_CS_CMD config_sync;
609 IPS_US_CMD unlock_stripe;
610 IPS_FC_CMD flush_cache;
611 IPS_STATUS_CMD status;
612 IPS_NVRAM_CMD nvram;
613 IPS_FFDC_CMD ffdc;
614 IPS_FLASHFW_CMD flashfw;
615 IPS_FLASHBIOS_CMD flashbios;
616 IPS_VERSION_INFO version_info;
617 IPS_RESET_CMD reset;
618} IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
619
620typedef struct {
621 uint8_t logical_id;
622 uint8_t reserved;
623 uint8_t raid_level;
624 uint8_t state;
625 uint32_t sector_count;
626} IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
627
628typedef struct {
629 uint8_t no_of_log_drive;
630 uint8_t reserved[3];
631 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
632} IPS_LD_INFO, *PIPS_LD_INFO;
633
634typedef struct {
635 uint8_t device_address;
636 uint8_t cmd_attribute;
637 uint16_t transfer_length;
638 uint32_t buffer_pointer;
639 uint8_t cdb_length;
640 uint8_t sense_length;
641 uint8_t sg_count;
642 uint8_t reserved;
643 uint8_t scsi_cdb[12];
644 uint8_t sense_info[64];
645 uint8_t scsi_status;
646 uint8_t reserved2[3];
647} IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
648
649typedef struct {
650 uint8_t device_address;
651 uint8_t cmd_attribute;
652 uint8_t cdb_length;
653 uint8_t reserved_for_LUN;
654 uint32_t transfer_length;
655 uint32_t buffer_pointer;
656 uint16_t sg_count;
657 uint8_t sense_length;
658 uint8_t scsi_status;
659 uint32_t reserved;
660 uint8_t scsi_cdb[16];
661 uint8_t sense_info[56];
662} IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
663
664typedef union {
665 struct {
666 volatile uint8_t reserved;
667 volatile uint8_t command_id;
668 volatile uint8_t basic_status;
669 volatile uint8_t extended_status;
670 } fields;
671
672 volatile uint32_t value;
673} IPS_STATUS, *PIPS_STATUS;
674
675typedef struct {
676 IPS_STATUS status[IPS_MAX_CMDS + 1];
677 volatile PIPS_STATUS p_status_start;
678 volatile PIPS_STATUS p_status_end;
679 volatile PIPS_STATUS p_status_tail;
680 volatile uint32_t hw_status_start;
681 volatile uint32_t hw_status_tail;
682} IPS_ADAPTER, *PIPS_ADAPTER;
683
684typedef struct {
685 uint8_t ucLogDriveCount;
686 uint8_t ucMiscFlag;
687 uint8_t ucSLTFlag;
688 uint8_t ucBSTFlag;
689 uint8_t ucPwrChgCnt;
690 uint8_t ucWrongAdrCnt;
691 uint8_t ucUnidentCnt;
692 uint8_t ucNVramDevChgCnt;
693 uint8_t CodeBlkVersion[8];
694 uint8_t BootBlkVersion[8];
695 uint32_t ulDriveSize[IPS_MAX_LD];
696 uint8_t ucConcurrentCmdCount;
697 uint8_t ucMaxPhysicalDevices;
698 uint16_t usFlashRepgmCount;
699 uint8_t ucDefunctDiskCount;
700 uint8_t ucRebuildFlag;
701 uint8_t ucOfflineLogDrvCount;
702 uint8_t ucCriticalDrvCount;
703 uint16_t usConfigUpdateCount;
704 uint8_t ucBlkFlag;
705 uint8_t reserved;
706 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
707} IPS_ENQ, *PIPS_ENQ;
708
709typedef struct {
710 uint8_t ucInitiator;
711 uint8_t ucParameters;
712 uint8_t ucMiscFlag;
713 uint8_t ucState;
714 uint32_t ulBlockCount;
715 uint8_t ucDeviceId[28];
716} IPS_DEVSTATE, *PIPS_DEVSTATE;
717
718typedef struct {
719 uint8_t ucChn;
720 uint8_t ucTgt;
721 uint16_t ucReserved;
722 uint32_t ulStartSect;
723 uint32_t ulNoOfSects;
724} IPS_CHUNK, *PIPS_CHUNK;
725
726typedef struct {
727 uint16_t ucUserField;
728 uint8_t ucState;
729 uint8_t ucRaidCacheParam;
730 uint8_t ucNoOfChunkUnits;
731 uint8_t ucStripeSize;
732 uint8_t ucParams;
733 uint8_t ucReserved;
734 uint32_t ulLogDrvSize;
735 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
736} IPS_LD, *PIPS_LD;
737
738typedef struct {
739 uint8_t board_disc[8];
740 uint8_t processor[8];
741 uint8_t ucNoChanType;
742 uint8_t ucNoHostIntType;
743 uint8_t ucCompression;
744 uint8_t ucNvramType;
745 uint32_t ulNvramSize;
746} IPS_HARDWARE, *PIPS_HARDWARE;
747
748typedef struct {
749 uint8_t ucLogDriveCount;
750 uint8_t ucDateD;
751 uint8_t ucDateM;
752 uint8_t ucDateY;
753 uint8_t init_id[4];
754 uint8_t host_id[12];
755 uint8_t time_sign[8];
756 uint32_t UserOpt;
757 uint16_t user_field;
758 uint8_t ucRebuildRate;
759 uint8_t ucReserve;
760 IPS_HARDWARE hardware_disc;
761 IPS_LD logical_drive[IPS_MAX_LD];
762 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
763 uint8_t reserved[512];
764} IPS_CONF, *PIPS_CONF;
765
766typedef struct {
767 uint32_t signature;
768 uint8_t reserved1;
769 uint8_t adapter_slot;
770 uint16_t adapter_type;
771 uint8_t ctrl_bios[8];
772 uint8_t versioning;
773 uint8_t version_mismatch;
774 uint8_t reserved2;
775 uint8_t operating_system;
776 uint8_t driver_high[4];
777 uint8_t driver_low[4];
778 uint8_t BiosCompatibilityID[8];
779 uint8_t ReservedForOS2[8];
780 uint8_t bios_high[4];
781 uint8_t bios_low[4];
782 uint8_t adapter_order[16];
783 uint8_t Filler[60];
784} IPS_NVRAM_P5, *PIPS_NVRAM_P5;
785
786
787
788
789
790
791#define IPS_GET_VERSION_SUPPORT 0x00018000
792
793typedef struct
794{
795 uint32_t revision;
796 uint8_t bootBlkVersion[32];
797 uint8_t bootBlkAttributes[4];
798 uint8_t codeBlkVersion[32];
799 uint8_t biosVersion[32];
800 uint8_t biosAttributes[4];
801 uint8_t compatibilityId[32];
802 uint8_t reserved[4];
803} IPS_VERSION_DATA;
804
805
806typedef struct _IPS_SUBSYS {
807 uint32_t param[128];
808} IPS_SUBSYS, *PIPS_SUBSYS;
809
810
811
812
813
814
815
816
817typedef struct {
818 uint8_t DeviceType;
819 uint8_t DeviceTypeQualifier;
820 uint8_t Version;
821 uint8_t ResponseDataFormat;
822 uint8_t AdditionalLength;
823 uint8_t Reserved;
824 uint8_t Flags[2];
825 uint8_t VendorId[8];
826 uint8_t ProductId[16];
827 uint8_t ProductRevisionLevel[4];
828 uint8_t Reserved2;
829} IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
830
831
832
833
834typedef struct {
835 uint32_t lba;
836 uint32_t len;
837} IPS_SCSI_CAPACITY;
838
839
840
841
842typedef struct {
843 uint8_t ResponseCode;
844 uint8_t SegmentNumber;
845 uint8_t Flags;
846 uint8_t Information[4];
847 uint8_t AdditionalLength;
848 uint8_t CommandSpecific[4];
849 uint8_t AdditionalSenseCode;
850 uint8_t AdditionalSenseCodeQual;
851 uint8_t FRUCode;
852 uint8_t SenseKeySpecific[3];
853} IPS_SCSI_REQSEN;
854
855
856
857
858typedef struct {
859 uint8_t PageCode;
860 uint8_t PageLength;
861 uint16_t TracksPerZone;
862 uint16_t AltSectorsPerZone;
863 uint16_t AltTracksPerZone;
864 uint16_t AltTracksPerVolume;
865 uint16_t SectorsPerTrack;
866 uint16_t BytesPerSector;
867 uint16_t Interleave;
868 uint16_t TrackSkew;
869 uint16_t CylinderSkew;
870 uint8_t flags;
871 uint8_t reserved[3];
872} IPS_SCSI_MODE_PAGE3;
873
874
875
876
877typedef struct {
878 uint8_t PageCode;
879 uint8_t PageLength;
880 uint16_t CylindersHigh;
881 uint8_t CylindersLow;
882 uint8_t Heads;
883 uint16_t WritePrecompHigh;
884 uint8_t WritePrecompLow;
885 uint16_t ReducedWriteCurrentHigh;
886 uint8_t ReducedWriteCurrentLow;
887 uint16_t StepRate;
888 uint16_t LandingZoneHigh;
889 uint8_t LandingZoneLow;
890 uint8_t flags;
891 uint8_t RotationalOffset;
892 uint8_t Reserved;
893 uint16_t MediumRotationRate;
894 uint8_t Reserved2[2];
895} IPS_SCSI_MODE_PAGE4;
896
897
898
899
900typedef struct {
901 uint8_t PageCode;
902 uint8_t PageLength;
903 uint8_t flags;
904 uint8_t RetentPrio;
905 uint16_t DisPrefetchLen;
906 uint16_t MinPrefetchLen;
907 uint16_t MaxPrefetchLen;
908 uint16_t MaxPrefetchCeiling;
909} IPS_SCSI_MODE_PAGE8;
910
911
912
913
914typedef struct {
915 uint32_t NumberOfBlocks;
916 uint8_t DensityCode;
917 uint16_t BlockLengthHigh;
918 uint8_t BlockLengthLow;
919} IPS_SCSI_MODE_PAGE_BLKDESC;
920
921
922
923
924typedef struct {
925 uint8_t DataLength;
926 uint8_t MediumType;
927 uint8_t Reserved;
928 uint8_t BlockDescLength;
929} IPS_SCSI_MODE_PAGE_HEADER;
930
931typedef struct {
932 IPS_SCSI_MODE_PAGE_HEADER hdr;
933 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
934
935 union {
936 IPS_SCSI_MODE_PAGE3 pg3;
937 IPS_SCSI_MODE_PAGE4 pg4;
938 IPS_SCSI_MODE_PAGE8 pg8;
939 } pdata;
940} IPS_SCSI_MODE_PAGE_DATA;
941
942
943
944
945typedef struct ips_sglist {
946 uint32_t address;
947 uint32_t length;
948} IPS_STD_SG_LIST;
949
950typedef struct ips_enh_sglist {
951 uint32_t address_lo;
952 uint32_t address_hi;
953 uint32_t length;
954 uint32_t reserved;
955} IPS_ENH_SG_LIST;
956
957typedef union {
958 void *list;
959 IPS_STD_SG_LIST *std_list;
960 IPS_ENH_SG_LIST *enh_list;
961} IPS_SG_LIST;
962
963typedef struct _IPS_INFOSTR {
964 char *buffer;
965 int length;
966 int offset;
967 int pos;
968 int localpos;
969} IPS_INFOSTR;
970
971typedef struct {
972 char *option_name;
973 int *option_flag;
974 int option_value;
975} IPS_OPTION;
976
977
978
979
980typedef struct ips_stat {
981 uint32_t residue_len;
982 void *scb_addr;
983 uint8_t padding[12 - sizeof(void *)];
984} ips_stat_t;
985
986
987
988
989typedef struct ips_scb_queue {
990 struct ips_scb *head;
991 struct ips_scb *tail;
992 int count;
993} ips_scb_queue_t;
994
995
996
997
998typedef struct ips_wait_queue {
999 struct scsi_cmnd *head;
1000 struct scsi_cmnd *tail;
1001 int count;
1002} ips_wait_queue_t;
1003
1004typedef struct ips_copp_wait_item {
1005 struct scsi_cmnd *scsi_cmd;
1006 struct ips_copp_wait_item *next;
1007} ips_copp_wait_item_t;
1008
1009typedef struct ips_copp_queue {
1010 struct ips_copp_wait_item *head;
1011 struct ips_copp_wait_item *tail;
1012 int count;
1013} ips_copp_queue_t;
1014
1015
1016struct ips_ha;
1017
1018typedef struct {
1019 int (*reset)(struct ips_ha *);
1020 int (*issue)(struct ips_ha *, struct ips_scb *);
1021 int (*isinit)(struct ips_ha *);
1022 int (*isintr)(struct ips_ha *);
1023 int (*init)(struct ips_ha *);
1024 int (*erasebios)(struct ips_ha *);
1025 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1026 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1027 void (*statinit)(struct ips_ha *);
1028 int (*intr)(struct ips_ha *);
1029 void (*enableint)(struct ips_ha *);
1030 uint32_t (*statupd)(struct ips_ha *);
1031} ips_hw_func_t;
1032
1033typedef struct ips_ha {
1034 uint8_t ha_id[IPS_MAX_CHANNELS+1];
1035 uint32_t dcdb_active[IPS_MAX_CHANNELS];
1036 uint32_t io_addr;
1037 uint8_t irq;
1038 uint8_t ntargets;
1039 uint8_t nbus;
1040 uint8_t nlun;
1041 uint16_t ad_type;
1042 uint16_t host_num;
1043 uint32_t max_xfer;
1044 uint32_t max_cmds;
1045 uint32_t num_ioctl;
1046 ips_stat_t sp;
1047 struct ips_scb *scbs;
1048 struct ips_scb *scb_freelist;
1049 ips_wait_queue_t scb_waitlist;
1050 ips_copp_queue_t copp_waitlist;
1051 ips_scb_queue_t scb_activelist;
1052 IPS_IO_CMD *dummy;
1053 IPS_ADAPTER *adapt;
1054 IPS_LD_INFO *logical_drive_info;
1055 dma_addr_t logical_drive_info_dma_addr;
1056 IPS_ENQ *enq;
1057 IPS_CONF *conf;
1058 IPS_NVRAM_P5 *nvram;
1059 IPS_SUBSYS *subsys;
1060 char *ioctl_data;
1061 uint32_t ioctl_datasize;
1062 uint32_t cmd_in_progress;
1063 int flags;
1064 uint8_t waitflag;
1065 uint8_t active;
1066 int ioctl_reset;
1067 uint16_t reset_count;
1068 time_t last_ffdc;
1069 uint8_t revision_id;
1070 uint16_t device_id;
1071 uint8_t slot_num;
1072 uint16_t subdevice_id;
1073 int ioctl_len;
1074 dma_addr_t ioctl_busaddr;
1075 uint8_t bios_version[8];
1076 uint32_t mem_addr;
1077 uint32_t io_len;
1078 uint32_t mem_len;
1079 char __iomem *mem_ptr;
1080 char __iomem *ioremap_ptr;
1081 ips_hw_func_t func;
1082 struct pci_dev *pcidev;
1083 char *flash_data;
1084 int flash_len;
1085 u32 flash_datasize;
1086 dma_addr_t flash_busaddr;
1087 dma_addr_t enq_busaddr;
1088 uint8_t requires_esl;
1089} ips_ha_t;
1090
1091typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1092
1093
1094
1095
1096typedef struct ips_scb {
1097 IPS_HOST_COMMAND cmd;
1098 IPS_DCDB_TABLE dcdb;
1099 uint8_t target_id;
1100 uint8_t bus;
1101 uint8_t lun;
1102 uint8_t cdb[12];
1103 uint32_t scb_busaddr;
1104 uint32_t old_data_busaddr;
1105 uint32_t timeout;
1106 uint8_t basic_status;
1107 uint8_t extended_status;
1108 uint8_t breakup;
1109 uint8_t sg_break;
1110 uint32_t data_len;
1111 uint32_t sg_len;
1112 uint32_t flags;
1113 uint32_t op_code;
1114 IPS_SG_LIST sg_list;
1115 struct scsi_cmnd *scsi_cmd;
1116 struct ips_scb *q_next;
1117 ips_scb_callback callback;
1118 uint32_t sg_busaddr;
1119 int sg_count;
1120 dma_addr_t data_busaddr;
1121} ips_scb_t;
1122
1123typedef struct ips_scb_pt {
1124 IPS_HOST_COMMAND cmd;
1125 IPS_DCDB_TABLE dcdb;
1126 uint8_t target_id;
1127 uint8_t bus;
1128 uint8_t lun;
1129 uint8_t cdb[12];
1130 uint32_t scb_busaddr;
1131 uint32_t data_busaddr;
1132 uint32_t timeout;
1133 uint8_t basic_status;
1134 uint8_t extended_status;
1135 uint16_t breakup;
1136 uint32_t data_len;
1137 uint32_t sg_len;
1138 uint32_t flags;
1139 uint32_t op_code;
1140 IPS_SG_LIST *sg_list;
1141 struct scsi_cmnd *scsi_cmd;
1142 struct ips_scb *q_next;
1143 ips_scb_callback callback;
1144} ips_scb_pt_t;
1145
1146
1147
1148
1149typedef struct {
1150 uint8_t CoppID[4];
1151 uint32_t CoppCmd;
1152 uint32_t PtBuffer;
1153 uint8_t *CmdBuffer;
1154 uint32_t CmdBSize;
1155 ips_scb_pt_t CoppCP;
1156 uint32_t TimeOut;
1157 uint8_t BasicStatus;
1158 uint8_t ExtendedStatus;
1159 uint8_t AdapterType;
1160 uint8_t reserved;
1161} ips_passthru_t;
1162
1163#endif
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174#define IPS_VER_MAJOR 7
1175#define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1176#define IPS_VER_MINOR 12
1177#define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1178#define IPS_VER_BUILD 05
1179#define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1180#define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1181 IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1182#define IPS_RELEASE_ID 0x00020000
1183#define IPS_BUILD_IDENT 761
1184#define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1185#define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1186#define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1187#define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1188
1189
1190#define IPS_VER_SERVERAID1 "2.25.01"
1191#define IPS_VER_SERVERAID2 "2.88.13"
1192#define IPS_VER_NAVAJO "2.88.13"
1193#define IPS_VER_SERVERAID3 "6.10.24"
1194#define IPS_VER_SERVERAID4H "7.12.02"
1195#define IPS_VER_SERVERAID4MLx "7.12.02"
1196#define IPS_VER_SARASOTA "7.12.02"
1197#define IPS_VER_MARCO "7.12.02"
1198#define IPS_VER_SEBRING "7.12.02"
1199#define IPS_VER_KEYWEST "7.12.02"
1200
1201
1202#define IPS_COMPAT_UNKNOWN ""
1203#define IPS_COMPAT_CURRENT "KW710"
1204#define IPS_COMPAT_SERVERAID1 "2.25.01"
1205#define IPS_COMPAT_SERVERAID2 "2.88.13"
1206#define IPS_COMPAT_NAVAJO "2.88.13"
1207#define IPS_COMPAT_KIOWA "2.88.13"
1208#define IPS_COMPAT_SERVERAID3H "SB610"
1209#define IPS_COMPAT_SERVERAID3L "SB610"
1210#define IPS_COMPAT_SERVERAID4H "KW710"
1211#define IPS_COMPAT_SERVERAID4M "KW710"
1212#define IPS_COMPAT_SERVERAID4L "KW710"
1213#define IPS_COMPAT_SERVERAID4Mx "KW710"
1214#define IPS_COMPAT_SERVERAID4Lx "KW710"
1215#define IPS_COMPAT_SARASOTA "KW710"
1216#define IPS_COMPAT_MARCO "KW710"
1217#define IPS_COMPAT_SEBRING "KW710"
1218#define IPS_COMPAT_TAMPA "KW710"
1219#define IPS_COMPAT_KEYWEST "KW710"
1220#define IPS_COMPAT_BIOS "KW710"
1221
1222#define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1223#define IPS_COMPAT_ID_LENGTH 8
1224
1225#define IPS_DEFINE_COMPAT_TABLE(tablename) \
1226 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1227 IPS_COMPAT_UNKNOWN, \
1228 IPS_COMPAT_SERVERAID1, \
1229 IPS_COMPAT_SERVERAID2, \
1230 IPS_COMPAT_NAVAJO, \
1231 IPS_COMPAT_KIOWA, \
1232 IPS_COMPAT_SERVERAID3H, \
1233 IPS_COMPAT_SERVERAID3L, \
1234 IPS_COMPAT_SERVERAID4H, \
1235 IPS_COMPAT_SERVERAID4M, \
1236 IPS_COMPAT_SERVERAID4L, \
1237 IPS_COMPAT_SERVERAID4Mx, \
1238 IPS_COMPAT_SERVERAID4Lx, \
1239 IPS_COMPAT_SARASOTA, \
1240 IPS_COMPAT_SARASOTA, \
1241 IPS_COMPAT_MARCO, \
1242 IPS_COMPAT_SEBRING, \
1243 IPS_COMPAT_TAMPA, \
1244 IPS_COMPAT_KEYWEST \
1245 }
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
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