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30#include <linux/module.h>
31#include <linux/tty.h>
32#include <linux/ioport.h>
33#include <linux/init.h>
34#include <linux/serial.h>
35#include <linux/console.h>
36#include <linux/sysrq.h>
37#include <linux/device.h>
38#include <linux/bootmem.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/fs_pd.h>
44
45#include <linux/serial_core.h>
46#include <linux/kernel.h>
47
48#include "cpm_uart.h"
49
50
51
52#ifdef CONFIG_PPC_CPM_NEW_BINDING
53void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
54{
55 cpm_cpm2_t __iomem *cp = cpm2_map(im_cpm);
56
57 out_be32(&cp->cp_cpcr, port->command | cmd | CPM_CR_FLG);
58 while (in_be32(&cp->cp_cpcr) & CPM_CR_FLG)
59 ;
60
61 cpm2_unmap(cp);
62}
63#else
64void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
65{
66 ulong val;
67 int line = port - cpm_uart_ports;
68 volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
69
70
71 switch (line) {
72 case UART_SMC1:
73 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
74 cmd) | CPM_CR_FLG;
75 break;
76 case UART_SMC2:
77 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
78 cmd) | CPM_CR_FLG;
79 break;
80 case UART_SCC1:
81 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
82 cmd) | CPM_CR_FLG;
83 break;
84 case UART_SCC2:
85 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
86 cmd) | CPM_CR_FLG;
87 break;
88 case UART_SCC3:
89 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
90 cmd) | CPM_CR_FLG;
91 break;
92 case UART_SCC4:
93 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
94 cmd) | CPM_CR_FLG;
95 break;
96 default:
97 return;
98
99 }
100 cp->cp_cpcr = val;
101 while (cp->cp_cpcr & CPM_CR_FLG) ;
102
103 cpm2_unmap(cp);
104}
105
106void smc1_lineif(struct uart_cpm_port *pinfo)
107{
108 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
109 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
110
111
112 io->iop_ppard |= 0x00c00000;
113 io->iop_pdird |= 0x00400000;
114 io->iop_pdird &= ~0x00800000;
115 io->iop_psord &= ~0x00c00000;
116
117
118 cpmux->cmx_smr &= 0x0f;
119 pinfo->brg = 1;
120
121 cpm2_unmap(cpmux);
122 cpm2_unmap(io);
123}
124
125void smc2_lineif(struct uart_cpm_port *pinfo)
126{
127 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
128 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
129
130
131 io->iop_ppara |= 0x00c00000;
132 io->iop_pdira |= 0x00400000;
133 io->iop_pdira &= ~0x00800000;
134 io->iop_psora &= ~0x00c00000;
135
136
137 cpmux->cmx_smr &= 0xf0;
138 pinfo->brg = 2;
139
140 cpm2_unmap(cpmux);
141 cpm2_unmap(io);
142}
143
144void scc1_lineif(struct uart_cpm_port *pinfo)
145{
146 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
147 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
148
149
150 io->iop_ppard |= 0x00000003;
151 io->iop_psord &= ~0x00000001;
152 io->iop_psord |= 0x00000002;
153 io->iop_pdird &= ~0x00000001;
154 io->iop_pdird |= 0x00000002;
155
156
157 cpmux->cmx_scr &= 0x00ffffff;
158 cpmux->cmx_scr |= 0x00000000;
159 pinfo->brg = 1;
160
161 cpm2_unmap(cpmux);
162 cpm2_unmap(io);
163}
164
165void scc2_lineif(struct uart_cpm_port *pinfo)
166{
167
168
169
170
171
172
173
174#ifndef CONFIG_STX_GP3
175 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
176 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
177
178 io->iop_pparb |= 0x008b0000;
179 io->iop_pdirb |= 0x00880000;
180 io->iop_psorb |= 0x00880000;
181 io->iop_pdirb &= ~0x00030000;
182 io->iop_psorb &= ~0x00030000;
183#endif
184 cpmux->cmx_scr &= 0xff00ffff;
185 cpmux->cmx_scr |= 0x00090000;
186 pinfo->brg = 2;
187
188 cpm2_unmap(cpmux);
189 cpm2_unmap(io);
190}
191
192void scc3_lineif(struct uart_cpm_port *pinfo)
193{
194 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
195 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
196
197 io->iop_pparb |= 0x008b0000;
198 io->iop_pdirb |= 0x00880000;
199 io->iop_psorb |= 0x00880000;
200 io->iop_pdirb &= ~0x00030000;
201 io->iop_psorb &= ~0x00030000;
202 cpmux->cmx_scr &= 0xffff00ff;
203 cpmux->cmx_scr |= 0x00001200;
204 pinfo->brg = 3;
205
206 cpm2_unmap(cpmux);
207 cpm2_unmap(io);
208}
209
210void scc4_lineif(struct uart_cpm_port *pinfo)
211{
212 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
213 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
214
215 io->iop_ppard |= 0x00000600;
216 io->iop_psord &= ~0x00000600;
217 io->iop_pdird &= ~0x00000200;
218 io->iop_pdird |= 0x00000400;
219
220 cpmux->cmx_scr &= 0xffffff00;
221 cpmux->cmx_scr |= 0x0000001b;
222 pinfo->brg = 4;
223
224 cpm2_unmap(cpmux);
225 cpm2_unmap(io);
226}
227#endif
228
229
230
231
232
233
234
235int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
236{
237 int dpmemsz, memsz;
238 u8 __iomem *dp_mem;
239 unsigned long dp_offset;
240 u8 *mem_addr;
241 dma_addr_t dma_addr = 0;
242
243 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
244
245 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
246 dp_offset = cpm_dpalloc(dpmemsz, 8);
247 if (IS_ERR_VALUE(dp_offset)) {
248 printk(KERN_ERR
249 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
250 return -ENOMEM;
251 }
252
253 dp_mem = cpm_dpram_addr(dp_offset);
254
255 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
256 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
257 if (is_con) {
258 mem_addr = alloc_bootmem(memsz);
259 dma_addr = virt_to_bus(mem_addr);
260 }
261 else
262 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
263 GFP_KERNEL);
264
265 if (mem_addr == NULL) {
266 cpm_dpfree(dp_offset);
267 printk(KERN_ERR
268 "cpm_uart_cpm.c: could not allocate coherent memory\n");
269 return -ENOMEM;
270 }
271
272 pinfo->dp_addr = dp_offset;
273 pinfo->mem_addr = mem_addr;
274 pinfo->dma_addr = dma_addr;
275 pinfo->mem_size = memsz;
276
277 pinfo->rx_buf = mem_addr;
278 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
279 * pinfo->rx_fifosize);
280
281 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem;
282 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
283
284 return 0;
285}
286
287void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
288{
289 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
290 pinfo->rx_fifosize) +
291 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
292 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
293 pinfo->dma_addr);
294
295 cpm_dpfree(pinfo->dp_addr);
296}
297
298#ifndef CONFIG_PPC_CPM_NEW_BINDING
299
300int cpm_uart_init_portdesc(void)
301{
302#if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
303 u16 *addr;
304#endif
305 pr_debug("CPM uart[-]:init portdesc\n");
306
307 cpm_uart_nr = 0;
308#ifdef CONFIG_SERIAL_CPM_SMC1
309 cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
310 cpm_uart_ports[UART_SMC1].port.mapbase =
311 (unsigned long)cpm_uart_ports[UART_SMC1].smcp;
312
313 cpm_uart_ports[UART_SMC1].smcup =
314 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
315 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
316 *addr = PROFF_SMC1;
317 cpm2_unmap(addr);
318
319 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
320 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
321 cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
322 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
323#endif
324
325#ifdef CONFIG_SERIAL_CPM_SMC2
326 cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
327 cpm_uart_ports[UART_SMC2].port.mapbase =
328 (unsigned long)cpm_uart_ports[UART_SMC2].smcp;
329
330 cpm_uart_ports[UART_SMC2].smcup =
331 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
332 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
333 *addr = PROFF_SMC2;
334 cpm2_unmap(addr);
335
336 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
337 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
338 cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
339 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
340#endif
341
342#ifdef CONFIG_SERIAL_CPM_SCC1
343 cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
344 cpm_uart_ports[UART_SCC1].port.mapbase =
345 (unsigned long)cpm_uart_ports[UART_SCC1].sccp;
346 cpm_uart_ports[UART_SCC1].sccup =
347 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
348
349 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
350 ~(UART_SCCM_TX | UART_SCCM_RX);
351 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
352 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
353 cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
354 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
355#endif
356
357#ifdef CONFIG_SERIAL_CPM_SCC2
358 cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
359 cpm_uart_ports[UART_SCC2].port.mapbase =
360 (unsigned long)cpm_uart_ports[UART_SCC2].sccp;
361 cpm_uart_ports[UART_SCC2].sccup =
362 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
363
364 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
365 ~(UART_SCCM_TX | UART_SCCM_RX);
366 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
367 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
368 cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
369 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
370#endif
371
372#ifdef CONFIG_SERIAL_CPM_SCC3
373 cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
374 cpm_uart_ports[UART_SCC3].port.mapbase =
375 (unsigned long)cpm_uart_ports[UART_SCC3].sccp;
376 cpm_uart_ports[UART_SCC3].sccup =
377 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
378
379 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
380 ~(UART_SCCM_TX | UART_SCCM_RX);
381 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
382 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
383 cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
384 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
385#endif
386
387#ifdef CONFIG_SERIAL_CPM_SCC4
388 cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
389 cpm_uart_ports[UART_SCC4].port.mapbase =
390 (unsigned long)cpm_uart_ports[UART_SCC4].sccp;
391 cpm_uart_ports[UART_SCC4].sccup =
392 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
393
394 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
395 ~(UART_SCCM_TX | UART_SCCM_RX);
396 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
397 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
398 cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
399 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
400#endif
401
402 return 0;
403}
404#endif
405
