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20#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/pci.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33
34#include <asm/io.h>
35
36static char *serial_version = "1.11";
37static char *serial_name = "TX39/49 Serial driver";
38
39#define PASS_LIMIT 256
40
41#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
42
43#define TXX9_TTY_NAME "ttyTX"
44#define TXX9_TTY_MINOR_START 196
45#define TXX9_TTY_MAJOR 204
46#else
47
48#define TXX9_TTY_NAME "ttyS"
49#define TXX9_TTY_MINOR_START 64
50#define TXX9_TTY_MAJOR TTY_MAJOR
51#endif
52
53
54#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
55#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
56
57#ifdef CONFIG_PCI
58
59#define ENABLE_SERIAL_TXX9_PCI
60#endif
61
62
63
64
65#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
66
67struct uart_txx9_port {
68 struct uart_port port;
69
70};
71
72#define TXX9_REGION_SIZE 0x24
73
74
75#define TXX9_SILCR 0x00
76#define TXX9_SIDICR 0x04
77#define TXX9_SIDISR 0x08
78#define TXX9_SICISR 0x0c
79#define TXX9_SIFCR 0x10
80#define TXX9_SIFLCR 0x14
81#define TXX9_SIBGR 0x18
82#define TXX9_SITFIFO 0x1c
83#define TXX9_SIRFIFO 0x20
84
85
86#define TXX9_SILCR_SCS_MASK 0x00000060
87#define TXX9_SILCR_SCS_IMCLK 0x00000000
88#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
89#define TXX9_SILCR_SCS_SCLK 0x00000040
90#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
91#define TXX9_SILCR_UEPS 0x00000010
92#define TXX9_SILCR_UPEN 0x00000008
93#define TXX9_SILCR_USBL_MASK 0x00000004
94#define TXX9_SILCR_USBL_1BIT 0x00000000
95#define TXX9_SILCR_USBL_2BIT 0x00000004
96#define TXX9_SILCR_UMODE_MASK 0x00000003
97#define TXX9_SILCR_UMODE_8BIT 0x00000000
98#define TXX9_SILCR_UMODE_7BIT 0x00000001
99
100
101#define TXX9_SIDICR_TDE 0x00008000
102#define TXX9_SIDICR_RDE 0x00004000
103#define TXX9_SIDICR_TIE 0x00002000
104#define TXX9_SIDICR_RIE 0x00001000
105#define TXX9_SIDICR_SPIE 0x00000800
106#define TXX9_SIDICR_CTSAC 0x00000600
107#define TXX9_SIDICR_STIE_MASK 0x0000003f
108#define TXX9_SIDICR_STIE_OERS 0x00000020
109#define TXX9_SIDICR_STIE_CTSS 0x00000010
110#define TXX9_SIDICR_STIE_RBRKD 0x00000008
111#define TXX9_SIDICR_STIE_TRDY 0x00000004
112#define TXX9_SIDICR_STIE_TXALS 0x00000002
113#define TXX9_SIDICR_STIE_UBRKD 0x00000001
114
115
116#define TXX9_SIDISR_UBRK 0x00008000
117#define TXX9_SIDISR_UVALID 0x00004000
118#define TXX9_SIDISR_UFER 0x00002000
119#define TXX9_SIDISR_UPER 0x00001000
120#define TXX9_SIDISR_UOER 0x00000800
121#define TXX9_SIDISR_ERI 0x00000400
122#define TXX9_SIDISR_TOUT 0x00000200
123#define TXX9_SIDISR_TDIS 0x00000100
124#define TXX9_SIDISR_RDIS 0x00000080
125#define TXX9_SIDISR_STIS 0x00000040
126#define TXX9_SIDISR_RFDN_MASK 0x0000001f
127
128
129#define TXX9_SICISR_OERS 0x00000020
130#define TXX9_SICISR_CTSS 0x00000010
131#define TXX9_SICISR_RBRKD 0x00000008
132#define TXX9_SICISR_TRDY 0x00000004
133#define TXX9_SICISR_TXALS 0x00000002
134#define TXX9_SICISR_UBRKD 0x00000001
135
136
137#define TXX9_SIFCR_SWRST 0x00008000
138#define TXX9_SIFCR_RDIL_MASK 0x00000180
139#define TXX9_SIFCR_RDIL_1 0x00000000
140#define TXX9_SIFCR_RDIL_4 0x00000080
141#define TXX9_SIFCR_RDIL_8 0x00000100
142#define TXX9_SIFCR_RDIL_12 0x00000180
143#define TXX9_SIFCR_RDIL_MAX 0x00000180
144#define TXX9_SIFCR_TDIL_MASK 0x00000018
145#define TXX9_SIFCR_TDIL_MASK 0x00000018
146#define TXX9_SIFCR_TDIL_1 0x00000000
147#define TXX9_SIFCR_TDIL_4 0x00000001
148#define TXX9_SIFCR_TDIL_8 0x00000010
149#define TXX9_SIFCR_TDIL_MAX 0x00000010
150#define TXX9_SIFCR_TFRST 0x00000004
151#define TXX9_SIFCR_RFRST 0x00000002
152#define TXX9_SIFCR_FRSTE 0x00000001
153#define TXX9_SIO_TX_FIFO 8
154#define TXX9_SIO_RX_FIFO 16
155
156
157#define TXX9_SIFLCR_RCS 0x00001000
158#define TXX9_SIFLCR_TES 0x00000800
159#define TXX9_SIFLCR_RTSSC 0x00000200
160#define TXX9_SIFLCR_RSDE 0x00000100
161#define TXX9_SIFLCR_TSDE 0x00000080
162#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
163#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
164#define TXX9_SIFLCR_TBRK 0x00000001
165
166
167#define TXX9_SIBGR_BCLK_MASK 0x00000300
168#define TXX9_SIBGR_BCLK_T0 0x00000000
169#define TXX9_SIBGR_BCLK_T2 0x00000100
170#define TXX9_SIBGR_BCLK_T4 0x00000200
171#define TXX9_SIBGR_BCLK_T6 0x00000300
172#define TXX9_SIBGR_BRD_MASK 0x000000ff
173
174static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
175{
176 switch (up->port.iotype) {
177 default:
178 return __raw_readl(up->port.membase + offset);
179 case UPIO_PORT:
180 return inl(up->port.iobase + offset);
181 }
182}
183
184static inline void
185sio_out(struct uart_txx9_port *up, int offset, int value)
186{
187 switch (up->port.iotype) {
188 default:
189 __raw_writel(value, up->port.membase + offset);
190 break;
191 case UPIO_PORT:
192 outl(value, up->port.iobase + offset);
193 break;
194 }
195}
196
197static inline void
198sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
199{
200 sio_out(up, offset, sio_in(up, offset) & ~value);
201}
202static inline void
203sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
204{
205 sio_out(up, offset, sio_in(up, offset) | value);
206}
207
208static inline void
209sio_quot_set(struct uart_txx9_port *up, int quot)
210{
211 quot >>= 1;
212 if (quot < 256)
213 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
214 else if (quot < (256 << 2))
215 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
216 else if (quot < (256 << 4))
217 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
218 else if (quot < (256 << 6))
219 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
220 else
221 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
222}
223
224static void serial_txx9_stop_tx(struct uart_port *port)
225{
226 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
227 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
228}
229
230static void serial_txx9_start_tx(struct uart_port *port)
231{
232 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
233 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
234}
235
236static void serial_txx9_stop_rx(struct uart_port *port)
237{
238 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
239 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
240}
241
242static void serial_txx9_enable_ms(struct uart_port *port)
243{
244
245}
246
247static void serial_txx9_initialize(struct uart_port *port)
248{
249 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
250 unsigned int tmout = 10000;
251
252 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
253
254
255 mmiowb();
256 udelay(1);
257 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
258 udelay(1);
259
260 sio_set(up, TXX9_SIFCR,
261 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
262
263 sio_out(up, TXX9_SILCR,
264 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
265 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
266 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
267 sio_quot_set(up, uart_get_divisor(port, 9600));
268 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX );
269 sio_out(up, TXX9_SIDICR, 0);
270}
271
272static inline void
273receive_chars(struct uart_txx9_port *up, unsigned int *status)
274{
275 struct tty_struct *tty = up->port.info->tty;
276 unsigned char ch;
277 unsigned int disr = *status;
278 int max_count = 256;
279 char flag;
280 unsigned int next_ignore_status_mask;
281
282 do {
283 ch = sio_in(up, TXX9_SIRFIFO);
284 flag = TTY_NORMAL;
285 up->port.icount.rx++;
286
287
288 next_ignore_status_mask =
289 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
290 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
291 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
292
293
294
295 if (disr & TXX9_SIDISR_UBRK) {
296 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
297 up->port.icount.brk++;
298
299
300
301
302
303
304 if (uart_handle_break(&up->port))
305 goto ignore_char;
306 } else if (disr & TXX9_SIDISR_UPER)
307 up->port.icount.parity++;
308 else if (disr & TXX9_SIDISR_UFER)
309 up->port.icount.frame++;
310 if (disr & TXX9_SIDISR_UOER) {
311 up->port.icount.overrun++;
312
313
314
315
316
317
318 next_ignore_status_mask |=
319 TXX9_SIDISR_RFDN_MASK;
320 }
321
322
323
324
325 disr &= up->port.read_status_mask;
326
327 if (disr & TXX9_SIDISR_UBRK) {
328 flag = TTY_BREAK;
329 } else if (disr & TXX9_SIDISR_UPER)
330 flag = TTY_PARITY;
331 else if (disr & TXX9_SIDISR_UFER)
332 flag = TTY_FRAME;
333 }
334 if (uart_handle_sysrq_char(&up->port, ch))
335 goto ignore_char;
336
337 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
338
339 ignore_char:
340 up->port.ignore_status_mask = next_ignore_status_mask;
341 disr = sio_in(up, TXX9_SIDISR);
342 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
343 spin_unlock(&up->port.lock);
344 tty_flip_buffer_push(tty);
345 spin_lock(&up->port.lock);
346 *status = disr;
347}
348
349static inline void transmit_chars(struct uart_txx9_port *up)
350{
351 struct circ_buf *xmit = &up->port.info->xmit;
352 int count;
353
354 if (up->port.x_char) {
355 sio_out(up, TXX9_SITFIFO, up->port.x_char);
356 up->port.icount.tx++;
357 up->port.x_char = 0;
358 return;
359 }
360 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
361 serial_txx9_stop_tx(&up->port);
362 return;
363 }
364
365 count = TXX9_SIO_TX_FIFO;
366 do {
367 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
369 up->port.icount.tx++;
370 if (uart_circ_empty(xmit))
371 break;
372 } while (--count > 0);
373
374 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
375 uart_write_wakeup(&up->port);
376
377 if (uart_circ_empty(xmit))
378 serial_txx9_stop_tx(&up->port);
379}
380
381static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
382{
383 int pass_counter = 0;
384 struct uart_txx9_port *up = dev_id;
385 unsigned int status;
386
387 while (1) {
388 spin_lock(&up->port.lock);
389 status = sio_in(up, TXX9_SIDISR);
390 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
391 status &= ~TXX9_SIDISR_TDIS;
392 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
393 TXX9_SIDISR_TOUT))) {
394 spin_unlock(&up->port.lock);
395 break;
396 }
397
398 if (status & TXX9_SIDISR_RDIS)
399 receive_chars(up, &status);
400 if (status & TXX9_SIDISR_TDIS)
401 transmit_chars(up);
402
403 sio_mask(up, TXX9_SIDISR,
404 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
405 TXX9_SIDISR_TOUT);
406 spin_unlock(&up->port.lock);
407
408 if (pass_counter++ > PASS_LIMIT)
409 break;
410 }
411
412 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
413}
414
415static unsigned int serial_txx9_tx_empty(struct uart_port *port)
416{
417 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
418 unsigned long flags;
419 unsigned int ret;
420
421 spin_lock_irqsave(&up->port.lock, flags);
422 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
423 spin_unlock_irqrestore(&up->port.lock, flags);
424
425 return ret;
426}
427
428static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
429{
430 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
431 unsigned int ret;
432
433
434 ret = TIOCM_CAR | TIOCM_DSR;
435 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
436 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
437
438 return ret;
439}
440
441static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
442{
443 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
444
445 if (mctrl & TIOCM_RTS)
446 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
447 else
448 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
449}
450
451static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
452{
453 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
454 unsigned long flags;
455
456 spin_lock_irqsave(&up->port.lock, flags);
457 if (break_state == -1)
458 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
459 else
460 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
461 spin_unlock_irqrestore(&up->port.lock, flags);
462}
463
464static int serial_txx9_startup(struct uart_port *port)
465{
466 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
467 unsigned long flags;
468 int retval;
469
470
471
472
473
474 sio_set(up, TXX9_SIFCR,
475 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
476
477 sio_mask(up, TXX9_SIFCR,
478 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
479 sio_out(up, TXX9_SIDICR, 0);
480
481
482
483
484 sio_out(up, TXX9_SIDISR, 0);
485
486 retval = request_irq(up->port.irq, serial_txx9_interrupt,
487 IRQF_SHARED, "serial_txx9", up);
488 if (retval)
489 return retval;
490
491
492
493
494 spin_lock_irqsave(&up->port.lock, flags);
495 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
496 spin_unlock_irqrestore(&up->port.lock, flags);
497
498
499 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
500
501
502
503
504 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
505
506 return 0;
507}
508
509static void serial_txx9_shutdown(struct uart_port *port)
510{
511 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
512 unsigned long flags;
513
514
515
516
517 sio_out(up, TXX9_SIDICR, 0);
518
519 spin_lock_irqsave(&up->port.lock, flags);
520 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
521 spin_unlock_irqrestore(&up->port.lock, flags);
522
523
524
525
526 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
527
528#ifdef CONFIG_SERIAL_TXX9_CONSOLE
529 if (up->port.cons && up->port.line == up->port.cons->index) {
530 free_irq(up->port.irq, up);
531 return;
532 }
533#endif
534
535 sio_set(up, TXX9_SIFCR,
536 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
537
538 sio_mask(up, TXX9_SIFCR,
539 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
540
541
542 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
543
544 free_irq(up->port.irq, up);
545}
546
547static void
548serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
549 struct ktermios *old)
550{
551 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
552 unsigned int cval, fcr = 0;
553 unsigned long flags;
554 unsigned int baud, quot;
555
556
557
558
559 termios->c_cflag &= ~(HUPCL | CMSPAR);
560 termios->c_cflag |= CLOCAL;
561
562 cval = sio_in(up, TXX9_SILCR);
563
564 cval &= ~TXX9_SILCR_UMODE_MASK;
565 switch (termios->c_cflag & CSIZE) {
566 case CS7:
567 cval |= TXX9_SILCR_UMODE_7BIT;
568 break;
569 default:
570 case CS5:
571 case CS6:
572 case CS8:
573 cval |= TXX9_SILCR_UMODE_8BIT;
574 break;
575 }
576
577 cval &= ~TXX9_SILCR_USBL_MASK;
578 if (termios->c_cflag & CSTOPB)
579 cval |= TXX9_SILCR_USBL_2BIT;
580 else
581 cval |= TXX9_SILCR_USBL_1BIT;
582 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
583 if (termios->c_cflag & PARENB)
584 cval |= TXX9_SILCR_UPEN;
585 if (!(termios->c_cflag & PARODD))
586 cval |= TXX9_SILCR_UEPS;
587
588
589
590
591 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
592 quot = uart_get_divisor(port, baud);
593
594
595
596 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
597
598
599
600
601
602 spin_lock_irqsave(&up->port.lock, flags);
603
604
605
606
607 uart_update_timeout(port, termios->c_cflag, baud);
608
609 up->port.read_status_mask = TXX9_SIDISR_UOER |
610 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
611 if (termios->c_iflag & INPCK)
612 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
613 if (termios->c_iflag & (BRKINT | PARMRK))
614 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
615
616
617
618
619 up->port.ignore_status_mask = 0;
620 if (termios->c_iflag & IGNPAR)
621 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
622 if (termios->c_iflag & IGNBRK) {
623 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
624
625
626
627
628 if (termios->c_iflag & IGNPAR)
629 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
630 }
631
632
633
634
635 if ((termios->c_cflag & CREAD) == 0)
636 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
637
638
639 if ((termios->c_cflag & CRTSCTS) &&
640 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
641 sio_set(up, TXX9_SIFLCR,
642 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
643 } else {
644 sio_mask(up, TXX9_SIFLCR,
645 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
646 }
647
648 sio_out(up, TXX9_SILCR, cval);
649 sio_quot_set(up, quot);
650 sio_out(up, TXX9_SIFCR, fcr);
651
652 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
653 spin_unlock_irqrestore(&up->port.lock, flags);
654}
655
656static void
657serial_txx9_pm(struct uart_port *port, unsigned int state,
658 unsigned int oldstate)
659{
660
661
662
663
664
665
666
667
668 if (state == 0 && oldstate != -1)
669 serial_txx9_initialize(port);
670}
671
672static int serial_txx9_request_resource(struct uart_txx9_port *up)
673{
674 unsigned int size = TXX9_REGION_SIZE;
675 int ret = 0;
676
677 switch (up->port.iotype) {
678 default:
679 if (!up->port.mapbase)
680 break;
681
682 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
683 ret = -EBUSY;
684 break;
685 }
686
687 if (up->port.flags & UPF_IOREMAP) {
688 up->port.membase = ioremap(up->port.mapbase, size);
689 if (!up->port.membase) {
690 release_mem_region(up->port.mapbase, size);
691 ret = -ENOMEM;
692 }
693 }
694 break;
695
696 case UPIO_PORT:
697 if (!request_region(up->port.iobase, size, "serial_txx9"))
698 ret = -EBUSY;
699 break;
700 }
701 return ret;
702}
703
704static void serial_txx9_release_resource(struct uart_txx9_port *up)
705{
706 unsigned int size = TXX9_REGION_SIZE;
707
708 switch (up->port.iotype) {
709 default:
710 if (!up->port.mapbase)
711 break;
712
713 if (up->port.flags & UPF_IOREMAP) {
714 iounmap(up->port.membase);
715 up->port.membase = NULL;
716 }
717
718 release_mem_region(up->port.mapbase, size);
719 break;
720
721 case UPIO_PORT:
722 release_region(up->port.iobase, size);
723 break;
724 }
725}
726
727static void serial_txx9_release_port(struct uart_port *port)
728{
729 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
730 serial_txx9_release_resource(up);
731}
732
733static int serial_txx9_request_port(struct uart_port *port)
734{
735 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
736 return serial_txx9_request_resource(up);
737}
738
739static void serial_txx9_config_port(struct uart_port *port, int uflags)
740{
741 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
742 int ret;
743
744
745
746
747
748 ret = serial_txx9_request_resource(up);
749 if (ret < 0)
750 return;
751 port->type = PORT_TXX9;
752 up->port.fifosize = TXX9_SIO_TX_FIFO;
753
754#ifdef CONFIG_SERIAL_TXX9_CONSOLE
755 if (up->port.line == up->port.cons->index)
756 return;
757#endif
758 serial_txx9_initialize(port);
759}
760
761static const char *
762serial_txx9_type(struct uart_port *port)
763{
764 return "txx9";
765}
766
767static struct uart_ops serial_txx9_pops = {
768 .tx_empty = serial_txx9_tx_empty,
769 .set_mctrl = serial_txx9_set_mctrl,
770 .get_mctrl = serial_txx9_get_mctrl,
771 .stop_tx = serial_txx9_stop_tx,
772 .start_tx = serial_txx9_start_tx,
773 .stop_rx = serial_txx9_stop_rx,
774 .enable_ms = serial_txx9_enable_ms,
775 .break_ctl = serial_txx9_break_ctl,
776 .startup = serial_txx9_startup,
777 .shutdown = serial_txx9_shutdown,
778 .set_termios = serial_txx9_set_termios,
779 .pm = serial_txx9_pm,
780 .type = serial_txx9_type,
781 .release_port = serial_txx9_release_port,
782 .request_port = serial_txx9_request_port,
783 .config_port = serial_txx9_config_port,
784};
785
786static struct uart_txx9_port serial_txx9_ports[UART_NR];
787
788static void __init serial_txx9_register_ports(struct uart_driver *drv,
789 struct device *dev)
790{
791 int i;
792
793 for (i = 0; i < UART_NR; i++) {
794 struct uart_txx9_port *up = &serial_txx9_ports[i];
795
796 up->port.line = i;
797 up->port.ops = &serial_txx9_pops;
798 up->port.dev = dev;
799 if (up->port.iobase || up->port.mapbase)
800 uart_add_one_port(drv, &up->port);
801 }
802}
803
804#ifdef CONFIG_SERIAL_TXX9_CONSOLE
805
806
807
808
809static inline void wait_for_xmitr(struct uart_txx9_port *up)
810{
811 unsigned int tmout = 10000;
812
813
814 while (--tmout &&
815 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
816 udelay(1);
817
818
819 if (up->port.flags & UPF_CONS_FLOW) {
820 tmout = 1000000;
821 while (--tmout &&
822 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
823 udelay(1);
824 }
825}
826
827static void serial_txx9_console_putchar(struct uart_port *port, int ch)
828{
829 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
830
831 wait_for_xmitr(up);
832 sio_out(up, TXX9_SITFIFO, ch);
833}
834
835
836
837
838
839
840
841static void
842serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
843{
844 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
845 unsigned int ier, flcr;
846
847
848
849
850 ier = sio_in(up, TXX9_SIDICR);
851 sio_out(up, TXX9_SIDICR, 0);
852
853
854
855 flcr = sio_in(up, TXX9_SIFLCR);
856 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
857 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
858
859 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
860
861
862
863
864
865 wait_for_xmitr(up);
866 sio_out(up, TXX9_SIFLCR, flcr);
867 sio_out(up, TXX9_SIDICR, ier);
868}
869
870static int __init serial_txx9_console_setup(struct console *co, char *options)
871{
872 struct uart_port *port;
873 struct uart_txx9_port *up;
874 int baud = 9600;
875 int bits = 8;
876 int parity = 'n';
877 int flow = 'n';
878
879
880
881
882
883
884 if (co->index >= UART_NR)
885 co->index = 0;
886 up = &serial_txx9_ports[co->index];
887 port = &up->port;
888 if (!port->ops)
889 return -ENODEV;
890
891 serial_txx9_initialize(&up->port);
892
893 if (options)
894 uart_parse_options(options, &baud, &parity, &bits, &flow);
895
896 return uart_set_options(port, co, baud, parity, bits, flow);
897}
898
899static struct uart_driver serial_txx9_reg;
900static struct console serial_txx9_console = {
901 .name = TXX9_TTY_NAME,
902 .write = serial_txx9_console_write,
903 .device = uart_console_device,
904 .setup = serial_txx9_console_setup,
905 .flags = CON_PRINTBUFFER,
906 .index = -1,
907 .data = &serial_txx9_reg,
908};
909
910static int __init serial_txx9_console_init(void)
911{
912 register_console(&serial_txx9_console);
913 return 0;
914}
915console_initcall(serial_txx9_console_init);
916
917#define SERIAL_TXX9_CONSOLE &serial_txx9_console
918#else
919#define SERIAL_TXX9_CONSOLE NULL
920#endif
921
922static struct uart_driver serial_txx9_reg = {
923 .owner = THIS_MODULE,
924 .driver_name = "serial_txx9",
925 .dev_name = TXX9_TTY_NAME,
926 .major = TXX9_TTY_MAJOR,
927 .minor = TXX9_TTY_MINOR_START,
928 .nr = UART_NR,
929 .cons = SERIAL_TXX9_CONSOLE,
930};
931
932int __init early_serial_txx9_setup(struct uart_port *port)
933{
934 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
935 return -ENODEV;
936
937 serial_txx9_ports[port->line].port = *port;
938 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
939 serial_txx9_ports[port->line].port.flags |=
940 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
941 return 0;
942}
943
944static DEFINE_MUTEX(serial_txx9_mutex);
945
946
947
948
949
950
951
952
953
954
955
956
957static int __devinit serial_txx9_register_port(struct uart_port *port)
958{
959 int i;
960 struct uart_txx9_port *uart;
961 int ret = -ENOSPC;
962
963 mutex_lock(&serial_txx9_mutex);
964 for (i = 0; i < UART_NR; i++) {
965 uart = &serial_txx9_ports[i];
966 if (uart_match_port(&uart->port, port)) {
967 uart_remove_one_port(&serial_txx9_reg, &uart->port);
968 break;
969 }
970 }
971 if (i == UART_NR) {
972
973 for (i = 0; i < UART_NR; i++) {
974 uart = &serial_txx9_ports[i];
975 if (!(uart->port.iobase || uart->port.mapbase))
976 break;
977 }
978 }
979 if (i < UART_NR) {
980 uart->port.iobase = port->iobase;
981 uart->port.membase = port->membase;
982 uart->port.irq = port->irq;
983 uart->port.uartclk = port->uartclk;
984 uart->port.iotype = port->iotype;
985 uart->port.flags = port->flags
986 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
987 uart->port.mapbase = port->mapbase;
988 if (port->dev)
989 uart->port.dev = port->dev;
990 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
991 if (ret == 0)
992 ret = uart->port.line;
993 }
994 mutex_unlock(&serial_txx9_mutex);
995 return ret;
996}
997
998
999
1000
1001
1002
1003
1004
1005static void __devexit serial_txx9_unregister_port(int line)
1006{
1007 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1008
1009 mutex_lock(&serial_txx9_mutex);
1010 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1011 uart->port.flags = 0;
1012 uart->port.type = PORT_UNKNOWN;
1013 uart->port.iobase = 0;
1014 uart->port.mapbase = 0;
1015 uart->port.membase = NULL;
1016 uart->port.dev = NULL;
1017 mutex_unlock(&serial_txx9_mutex);
1018}
1019
1020
1021
1022
1023static int __devinit serial_txx9_probe(struct platform_device *dev)
1024{
1025 struct uart_port *p = dev->dev.platform_data;
1026 struct uart_port port;
1027 int ret, i;
1028
1029 memset(&port, 0, sizeof(struct uart_port));
1030 for (i = 0; p && p->uartclk != 0; p++, i++) {
1031 port.iobase = p->iobase;
1032 port.membase = p->membase;
1033 port.irq = p->irq;
1034 port.uartclk = p->uartclk;
1035 port.iotype = p->iotype;
1036 port.flags = p->flags;
1037 port.mapbase = p->mapbase;
1038 port.dev = &dev->dev;
1039 ret = serial_txx9_register_port(&port);
1040 if (ret < 0) {
1041 dev_err(&dev->dev, "unable to register port at index %d "
1042 "(IO%x MEM%llx IRQ%d): %d\n", i,
1043 p->iobase, (unsigned long long)p->mapbase,
1044 p->irq, ret);
1045 }
1046 }
1047 return 0;
1048}
1049
1050
1051
1052
1053static int __devexit serial_txx9_remove(struct platform_device *dev)
1054{
1055 int i;
1056
1057 for (i = 0; i < UART_NR; i++) {
1058 struct uart_txx9_port *up = &serial_txx9_ports[i];
1059
1060 if (up->port.dev == &dev->dev)
1061 serial_txx9_unregister_port(i);
1062 }
1063 return 0;
1064}
1065
1066#ifdef CONFIG_PM
1067static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1068{
1069 int i;
1070
1071 for (i = 0; i < UART_NR; i++) {
1072 struct uart_txx9_port *up = &serial_txx9_ports[i];
1073
1074 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1075 uart_suspend_port(&serial_txx9_reg, &up->port);
1076 }
1077
1078 return 0;
1079}
1080
1081static int serial_txx9_resume(struct platform_device *dev)
1082{
1083 int i;
1084
1085 for (i = 0; i < UART_NR; i++) {
1086 struct uart_txx9_port *up = &serial_txx9_ports[i];
1087
1088 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1089 uart_resume_port(&serial_txx9_reg, &up->port);
1090 }
1091
1092 return 0;
1093}
1094#endif
1095
1096static struct platform_driver serial_txx9_plat_driver = {
1097 .probe = serial_txx9_probe,
1098 .remove = __devexit_p(serial_txx9_remove),
1099#ifdef CONFIG_PM
1100 .suspend = serial_txx9_suspend,
1101 .resume = serial_txx9_resume,
1102#endif
1103 .driver = {
1104 .name = "serial_txx9",
1105 .owner = THIS_MODULE,
1106 },
1107};
1108
1109#ifdef ENABLE_SERIAL_TXX9_PCI
1110
1111
1112
1113
1114static int __devinit
1115pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1116{
1117 struct uart_port port;
1118 int line;
1119 int rc;
1120
1121 rc = pci_enable_device(dev);
1122 if (rc)
1123 return rc;
1124
1125 memset(&port, 0, sizeof(port));
1126 port.ops = &serial_txx9_pops;
1127 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1128 port.uartclk = 66670000;
1129 port.irq = dev->irq;
1130 port.iotype = UPIO_PORT;
1131 port.iobase = pci_resource_start(dev, 1);
1132 port.dev = &dev->dev;
1133 line = serial_txx9_register_port(&port);
1134 if (line < 0) {
1135 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1136 pci_disable_device(dev);
1137 return line;
1138 }
1139 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1140
1141 return 0;
1142}
1143
1144static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1145{
1146 struct uart_txx9_port *up = pci_get_drvdata(dev);
1147
1148 pci_set_drvdata(dev, NULL);
1149
1150 if (up) {
1151 serial_txx9_unregister_port(up->port.line);
1152 pci_disable_device(dev);
1153 }
1154}
1155
1156#ifdef CONFIG_PM
1157static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1158{
1159 struct uart_txx9_port *up = pci_get_drvdata(dev);
1160
1161 if (up)
1162 uart_suspend_port(&serial_txx9_reg, &up->port);
1163 pci_save_state(dev);
1164 pci_set_power_state(dev, pci_choose_state(dev, state));
1165 return 0;
1166}
1167
1168static int pciserial_txx9_resume_one(struct pci_dev *dev)
1169{
1170 struct uart_txx9_port *up = pci_get_drvdata(dev);
1171
1172 pci_set_power_state(dev, PCI_D0);
1173 pci_restore_state(dev);
1174 if (up)
1175 uart_resume_port(&serial_txx9_reg, &up->port);
1176 return 0;
1177}
1178#endif
1179
1180static const struct pci_device_id serial_txx9_pci_tbl[] = {
1181 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1182 { 0, }
1183};
1184
1185static struct pci_driver serial_txx9_pci_driver = {
1186 .name = "serial_txx9",
1187 .probe = pciserial_txx9_init_one,
1188 .remove = __devexit_p(pciserial_txx9_remove_one),
1189#ifdef CONFIG_PM
1190 .suspend = pciserial_txx9_suspend_one,
1191 .resume = pciserial_txx9_resume_one,
1192#endif
1193 .id_table = serial_txx9_pci_tbl,
1194};
1195
1196MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1197#endif
1198
1199static struct platform_device *serial_txx9_plat_devs;
1200
1201static int __init serial_txx9_init(void)
1202{
1203 int ret;
1204
1205 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1206
1207 ret = uart_register_driver(&serial_txx9_reg);
1208 if (ret)
1209 goto out;
1210
1211 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1212 if (!serial_txx9_plat_devs) {
1213 ret = -ENOMEM;
1214 goto unreg_uart_drv;
1215 }
1216
1217 ret = platform_device_add(serial_txx9_plat_devs);
1218 if (ret)
1219 goto put_dev;
1220
1221 serial_txx9_register_ports(&serial_txx9_reg,
1222 &serial_txx9_plat_devs->dev);
1223
1224 ret = platform_driver_register(&serial_txx9_plat_driver);
1225 if (ret)
1226 goto del_dev;
1227
1228#ifdef ENABLE_SERIAL_TXX9_PCI
1229 ret = pci_register_driver(&serial_txx9_pci_driver);
1230#endif
1231 if (ret == 0)
1232 goto out;
1233
1234 del_dev:
1235 platform_device_del(serial_txx9_plat_devs);
1236 put_dev:
1237 platform_device_put(serial_txx9_plat_devs);
1238 unreg_uart_drv:
1239 uart_unregister_driver(&serial_txx9_reg);
1240 out:
1241 return ret;
1242}
1243
1244static void __exit serial_txx9_exit(void)
1245{
1246 int i;
1247
1248#ifdef ENABLE_SERIAL_TXX9_PCI
1249 pci_unregister_driver(&serial_txx9_pci_driver);
1250#endif
1251 platform_driver_unregister(&serial_txx9_plat_driver);
1252 platform_device_unregister(serial_txx9_plat_devs);
1253 for (i = 0; i < UART_NR; i++) {
1254 struct uart_txx9_port *up = &serial_txx9_ports[i];
1255 if (up->port.iobase || up->port.mapbase)
1256 uart_remove_one_port(&serial_txx9_reg, &up->port);
1257 }
1258
1259 uart_unregister_driver(&serial_txx9_reg);
1260}
1261
1262module_init(serial_txx9_init);
1263module_exit(serial_txx9_exit);
1264
1265MODULE_LICENSE("GPL");
1266MODULE_DESCRIPTION("TX39/49 serial driver");
1267
1268MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1269
