1/* 2 * linux/include/asm-arm/arch-omap/io.h 3 * 4 * IO definitions for TI OMAP processors and boards 5 * 6 * Copied from linux/include/asm-arm/arch-sa1100/io.h 7 * Copyright (C) 1997-1999 Russell King 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 29 * Modifications: 30 * 06-12-1997 RMK Created. 31 * 07-04-1999 RMK Major cleanup 32 */ 33 34#ifndef __ASM_ARM_ARCH_IO_H 35#define __ASM_ARM_ARCH_IO_H 36 37#include <asm/hardware.h> 38 39#define IO_SPACE_LIMIT 0xffffffff 40 41/* 42 * We don't actually have real ISA nor PCI buses, but there is so many 43 * drivers out there that might just work if we fake them... 44 */ 45#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 46#define __mem_pci(a) (a) 47 48/* 49 * ---------------------------------------------------------------------------- 50 * I/O mapping 51 * ---------------------------------------------------------------------------- 52 */ 53 54#define PCIO_BASE 0 55 56#if defined(CONFIG_ARCH_OMAP1) 57 58#define IO_PHYS 0xFFFB0000 59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 60#define IO_SIZE 0x40000 61#define IO_VIRT (IO_PHYS - IO_OFFSET) 62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 63#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_v2p(va) ((va) + IO_OFFSET) 65 66#elif defined(CONFIG_ARCH_OMAP2) 67 68/* We map both L3 and L4 on OMAP2 */ 69#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ 70#define L3_24XX_VIRT 0xf8000000 71#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 72#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ 73#define L4_24XX_VIRT 0xd8000000 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 75 76#ifdef CONFIG_ARCH_OMAP2430 77#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 78#define L4_WK_243X_VIRT 0xd9000000 79#define L4_WK_243X_SIZE SZ_1M 80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ 81#define OMAP243X_GPMC_VIRT 0xFE000000 82#define OMAP243X_GPMC_SIZE SZ_1M 83#endif 84 85#define IO_OFFSET 0x90000000 86#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 87#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 88#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 89 90/* DSP */ 91#define DSP_MEM_24XX_PHYS OMAP24XX_DSP_MEM_BASE /* 0x58000000 */ 92#define DSP_MEM_24XX_VIRT 0xe0000000 93#define DSP_MEM_24XX_SIZE 0x28000 94#define DSP_IPI_24XX_PHYS OMAP24XX_DSP_IPI_BASE /* 0x59000000 */ 95#define DSP_IPI_24XX_VIRT 0xe1000000 96#define DSP_IPI_24XX_SIZE SZ_4K 97#define DSP_MMU_24XX_PHYS OMAP24XX_DSP_MMU_BASE /* 0x5a000000 */ 98#define DSP_MMU_24XX_VIRT 0xe2000000 99#define DSP_MMU_24XX_SIZE SZ_4K 100 101#endif 102 103#ifndef __ASSEMBLER__ 104 105/* 106 * Functions to access the OMAP IO region 107 * 108 * NOTE: - Use omap_read/write[bwl] for physical register addresses 109 * - Use __raw_read/write[bwl]() for virtual register addresses 110 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses 111 * - DO NOT use hardcoded virtual addresses to allow changing the 112 * IO address space again if needed 113 */ 114#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 115#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 116#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 117 118#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 119#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 120#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 121 122/* 16 bit uses LDRH/STRH, base +/- offset_8 */ 123typedef struct { volatile u16 offset[256]; } __regbase16; 124#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ 125 ->offset[((vaddr)&0xff)>>1] 126#define __REG16(paddr) __REGV16(io_p2v(paddr)) 127 128/* 8/32 bit uses LDR/STR, base +/- offset_12 */ 129typedef struct { volatile u8 offset[4096]; } __regbase8; 130#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ 131 ->offset[((vaddr)&4095)>>0] 132#define __REG8(paddr) __REGV8(io_p2v(paddr)) 133 134typedef struct { volatile u32 offset[4096]; } __regbase32; 135#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ 136 ->offset[((vaddr)&4095)>>2] 137#define __REG32(paddr) __REGV32(io_p2v(paddr)) 138 139extern void omap1_map_common_io(void); 140extern void omap1_init_common_hw(void); 141 142extern void omap2_map_common_io(void); 143extern void omap2_init_common_hw(void); 144 145#else 146 147#define __REG8(paddr) io_p2v(paddr) 148#define __REG16(paddr) io_p2v(paddr) 149#define __REG32(paddr) io_p2v(paddr) 150 151#endif 152 153#endif 154