1/****************************************************************************/ 2 3/* 4 * m5407sim.h -- ColdFire 5407 System Integration Module support. 5 * 6 * (C) Copyright 2000, Lineo (www.lineo.com) 7 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. 8 * 9 * Modified by David W. Miller for the MCF5307 Eval Board. 10 */ 11 12/****************************************************************************/ 13#ifndef m5407sim_h 14#define m5407sim_h 15/****************************************************************************/ 16 17/* 18 * Define the 5407 SIM register set addresses. 19 */ 20#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 21#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 22#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 23#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 24#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 25#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 26#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 27#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 28#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 29#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 30#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ 31#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 32#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 33#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 34#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 35#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 36#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 37#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 38#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 39#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 40#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 41#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 42#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 43 44#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 45#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 46#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 47#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 50 51#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ 52#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 53#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 54#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ 55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 57#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ 58#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 60#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ 61#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ 62#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 63#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ 64#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ 65#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 66#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ 67#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 68#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 69 70#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 71#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 72#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 73#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 74#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 75 76#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ 77#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ 78 79 80/* 81 * Some symbol defines for the above... 82 */ 83#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 84#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 85#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 86#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 87#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 88#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 89#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 90#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 91#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 92 93/* 94 * Macro to set IMR register. It is 32 bits on the 5407. 95 */ 96#define mcf_getimr() \ 97 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) 98 99#define mcf_setimr(imr) \ 100 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); 101 102#define mcf_getipr() \ 103 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) 104 105 106/* 107 * Some symbol defines for the Parallel Port Pin Assignment Register 108 */ 109#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 110 /* Clear to select par I/O */ 111#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ 112 /* Clear to select par I/O */ 113 114/* 115 * Defines for the IRQPAR Register 116 */ 117#define IRQ5_LEVEL4 0x80 118#define IRQ3_LEVEL6 0x40 119#define IRQ1_LEVEL2 0x20 120 121 122/* 123 * Define the Cache register flags. 124 */ 125#define CACR_DEC 0x80000000 /* Enable data cache */ 126#define CACR_DWP 0x40000000 /* Data write protection */ 127#define CACR_DESB 0x20000000 /* Enable data store buffer */ 128#define CACR_DDPI 0x10000000 /* Disable CPUSHL */ 129#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 130#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 131#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 132#define CACR_DDCM_P 0x04000000 /* No cache, precise */ 133#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 134#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 135#define CACR_BEC 0x00080000 /* Enable branch cache */ 136#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 137#define CACR_IEC 0x00008000 /* Enable instruction cache */ 138#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 139#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 140#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ 141#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ 142#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 143 144#define ACR_BASE_POS 24 /* Address Base */ 145#define ACR_MASK_POS 16 /* Address Mask */ 146#define ACR_ENABLE 0x00008000 /* Enable address */ 147#define ACR_USER 0x00000000 /* User mode access only */ 148#define ACR_SUPER 0x00002000 /* Supervisor mode only */ 149#define ACR_ANY 0x00004000 /* Match any access mode */ 150#define ACR_CM_WT 0x00000000 /* Write through mode */ 151#define ACR_CM_CP 0x00000020 /* Copyback mode */ 152#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 153#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 154#define ACR_WPROTECT 0x00000004 /* Write protect */ 155 156/****************************************************************************/ 157#endif /* m5407sim_h */ 158