1
2
3
4
5#ifdef __KERNEL__
6#ifndef _PPC_MMU_H_
7#define _PPC_MMU_H_
8
9
10#ifndef __ASSEMBLY__
11
12
13
14
15
16
17#ifndef CONFIG_PHYS_64BIT
18typedef unsigned long phys_addr_t;
19#define PHYS_FMT "%.8lx"
20#else
21typedef unsigned long long phys_addr_t;
22extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
23#define PHYS_FMT "%16Lx"
24#endif
25
26typedef struct {
27 unsigned long id;
28 unsigned long vdso_base;
29} mm_context_t;
30
31
32typedef struct _PTE {
33 unsigned long v:1;
34 unsigned long vsid:24;
35 unsigned long h:1;
36 unsigned long api:6;
37 unsigned long rpn:20;
38 unsigned long :3;
39 unsigned long r:1;
40 unsigned long c:1;
41 unsigned long w:1;
42 unsigned long i:1;
43 unsigned long m:1;
44 unsigned long g:1;
45 unsigned long :1;
46 unsigned long pp:2;
47} PTE;
48
49
50#define PP_RWXX 0
51#define PP_RWRX 1
52#define PP_RWRW 2
53#define PP_RXRX 3
54
55
56typedef struct _SEGREG {
57 unsigned long t:1;
58 unsigned long ks:1;
59 unsigned long kp:1;
60 unsigned long n:1;
61 unsigned long :4;
62 unsigned long vsid:24;
63} SEGREG;
64
65
66typedef struct _P601_BATU {
67 unsigned long bepi:15;
68 unsigned long :8;
69 unsigned long w:1;
70 unsigned long i:1;
71 unsigned long m:1;
72 unsigned long ks:1;
73 unsigned long kp:1;
74 unsigned long pp:2;
75} P601_BATU;
76
77typedef struct _BATU {
78 unsigned long bepi:15;
79 unsigned long :4;
80 unsigned long bl:11;
81 unsigned long vs:1;
82 unsigned long vp:1;
83} BATU;
84
85typedef struct _P601_BATL {
86 unsigned long brpn:15;
87 unsigned long :10;
88 unsigned long v:1;
89 unsigned long bl:6;
90} P601_BATL;
91
92typedef struct _BATL {
93 unsigned long brpn:15;
94 unsigned long :10;
95 unsigned long w:1;
96 unsigned long i:1;
97 unsigned long m:1;
98 unsigned long g:1;
99 unsigned long :1;
100 unsigned long pp:2;
101} BATL;
102
103typedef struct _BAT {
104 BATU batu;
105 BATL batl;
106} BAT;
107
108typedef struct _P601_BAT {
109 P601_BATU batu;
110 P601_BATL batl;
111} P601_BAT;
112
113#endif
114
115
116#define BL_128K 0x000
117#define BL_256K 0x001
118#define BL_512K 0x003
119#define BL_1M 0x007
120#define BL_2M 0x00F
121#define BL_4M 0x01F
122#define BL_8M 0x03F
123#define BL_16M 0x07F
124#define BL_32M 0x0FF
125#define BL_64M 0x1FF
126#define BL_128M 0x3FF
127#define BL_256M 0x7FF
128
129
130#define BPP_XX 0x00
131#define BPP_RX 0x01
132#define BPP_RW 0x02
133
134
135
136
137
138
139
140
141#define SPRN_MI_CTR 784
142#define MI_GPM 0x80000000
143#define MI_PPM 0x40000000
144#define MI_CIDEF 0x20000000
145#define MI_RSV4I 0x08000000
146#define MI_PPCS 0x02000000
147#define MI_IDXMASK 0x00001f00
148#define MI_RESETVAL 0x00000000
149
150
151
152
153#define SPRN_MI_AP 786
154#define MI_Ks 0x80000000
155#define MI_Kp 0x40000000
156
157
158
159
160
161#define SPRN_MI_EPN 787
162#define MI_EPNMASK 0xfffff000
163#define MI_EVALID 0x00000200
164#define MI_ASIDMASK 0x0000000f
165
166
167
168
169
170
171#define SPRN_MI_TWC 789
172#define MI_APG 0x000001e0
173#define MI_GUARDED 0x00000010
174#define MI_PSMASK 0x0000000c
175#define MI_PS8MEG 0x0000000c
176#define MI_PS512K 0x00000004
177#define MI_PS4K_16K 0x00000000
178#define MI_SVALID 0x00000001
179
180
181
182
183
184
185#define SPRN_MI_RPN 790
186
187
188
189
190
191
192#define MI_BOOTINIT 0x000001fd
193
194#define SPRN_MD_CTR 792
195#define MD_GPM 0x80000000
196#define MD_PPM 0x40000000
197#define MD_CIDEF 0x20000000
198#define MD_WTDEF 0x10000000
199#define MD_RSV4I 0x08000000
200#define MD_TWAM 0x04000000
201#define MD_PPCS 0x02000000
202#define MD_IDXMASK 0x00001f00
203#define MD_RESETVAL 0x04000000
204
205#define SPRN_M_CASID 793
206#define MC_ASIDMASK 0x0000000f
207
208
209
210
211
212#define SPRN_MD_AP 794
213#define MD_Ks 0x80000000
214#define MD_Kp 0x40000000
215
216
217
218
219
220#define SPRN_MD_EPN 795
221#define MD_EPNMASK 0xfffff000
222#define MD_EVALID 0x00000200
223#define MD_ASIDMASK 0x0000000f
224
225
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227
228
229
230#define SPRN_M_TWB 796
231#define M_L1TB 0xfffff000
232#define M_L1INDX 0x00000ffc
233
234
235
236
237
238
239
240#define SPRN_MD_TWC 797
241#define MD_L2TB 0xfffff000
242#define MD_L2INDX 0xfffffe00
243#define MD_APG 0x000001e0
244#define MD_GUARDED 0x00000010
245#define MD_PSMASK 0x0000000c
246#define MD_PS8MEG 0x0000000c
247#define MD_PS512K 0x00000004
248#define MD_PS4K_16K 0x00000000
249#define MD_WT 0x00000002
250#define MD_SVALID 0x00000001
251
252
253
254
255
256
257
258#define SPRN_MD_RPN 798
259
260
261
262
263#define SPRN_M_TW 799
264
265
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272
273
274
275#define PPC4XX_TLB_SIZE 64
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277
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283
284
285
286#define TLB_LO 1
287#define TLB_HI 0
288
289#define TLB_DATA TLB_LO
290#define TLB_TAG TLB_HI
291
292
293
294#define TLB_EPN_MASK 0xFFFFFC00
295#define TLB_PAGESZ_MASK 0x00000380
296#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
297#define PAGESZ_1K 0
298#define PAGESZ_4K 1
299#define PAGESZ_16K 2
300#define PAGESZ_64K 3
301#define PAGESZ_256K 4
302#define PAGESZ_1M 5
303#define PAGESZ_4M 6
304#define PAGESZ_16M 7
305#define TLB_VALID 0x00000040
306
307
308
309#define TLB_RPN_MASK 0xFFFFFC00
310#define TLB_PERM_MASK 0x00000300
311#define TLB_EX 0x00000200
312#define TLB_WR 0x00000100
313#define TLB_ZSEL_MASK 0x000000F0
314#define TLB_ZSEL(x) (((x) & 0xF) << 4)
315#define TLB_ATTR_MASK 0x0000000F
316#define TLB_W 0x00000008
317#define TLB_I 0x00000004
318#define TLB_M 0x00000002
319#define TLB_G 0x00000001
320
321
322
323
324#define PPC44x_MMUCR_TID 0x000000ff
325#define PPC44x_MMUCR_STS 0x00010000
326
327#define PPC44x_TLB_PAGEID 0
328#define PPC44x_TLB_XLAT 1
329#define PPC44x_TLB_ATTRIB 2
330
331
332#define PPC44x_TLB_EPN_MASK 0xfffffc00
333#define PPC44x_TLB_VALID 0x00000200
334#define PPC44x_TLB_TS 0x00000100
335#define PPC44x_TLB_1K 0x00000000
336#define PPC44x_TLB_4K 0x00000010
337#define PPC44x_TLB_16K 0x00000020
338#define PPC44x_TLB_64K 0x00000030
339#define PPC44x_TLB_256K 0x00000040
340#define PPC44x_TLB_1M 0x00000050
341#define PPC44x_TLB_16M 0x00000070
342#define PPC44x_TLB_256M 0x00000090
343
344
345#define PPC44x_TLB_RPN_MASK 0xfffffc00
346#define PPC44x_TLB_ERPN_MASK 0x0000000f
347
348
349#define PPC44x_TLB_ATTR_MASK 0x0000ff80
350#define PPC44x_TLB_U0 0x00008000
351#define PPC44x_TLB_U1 0x00004000
352#define PPC44x_TLB_U2 0x00002000
353#define PPC44x_TLB_U3 0x00001000
354#define PPC44x_TLB_W 0x00000800
355#define PPC44x_TLB_I 0x00000400
356#define PPC44x_TLB_M 0x00000200
357#define PPC44x_TLB_G 0x00000100
358#define PPC44x_TLB_E 0x00000080
359
360#define PPC44x_TLB_PERM_MASK 0x0000003f
361#define PPC44x_TLB_UX 0x00000020
362#define PPC44x_TLB_UW 0x00000010
363#define PPC44x_TLB_UR 0x00000008
364#define PPC44x_TLB_SX 0x00000004
365#define PPC44x_TLB_SW 0x00000002
366#define PPC44x_TLB_SR 0x00000001
367
368
369#define BOOKE_PAGESZ_1K 0
370#define BOOKE_PAGESZ_4K 1
371#define BOOKE_PAGESZ_16K 2
372#define BOOKE_PAGESZ_64K 3
373#define BOOKE_PAGESZ_256K 4
374#define BOOKE_PAGESZ_1M 5
375#define BOOKE_PAGESZ_4M 6
376#define BOOKE_PAGESZ_16M 7
377#define BOOKE_PAGESZ_64M 8
378#define BOOKE_PAGESZ_256M 9
379#define BOOKE_PAGESZ_1GB 10
380#define BOOKE_PAGESZ_4GB 11
381#define BOOKE_PAGESZ_16GB 12
382#define BOOKE_PAGESZ_64GB 13
383#define BOOKE_PAGESZ_256GB 14
384#define BOOKE_PAGESZ_1TB 15
385
386
387
388
389
390#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
391#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
392#define MAS0_NV(x) ((x) & 0x00000FFF)
393
394#define MAS1_VALID 0x80000000
395#define MAS1_IPROT 0x40000000
396#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
397#define MAS1_TS 0x00001000
398#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
399
400#define MAS2_EPN 0xFFFFF000
401#define MAS2_X0 0x00000040
402#define MAS2_X1 0x00000020
403#define MAS2_W 0x00000010
404#define MAS2_I 0x00000008
405#define MAS2_M 0x00000004
406#define MAS2_G 0x00000002
407#define MAS2_E 0x00000001
408
409#define MAS3_RPN 0xFFFFF000
410#define MAS3_U0 0x00000200
411#define MAS3_U1 0x00000100
412#define MAS3_U2 0x00000080
413#define MAS3_U3 0x00000040
414#define MAS3_UX 0x00000020
415#define MAS3_SX 0x00000010
416#define MAS3_UW 0x00000008
417#define MAS3_SW 0x00000004
418#define MAS3_UR 0x00000002
419#define MAS3_SR 0x00000001
420
421#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
422#define MAS4_TIDDSEL 0x000F0000
423#define MAS4_TSIZED(x) MAS1_TSIZE(x)
424#define MAS4_X0D 0x00000040
425#define MAS4_X1D 0x00000020
426#define MAS4_WD 0x00000010
427#define MAS4_ID 0x00000008
428#define MAS4_MD 0x00000004
429#define MAS4_GD 0x00000002
430#define MAS4_ED 0x00000001
431
432#define MAS6_SPID0 0x3FFF0000
433#define MAS6_SPID1 0x00007FFE
434#define MAS6_SAS 0x00000001
435#define MAS6_SPID MAS6_SPID0
436
437#define MAS7_RPN 0xFFFFFFFF
438
439#endif
440#endif
441