LXR linux/include/asm-sparc64/fhc.h

   1/* $Id: fhc.h,v 1.5 1999/09/21 14:39:29 davem Exp $
   2 * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
   3 *
   4 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
   5 */
   6
   7#ifndef _SPARC64_FHC_H
   8#define _SPARC64_FHC_H
   9
  10#include <linux/timer.h>
  11
  12#include <asm/oplib.h>
  13#include <asm/prom.h>
  14#include <asm/upa.h>
  15
  16struct linux_fhc;
  17
  18/* Clock board register offsets. */
  19#define CLOCK_CTRL      0x00UL  /* Main control */
  20#define CLOCK_STAT1     0x10UL  /* Status one */
  21#define CLOCK_STAT2     0x20UL  /* Status two */
  22#define CLOCK_PWRSTAT   0x30UL  /* Power status */
  23#define CLOCK_PWRPRES   0x40UL  /* Power presence */
  24#define CLOCK_TEMP      0x50UL  /* Temperature */
  25#define CLOCK_IRQDIAG   0x60UL  /* IRQ diagnostics */
  26#define CLOCK_PWRSTAT2  0x70UL  /* Power status two */
  27
  28#define CLOCK_CTRL_LLED         0x04    /* Left LED, 0 == on */
  29#define CLOCK_CTRL_MLED         0x02    /* Mid LED, 1 == on */
  30#define CLOCK_CTRL_RLED         0x01    /* RIght LED, 1 == on */
  31
  32struct linux_central {
  33        struct linux_fhc                *child;
  34        unsigned long                   cfreg;
  35        unsigned long                   clkregs;
  36        unsigned long                   clkver;
  37        int                             slots;
  38        struct device_node              *prom_node;
  39
  40        struct linux_prom_ranges        central_ranges[PROMREG_MAX];
  41        int                             num_central_ranges;
  42};
  43
  44/* Firehose controller register offsets */
  45struct fhc_regs {
  46        unsigned long                   pregs;  /* FHC internal regs */
  47#define FHC_PREGS_ID    0x00UL  /* FHC ID */
  48#define  FHC_ID_VERS            0xf0000000 /* Version of this FHC               */
  49#define  FHC_ID_PARTID          0x0ffff000 /* Part ID code (0x0f9f == FHC)      */
  50#define  FHC_ID_MANUF           0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
  51#define  FHC_ID_RESV            0x00000001 /* Read as one                       */
  52#define FHC_PREGS_RCS   0x10UL  /* FHC Reset Control/Status Register */
  53#define  FHC_RCS_POR            0x80000000 /* Last reset was a power cycle      */
  54#define  FHC_RCS_SPOR           0x40000000 /* Last reset was sw power on reset  */
  55#define  FHC_RCS_SXIR           0x20000000 /* Last reset was sw XIR reset       */
  56#define  FHC_RCS_BPOR           0x10000000 /* Last reset was due to POR button  */
  57#define  FHC_RCS_BXIR           0x08000000 /* Last reset was due to XIR button  */
  58#define  FHC_RCS_WEVENT         0x04000000 /* CPU reset was due to wakeup event */
  59#define  FHC_RCS_CFATAL         0x02000000 /* Centerplane Fatal Error signalled */
  60#define  FHC_RCS_FENAB          0x01000000 /* Fatal errors elicit system reset  */
  61#define FHC_PREGS_CTRL  0x20UL  /* FHC Control Register */
  62#define  FHC_CONTROL_ICS        0x00100000 /* Ignore Centerplane Signals        */
  63#define  FHC_CONTROL_FRST       0x00080000 /* Fatal Error Reset Enable          */
  64#define  FHC_CONTROL_LFAT       0x00040000 /* AC/DC signalled a local error     */
  65#define  FHC_CONTROL_SLINE      0x00010000 /* Firmware Synchronization Line     */
  66#define  FHC_CONTROL_DCD        0x00008000 /* DC-->DC Converter Disable         */
  67#define  FHC_CONTROL_POFF       0x00004000 /* AC/DC Controller PLL Disable      */
  68#define  FHC_CONTROL_FOFF       0x00002000 /* FHC Controller PLL Disable        */
  69#define  FHC_CONTROL_AOFF       0x00001000 /* CPU A SRAM/SBD Low Power Mode     */
  70#define  FHC_CONTROL_BOFF       0x00000800 /* CPU B SRAM/SBD Low Power Mode     */
  71#define  FHC_CONTROL_PSOFF      0x00000400 /* Turns off this FHC's power supply */
  72#define  FHC_CONTROL_IXIST      0x00000200 /* 0=FHC tells clock board it exists */
  73#define  FHC_CONTROL_XMSTR      0x00000100 /* 1=Causes this FHC to be XIR master*/
  74#define  FHC_CONTROL_LLED       0x00000040 /* 0=Left LED ON                     */
  75#define  FHC_CONTROL_MLED       0x00000020 /* 1=Middle LED ON                   */
  76#define  FHC_CONTROL_RLED       0x00000010 /* 1=Right LED                       */
  77#define  FHC_CONTROL_BPINS      0x00000003 /* Spare Bidirectional Pins          */
  78#define FHC_PREGS_BSR   0x30UL  /* FHC Board Status Register */
  79#define  FHC_BSR_DA64           0x00040000 /* Port A: 0=128bit 1=64bit data path */
  80#define  FHC_BSR_DB64           0x00020000 /* Port B: 0=128bit 1=64bit data path */
  81#define  FHC_BSR_BID            0x0001e000 /* Board ID                           */
  82#define  FHC_BSR_SA             0x00001c00 /* Port A UPA Speed (from the pins)   */
  83#define  FHC_BSR_SB             0x00000380 /* Port B UPA Speed (from the pins)   */
  84#define  FHC_BSR_NDIAG          0x00000040 /* Not in Diag Mode                   */
  85#define  FHC_BSR_NTBED          0x00000020 /* Not in TestBED Mode                */
  86#define  FHC_BSR_NIA            0x0000001c /* Jumper, bit 18 in PROM space       */
  87#define  FHC_BSR_SI             0x00000001 /* Spare input pin value              */
  88#define FHC_PREGS_ECC   0x40UL  /* FHC ECC Control Register (16 bits) */
  89#define FHC_PREGS_JCTRL 0xf0UL  /* FHC JTAG Control Register */
  90#define  FHC_JTAG_CTRL_MENAB    0x80000000 /* Indicates this is JTAG Master      */
  91#define  FHC_JTAG_CTRL_MNONE    0x40000000 /* Indicates no JTAG Master present   */
  92#define FHC_PREGS_JCMD  0x100UL /* FHC JTAG Command Register */
  93        unsigned long                   ireg;   /* FHC IGN reg */
  94#define FHC_IREG_IGN    0x00UL  /* This FHC's IGN */
  95        unsigned long                   ffregs; /* FHC fanfail regs */
  96#define FHC_FFREGS_IMAP 0x00UL  /* FHC Fanfail IMAP */
  97#define FHC_FFREGS_ICLR 0x10UL  /* FHC Fanfail ICLR */
  98        unsigned long                   sregs;  /* FHC system regs */
  99#define FHC_SREGS_IMAP  0x00UL  /* FHC System IMAP */
 100#define FHC_SREGS_ICLR  0x10UL  /* FHC System ICLR */
 101        unsigned long                   uregs;  /* FHC uart regs */
 102#define FHC_UREGS_IMAP  0x00UL  /* FHC Uart IMAP */
 103#define FHC_UREGS_ICLR  0x10UL  /* FHC Uart ICLR */
 104        unsigned long                   tregs;  /* FHC TOD regs */
 105#define FHC_TREGS_IMAP  0x00UL  /* FHC TOD IMAP */
 106#define FHC_TREGS_ICLR  0x10UL  /* FHC TOD ICLR */
 107};
 108
 109struct linux_fhc {
 110        struct linux_fhc                *next;
 111        struct linux_central            *parent;        /* NULL if not central FHC */
 112        struct fhc_regs                 fhc_regs;
 113        int                             board;
 114        int                             jtag_master;
 115        struct device_node              *prom_node;
 116
 117        struct linux_prom_ranges        fhc_ranges[PROMREG_MAX];
 118        int                             num_fhc_ranges;
 119};
 120
 121extern struct linux_central *central_bus;
 122
 123extern void apply_central_ranges(struct linux_central *central, 
 124                                 struct linux_prom_registers *regs,
 125                                 int nregs);
 126
 127extern void apply_fhc_ranges(struct linux_fhc *fhc, 
 128                             struct linux_prom_registers *regs,
 129                             int nregs);
 130
 131#endif /* !(_SPARC64_FHC_H) */
 132