1#ifndef __ARCH_DESC_H
2#define __ARCH_DESC_H
3
4#include <asm/ldt.h>
5#include <asm/segment.h>
6
7#ifndef __ASSEMBLY__
8
9#include <linux/preempt.h>
10#include <linux/smp.h>
11#include <linux/percpu.h>
12
13#include <asm/mmu.h>
14
15struct Xgt_desc_struct {
16 unsigned short size;
17 unsigned long address __attribute__((packed));
18 unsigned short pad;
19} __attribute__ ((packed));
20
21struct gdt_page
22{
23 struct desc_struct gdt[GDT_ENTRIES];
24} __attribute__((aligned(PAGE_SIZE)));
25DECLARE_PER_CPU(struct gdt_page, gdt_page);
26
27static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
28{
29 return per_cpu(gdt_page, cpu).gdt;
30}
31
32extern struct Xgt_desc_struct idt_descr;
33extern struct desc_struct idt_table[];
34extern void set_intr_gate(unsigned int irq, void * addr);
35
36static inline void pack_descriptor(__u32 *a, __u32 *b,
37 unsigned long base, unsigned long limit, unsigned char type, unsigned char flags)
38{
39 *a = ((base & 0xffff) << 16) | (limit & 0xffff);
40 *b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
41 (limit & 0x000f0000) | ((type & 0xff) << 8) | ((flags & 0xf) << 20);
42}
43
44static inline void pack_gate(__u32 *a, __u32 *b,
45 unsigned long base, unsigned short seg, unsigned char type, unsigned char flags)
46{
47 *a = (seg << 16) | (base & 0xffff);
48 *b = (base & 0xffff0000) | ((type & 0xff) << 8) | (flags & 0xff);
49}
50
51#define DESCTYPE_LDT 0x82
52#define DESCTYPE_TSS 0x89
53#define DESCTYPE_TASK 0x85
54#define DESCTYPE_INT 0x8e
55#define DESCTYPE_TRAP 0x8f
56#define DESCTYPE_DPL3 0x60
57#define DESCTYPE_S 0x10
58
59#ifdef CONFIG_PARAVIRT
60#include <asm/paravirt.h>
61#else
62#define load_TR_desc() native_load_tr_desc()
63#define load_gdt(dtr) native_load_gdt(dtr)
64#define load_idt(dtr) native_load_idt(dtr)
65#define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
66#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
67
68#define store_gdt(dtr) native_store_gdt(dtr)
69#define store_idt(dtr) native_store_idt(dtr)
70#define store_tr(tr) (tr = native_store_tr())
71#define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
72
73#define load_TLS(t, cpu) native_load_tls(t, cpu)
74#define set_ldt native_set_ldt
75
76#define write_ldt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
77#define write_gdt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
78#define write_idt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
79#endif
80
81static inline void write_dt_entry(struct desc_struct *dt,
82 int entry, u32 entry_low, u32 entry_high)
83{
84 dt[entry].a = entry_low;
85 dt[entry].b = entry_high;
86}
87
88static inline void native_set_ldt(const void *addr, unsigned int entries)
89{
90 if (likely(entries == 0))
91 __asm__ __volatile__("lldt %w0"::"q" (0));
92 else {
93 unsigned cpu = smp_processor_id();
94 __u32 a, b;
95
96 pack_descriptor(&a, &b, (unsigned long)addr,
97 entries * sizeof(struct desc_struct) - 1,
98 DESCTYPE_LDT, 0);
99 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, a, b);
100 __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
101 }
102}
103
104
105static inline void native_load_tr_desc(void)
106{
107 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
108}
109
110static inline void native_load_gdt(const struct Xgt_desc_struct *dtr)
111{
112 asm volatile("lgdt %0"::"m" (*dtr));
113}
114
115static inline void native_load_idt(const struct Xgt_desc_struct *dtr)
116{
117 asm volatile("lidt %0"::"m" (*dtr));
118}
119
120static inline void native_store_gdt(struct Xgt_desc_struct *dtr)
121{
122 asm ("sgdt %0":"=m" (*dtr));
123}
124
125static inline void native_store_idt(struct Xgt_desc_struct *dtr)
126{
127 asm ("sidt %0":"=m" (*dtr));
128}
129
130static inline unsigned long native_store_tr(void)
131{
132 unsigned long tr;
133 asm ("str %0":"=r" (tr));
134 return tr;
135}
136
137static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
138{
139 unsigned int i;
140 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
141
142 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
143 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
144}
145
146static inline void _set_gate(int gate, unsigned int type, void *addr, unsigned short seg)
147{
148 __u32 a, b;
149 pack_gate(&a, &b, (unsigned long)addr, seg, type, 0);
150 write_idt_entry(idt_table, gate, a, b);
151}
152
153static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, const void *addr)
154{
155 __u32 a, b;
156 pack_descriptor(&a, &b, (unsigned long)addr,
157 offsetof(struct tss_struct, __cacheline_filler) - 1,
158 DESCTYPE_TSS, 0);
159 write_gdt_entry(get_cpu_gdt_table(cpu), entry, a, b);
160}
161
162
163#define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
164
165#define LDT_entry_a(info) \
166 ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
167
168#define LDT_entry_b(info) \
169 (((info)->base_addr & 0xff000000) | \
170 (((info)->base_addr & 0x00ff0000) >> 16) | \
171 ((info)->limit & 0xf0000) | \
172 (((info)->read_exec_only ^ 1) << 9) | \
173 ((info)->contents << 10) | \
174 (((info)->seg_not_present ^ 1) << 15) | \
175 ((info)->seg_32bit << 22) | \
176 ((info)->limit_in_pages << 23) | \
177 ((info)->useable << 20) | \
178 0x7000)
179
180#define LDT_empty(info) (\
181 (info)->base_addr == 0 && \
182 (info)->limit == 0 && \
183 (info)->contents == 0 && \
184 (info)->read_exec_only == 1 && \
185 (info)->seg_32bit == 0 && \
186 (info)->limit_in_pages == 0 && \
187 (info)->seg_not_present == 1 && \
188 (info)->useable == 0 )
189
190static inline void clear_LDT(void)
191{
192 set_ldt(NULL, 0);
193}
194
195
196
197
198static inline void load_LDT_nolock(mm_context_t *pc)
199{
200 set_ldt(pc->ldt, pc->size);
201}
202
203static inline void load_LDT(mm_context_t *pc)
204{
205 preempt_disable();
206 load_LDT_nolock(pc);
207 preempt_enable();
208}
209
210static inline unsigned long get_desc_base(unsigned long *desc)
211{
212 unsigned long base;
213 base = ((desc[0] >> 16) & 0x0000ffff) |
214 ((desc[1] << 16) & 0x00ff0000) |
215 (desc[1] & 0xff000000);
216 return base;
217}
218
219#else
220
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234
235
236#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
237 movb idx*8+4(gdt), lo_b; \
238 movb idx*8+7(gdt), hi_b; \
239 shll $16, base; \
240 movw idx*8+2(gdt), lo_w;
241
242#endif
243
244#endif
245
