1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __SOUND_ASOUND_H
24#define __SOUND_ASOUND_H
25
26#ifdef __KERNEL__
27#include <linux/ioctl.h>
28#include <linux/types.h>
29#include <linux/time.h>
30#include <asm/byteorder.h>
31
32#ifdef __LITTLE_ENDIAN
33#define SNDRV_LITTLE_ENDIAN
34#else
35#ifdef __BIG_ENDIAN
36#define SNDRV_BIG_ENDIAN
37#else
38#error "Unsupported endian..."
39#endif
40#endif
41
42#endif
43
44
45
46
47
48#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
49#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
50#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
51#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
52#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
53 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
54 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
55 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
56
57
58
59
60
61
62
63struct snd_aes_iec958 {
64 unsigned char status[24];
65 unsigned char subcode[147];
66 unsigned char pad;
67 unsigned char dig_subframe[4];
68};
69
70
71
72
73
74
75
76#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
77
78enum {
79 SNDRV_HWDEP_IFACE_OPL2 = 0,
80 SNDRV_HWDEP_IFACE_OPL3,
81 SNDRV_HWDEP_IFACE_OPL4,
82 SNDRV_HWDEP_IFACE_SB16CSP,
83 SNDRV_HWDEP_IFACE_EMU10K1,
84 SNDRV_HWDEP_IFACE_YSS225,
85 SNDRV_HWDEP_IFACE_ICS2115,
86 SNDRV_HWDEP_IFACE_SSCAPE,
87 SNDRV_HWDEP_IFACE_VX,
88 SNDRV_HWDEP_IFACE_MIXART,
89 SNDRV_HWDEP_IFACE_USX2Y,
90 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
91 SNDRV_HWDEP_IFACE_BLUETOOTH,
92 SNDRV_HWDEP_IFACE_USX2Y_PCM,
93 SNDRV_HWDEP_IFACE_PCXHR,
94 SNDRV_HWDEP_IFACE_SB_RC,
95 SNDRV_HWDEP_IFACE_HDA,
96
97
98 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_SB_RC
99};
100
101struct snd_hwdep_info {
102 unsigned int device;
103 int card;
104 unsigned char id[64];
105 unsigned char name[80];
106 int iface;
107 unsigned char reserved[64];
108};
109
110
111struct snd_hwdep_dsp_status {
112 unsigned int version;
113 unsigned char id[32];
114 unsigned int num_dsps;
115 unsigned int dsp_loaded;
116 unsigned int chip_ready;
117 unsigned char reserved[16];
118};
119
120struct snd_hwdep_dsp_image {
121 unsigned int index;
122 unsigned char name[64];
123 unsigned char __user *image;
124 size_t length;
125 unsigned long driver_data;
126};
127
128enum {
129 SNDRV_HWDEP_IOCTL_PVERSION = _IOR ('H', 0x00, int),
130 SNDRV_HWDEP_IOCTL_INFO = _IOR ('H', 0x01, struct snd_hwdep_info),
131 SNDRV_HWDEP_IOCTL_DSP_STATUS = _IOR('H', 0x02, struct snd_hwdep_dsp_status),
132 SNDRV_HWDEP_IOCTL_DSP_LOAD = _IOW('H', 0x03, struct snd_hwdep_dsp_image)
133};
134
135
136
137
138
139
140
141#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 8)
142
143typedef unsigned long snd_pcm_uframes_t;
144typedef signed long snd_pcm_sframes_t;
145
146enum {
147 SNDRV_PCM_CLASS_GENERIC = 0,
148 SNDRV_PCM_CLASS_MULTI,
149 SNDRV_PCM_CLASS_MODEM,
150 SNDRV_PCM_CLASS_DIGITIZER,
151
152 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
153};
154
155enum {
156 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
157 SNDRV_PCM_SUBCLASS_MULTI_MIX,
158
159 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
160};
161
162enum {
163 SNDRV_PCM_STREAM_PLAYBACK = 0,
164 SNDRV_PCM_STREAM_CAPTURE,
165 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
166};
167
168typedef int __bitwise snd_pcm_access_t;
169#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0)
170#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1)
171#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2)
172#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3)
173#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4)
174#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
175
176typedef int __bitwise snd_pcm_format_t;
177#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
178#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
179#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
180#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
181#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
182#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
183#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6)
184#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7)
185#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8)
186#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9)
187#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
188#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
189#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
190#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
191#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14)
192#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15)
193#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16)
194#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17)
195#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18)
196#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19)
197#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
198#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
199#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
200#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
201#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
202#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
203#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32)
204#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33)
205#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34)
206#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35)
207#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36)
208#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37)
209#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38)
210#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39)
211#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40)
212#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41)
213#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42)
214#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43)
215#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_U18_3BE
216
217#ifdef SNDRV_LITTLE_ENDIAN
218#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
219#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
220#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
221#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
222#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
223#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
224#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
225#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
226#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
227#endif
228#ifdef SNDRV_BIG_ENDIAN
229#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
230#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
231#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
232#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
233#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
234#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
235#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
236#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
237#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
238#endif
239
240typedef int __bitwise snd_pcm_subformat_t;
241#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
242#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
243
244#define SNDRV_PCM_INFO_MMAP 0x00000001
245#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
246#define SNDRV_PCM_INFO_DOUBLE 0x00000004
247#define SNDRV_PCM_INFO_BATCH 0x00000010
248#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
249#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
250#define SNDRV_PCM_INFO_COMPLEX 0x00000400
251#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
252#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
253#define SNDRV_PCM_INFO_RESUME 0x00040000
254#define SNDRV_PCM_INFO_PAUSE 0x00080000
255#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
256#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
257#define SNDRV_PCM_INFO_SYNC_START 0x00400000
258
259typedef int __bitwise snd_pcm_state_t;
260#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0)
261#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1)
262#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2)
263#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3)
264#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4)
265#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5)
266#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6)
267#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7)
268#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8)
269#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
270
271enum {
272 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
273 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
274 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
275};
276
277union snd_pcm_sync_id {
278 unsigned char id[16];
279 unsigned short id16[8];
280 unsigned int id32[4];
281};
282
283struct snd_pcm_info {
284 unsigned int device;
285 unsigned int subdevice;
286 int stream;
287 int card;
288 unsigned char id[64];
289 unsigned char name[80];
290 unsigned char subname[32];
291 int dev_class;
292 int dev_subclass;
293 unsigned int subdevices_count;
294 unsigned int subdevices_avail;
295 union snd_pcm_sync_id sync;
296 unsigned char reserved[64];
297};
298
299typedef int __bitwise snd_pcm_hw_param_t;
300#define SNDRV_PCM_HW_PARAM_ACCESS ((__force snd_pcm_hw_param_t) 0)
301#define SNDRV_PCM_HW_PARAM_FORMAT ((__force snd_pcm_hw_param_t) 1)
302#define SNDRV_PCM_HW_PARAM_SUBFORMAT ((__force snd_pcm_hw_param_t) 2)
303#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
304#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
305
306#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS ((__force snd_pcm_hw_param_t) 8)
307#define SNDRV_PCM_HW_PARAM_FRAME_BITS ((__force snd_pcm_hw_param_t) 9)
308#define SNDRV_PCM_HW_PARAM_CHANNELS ((__force snd_pcm_hw_param_t) 10)
309#define SNDRV_PCM_HW_PARAM_RATE ((__force snd_pcm_hw_param_t) 11)
310#define SNDRV_PCM_HW_PARAM_PERIOD_TIME ((__force snd_pcm_hw_param_t) 12)
311#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE ((__force snd_pcm_hw_param_t) 13)
312#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES ((__force snd_pcm_hw_param_t) 14)
313#define SNDRV_PCM_HW_PARAM_PERIODS ((__force snd_pcm_hw_param_t) 15)
314#define SNDRV_PCM_HW_PARAM_BUFFER_TIME ((__force snd_pcm_hw_param_t) 16)
315#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE ((__force snd_pcm_hw_param_t) 17)
316#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES ((__force snd_pcm_hw_param_t) 18)
317#define SNDRV_PCM_HW_PARAM_TICK_TIME ((__force snd_pcm_hw_param_t) 19)
318#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
319#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
320
321#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0)
322
323struct snd_interval {
324 unsigned int min, max;
325 unsigned int openmin:1,
326 openmax:1,
327 integer:1,
328 empty:1;
329};
330
331#define SNDRV_MASK_MAX 256
332
333struct snd_mask {
334 u_int32_t bits[(SNDRV_MASK_MAX+31)/32];
335};
336
337struct snd_pcm_hw_params {
338 unsigned int flags;
339 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
340 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
341 struct snd_mask mres[5];
342 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
343 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
344 struct snd_interval ires[9];
345 unsigned int rmask;
346 unsigned int cmask;
347 unsigned int info;
348 unsigned int msbits;
349 unsigned int rate_num;
350 unsigned int rate_den;
351 snd_pcm_uframes_t fifo_size;
352 unsigned char reserved[64];
353};
354
355enum {
356 SNDRV_PCM_TSTAMP_NONE = 0,
357 SNDRV_PCM_TSTAMP_MMAP,
358 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_MMAP,
359};
360
361struct snd_pcm_sw_params {
362 int tstamp_mode;
363 unsigned int period_step;
364 unsigned int sleep_min;
365 snd_pcm_uframes_t avail_min;
366 snd_pcm_uframes_t xfer_align;
367 snd_pcm_uframes_t start_threshold;
368 snd_pcm_uframes_t stop_threshold;
369 snd_pcm_uframes_t silence_threshold;
370 snd_pcm_uframes_t silence_size;
371 snd_pcm_uframes_t boundary;
372 unsigned char reserved[64];
373};
374
375struct snd_pcm_channel_info {
376 unsigned int channel;
377 off_t offset;
378 unsigned int first;
379 unsigned int step;
380};
381
382struct snd_pcm_status {
383 snd_pcm_state_t state;
384 struct timespec trigger_tstamp;
385 struct timespec tstamp;
386 snd_pcm_uframes_t appl_ptr;
387 snd_pcm_uframes_t hw_ptr;
388 snd_pcm_sframes_t delay;
389 snd_pcm_uframes_t avail;
390 snd_pcm_uframes_t avail_max;
391 snd_pcm_uframes_t overrange;
392 snd_pcm_state_t suspended_state;
393 unsigned char reserved[60];
394};
395
396struct snd_pcm_mmap_status {
397 snd_pcm_state_t state;
398 int pad1;
399 snd_pcm_uframes_t hw_ptr;
400 struct timespec tstamp;
401 snd_pcm_state_t suspended_state;
402};
403
404struct snd_pcm_mmap_control {
405 snd_pcm_uframes_t appl_ptr;
406 snd_pcm_uframes_t avail_min;
407};
408
409#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0)
410#define SNDRV_PCM_SYNC_PTR_APPL (1<<1)
411#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2)
412
413struct snd_pcm_sync_ptr {
414 unsigned int flags;
415 union {
416 struct snd_pcm_mmap_status status;
417 unsigned char reserved[64];
418 } s;
419 union {
420 struct snd_pcm_mmap_control control;
421 unsigned char reserved[64];
422 } c;
423};
424
425struct snd_xferi {
426 snd_pcm_sframes_t result;
427 void __user *buf;
428 snd_pcm_uframes_t frames;
429};
430
431struct snd_xfern {
432 snd_pcm_sframes_t result;
433 void __user * __user *bufs;
434 snd_pcm_uframes_t frames;
435};
436
437enum {
438 SNDRV_PCM_IOCTL_PVERSION = _IOR('A', 0x00, int),
439 SNDRV_PCM_IOCTL_INFO = _IOR('A', 0x01, struct snd_pcm_info),
440 SNDRV_PCM_IOCTL_TSTAMP = _IOW('A', 0x02, int),
441 SNDRV_PCM_IOCTL_HW_REFINE = _IOWR('A', 0x10, struct snd_pcm_hw_params),
442 SNDRV_PCM_IOCTL_HW_PARAMS = _IOWR('A', 0x11, struct snd_pcm_hw_params),
443 SNDRV_PCM_IOCTL_HW_FREE = _IO('A', 0x12),
444 SNDRV_PCM_IOCTL_SW_PARAMS = _IOWR('A', 0x13, struct snd_pcm_sw_params),
445 SNDRV_PCM_IOCTL_STATUS = _IOR('A', 0x20, struct snd_pcm_status),
446 SNDRV_PCM_IOCTL_DELAY = _IOR('A', 0x21, snd_pcm_sframes_t),
447 SNDRV_PCM_IOCTL_HWSYNC = _IO('A', 0x22),
448 SNDRV_PCM_IOCTL_SYNC_PTR = _IOWR('A', 0x23, struct snd_pcm_sync_ptr),
449 SNDRV_PCM_IOCTL_CHANNEL_INFO = _IOR('A', 0x32, struct snd_pcm_channel_info),
450 SNDRV_PCM_IOCTL_PREPARE = _IO('A', 0x40),
451 SNDRV_PCM_IOCTL_RESET = _IO('A', 0x41),
452 SNDRV_PCM_IOCTL_START = _IO('A', 0x42),
453 SNDRV_PCM_IOCTL_DROP = _IO('A', 0x43),
454 SNDRV_PCM_IOCTL_DRAIN = _IO('A', 0x44),
455 SNDRV_PCM_IOCTL_PAUSE = _IOW('A', 0x45, int),
456 SNDRV_PCM_IOCTL_REWIND = _IOW('A', 0x46, snd_pcm_uframes_t),
457 SNDRV_PCM_IOCTL_RESUME = _IO('A', 0x47),
458 SNDRV_PCM_IOCTL_XRUN = _IO('A', 0x48),
459 SNDRV_PCM_IOCTL_FORWARD = _IOW('A', 0x49, snd_pcm_uframes_t),
460 SNDRV_PCM_IOCTL_WRITEI_FRAMES = _IOW('A', 0x50, struct snd_xferi),
461 SNDRV_PCM_IOCTL_READI_FRAMES = _IOR('A', 0x51, struct snd_xferi),
462 SNDRV_PCM_IOCTL_WRITEN_FRAMES = _IOW('A', 0x52, struct snd_xfern),
463 SNDRV_PCM_IOCTL_READN_FRAMES = _IOR('A', 0x53, struct snd_xfern),
464 SNDRV_PCM_IOCTL_LINK = _IOW('A', 0x60, int),
465 SNDRV_PCM_IOCTL_UNLINK = _IO('A', 0x61),
466};
467
468
469#define SNDRV_PCM_IOCTL_REWIND SNDRV_PCM_IOCTL_REWIND
470
471
472
473
474
475
476
477
478
479
480
481#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
482
483enum {
484 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
485 SNDRV_RAWMIDI_STREAM_INPUT,
486 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
487};
488
489#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
490#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
491#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
492
493struct snd_rawmidi_info {
494 unsigned int device;
495 unsigned int subdevice;
496 int stream;
497 int card;
498 unsigned int flags;
499 unsigned char id[64];
500 unsigned char name[80];
501 unsigned char subname[32];
502 unsigned int subdevices_count;
503 unsigned int subdevices_avail;
504 unsigned char reserved[64];
505};
506
507struct snd_rawmidi_params {
508 int stream;
509 size_t buffer_size;
510 size_t avail_min;
511 unsigned int no_active_sensing: 1;
512 unsigned char reserved[16];
513};
514
515struct snd_rawmidi_status {
516 int stream;
517 struct timespec tstamp;
518 size_t avail;
519 size_t xruns;
520 unsigned char reserved[16];
521};
522
523enum {
524 SNDRV_RAWMIDI_IOCTL_PVERSION = _IOR('W', 0x00, int),
525 SNDRV_RAWMIDI_IOCTL_INFO = _IOR('W', 0x01, struct snd_rawmidi_info),
526 SNDRV_RAWMIDI_IOCTL_PARAMS = _IOWR('W', 0x10, struct snd_rawmidi_params),
527 SNDRV_RAWMIDI_IOCTL_STATUS = _IOWR('W', 0x20, struct snd_rawmidi_status),
528 SNDRV_RAWMIDI_IOCTL_DROP = _IOW('W', 0x30, int),
529 SNDRV_RAWMIDI_IOCTL_DRAIN = _IOW('W', 0x31, int),
530};
531
532
533
534
535
536#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 5)
537
538enum {
539 SNDRV_TIMER_CLASS_NONE = -1,
540 SNDRV_TIMER_CLASS_SLAVE = 0,
541 SNDRV_TIMER_CLASS_GLOBAL,
542 SNDRV_TIMER_CLASS_CARD,
543 SNDRV_TIMER_CLASS_PCM,
544 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
545};
546
547
548enum {
549 SNDRV_TIMER_SCLASS_NONE = 0,
550 SNDRV_TIMER_SCLASS_APPLICATION,
551 SNDRV_TIMER_SCLASS_SEQUENCER,
552 SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
553 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
554};
555
556
557#define SNDRV_TIMER_GLOBAL_SYSTEM 0
558#define SNDRV_TIMER_GLOBAL_RTC 1
559#define SNDRV_TIMER_GLOBAL_HPET 2
560
561
562#define SNDRV_TIMER_FLG_SLAVE (1<<0)
563
564struct snd_timer_id {
565 int dev_class;
566 int dev_sclass;
567 int card;
568 int device;
569 int subdevice;
570};
571
572struct snd_timer_ginfo {
573 struct snd_timer_id tid;
574 unsigned int flags;
575 int card;
576 unsigned char id[64];
577 unsigned char name[80];
578 unsigned long reserved0;
579 unsigned long resolution;
580 unsigned long resolution_min;
581 unsigned long resolution_max;
582 unsigned int clients;
583 unsigned char reserved[32];
584};
585
586struct snd_timer_gparams {
587 struct snd_timer_id tid;
588 unsigned long period_num;
589 unsigned long period_den;
590 unsigned char reserved[32];
591};
592
593struct snd_timer_gstatus {
594 struct snd_timer_id tid;
595 unsigned long resolution;
596 unsigned long resolution_num;
597 unsigned long resolution_den;
598 unsigned char reserved[32];
599};
600
601struct snd_timer_select {
602 struct snd_timer_id id;
603 unsigned char reserved[32];
604};
605
606struct snd_timer_info {
607 unsigned int flags;
608 int card;
609 unsigned char id[64];
610 unsigned char name[80];
611 unsigned long reserved0;
612 unsigned long resolution;
613 unsigned char reserved[64];
614};
615
616#define SNDRV_TIMER_PSFLG_AUTO (1<<0)
617#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1)
618#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2)
619
620struct snd_timer_params {
621 unsigned int flags;
622 unsigned int ticks;
623 unsigned int queue_size;
624 unsigned int reserved0;
625 unsigned int filter;
626 unsigned char reserved[60];
627};
628
629struct snd_timer_status {
630 struct timespec tstamp;
631 unsigned int resolution;
632 unsigned int lost;
633 unsigned int overrun;
634 unsigned int queue;
635 unsigned char reserved[64];
636};
637
638enum {
639 SNDRV_TIMER_IOCTL_PVERSION = _IOR('T', 0x00, int),
640 SNDRV_TIMER_IOCTL_NEXT_DEVICE = _IOWR('T', 0x01, struct snd_timer_id),
641 SNDRV_TIMER_IOCTL_TREAD = _IOW('T', 0x02, int),
642 SNDRV_TIMER_IOCTL_GINFO = _IOWR('T', 0x03, struct snd_timer_ginfo),
643 SNDRV_TIMER_IOCTL_GPARAMS = _IOW('T', 0x04, struct snd_timer_gparams),
644 SNDRV_TIMER_IOCTL_GSTATUS = _IOWR('T', 0x05, struct snd_timer_gstatus),
645 SNDRV_TIMER_IOCTL_SELECT = _IOW('T', 0x10, struct snd_timer_select),
646 SNDRV_TIMER_IOCTL_INFO = _IOR('T', 0x11, struct snd_timer_info),
647 SNDRV_TIMER_IOCTL_PARAMS = _IOW('T', 0x12, struct snd_timer_params),
648 SNDRV_TIMER_IOCTL_STATUS = _IOR('T', 0x14, struct snd_timer_status),
649
650 SNDRV_TIMER_IOCTL_START = _IO('T', 0xa0),
651 SNDRV_TIMER_IOCTL_STOP = _IO('T', 0xa1),
652 SNDRV_TIMER_IOCTL_CONTINUE = _IO('T', 0xa2),
653 SNDRV_TIMER_IOCTL_PAUSE = _IO('T', 0xa3),
654};
655
656struct snd_timer_read {
657 unsigned int resolution;
658 unsigned int ticks;
659};
660
661enum {
662 SNDRV_TIMER_EVENT_RESOLUTION = 0,
663 SNDRV_TIMER_EVENT_TICK,
664 SNDRV_TIMER_EVENT_START,
665 SNDRV_TIMER_EVENT_STOP,
666 SNDRV_TIMER_EVENT_CONTINUE,
667 SNDRV_TIMER_EVENT_PAUSE,
668 SNDRV_TIMER_EVENT_EARLY,
669 SNDRV_TIMER_EVENT_SUSPEND,
670 SNDRV_TIMER_EVENT_RESUME,
671
672 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
673 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
674 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
675 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
676 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
677 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
678};
679
680struct snd_timer_tread {
681 int event;
682 struct timespec tstamp;
683 unsigned int val;
684};
685
686
687
688
689
690
691
692#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 4)
693
694struct snd_ctl_card_info {
695 int card;
696 int pad;
697 unsigned char id[16];
698 unsigned char driver[16];
699 unsigned char name[32];
700 unsigned char longname[80];
701 unsigned char reserved_[16];
702 unsigned char mixername[80];
703 unsigned char components[80];
704 unsigned char reserved[48];
705};
706
707typedef int __bitwise snd_ctl_elem_type_t;
708#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0)
709#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1)
710#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2)
711#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3)
712#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4)
713#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5)
714#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6)
715#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
716
717typedef int __bitwise snd_ctl_elem_iface_t;
718#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0)
719#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1)
720#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2)
721#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3)
722#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4)
723#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5)
724#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6)
725#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
726
727#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
728#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
729#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
730#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2)
731#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3)
732#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4)
733#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5)
734#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
735#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6)
736#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8)
737#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9)
738#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10)
739#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28)
740#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29)
741#define SNDRV_CTL_ELEM_ACCESS_DINDIRECT (1<<30)
742#define SNDRV_CTL_ELEM_ACCESS_INDIRECT (1<<31)
743
744
745#define SNDRV_CTL_POWER_D0 0x0000
746#define SNDRV_CTL_POWER_D1 0x0100
747#define SNDRV_CTL_POWER_D2 0x0200
748#define SNDRV_CTL_POWER_D3 0x0300
749#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000)
750#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001)
751
752struct snd_ctl_elem_id {
753 unsigned int numid;
754 snd_ctl_elem_iface_t iface;
755 unsigned int device;
756 unsigned int subdevice;
757 unsigned char name[44];
758 unsigned int index;
759};
760
761struct snd_ctl_elem_list {
762 unsigned int offset;
763 unsigned int space;
764 unsigned int used;
765 unsigned int count;
766 struct snd_ctl_elem_id __user *pids;
767 unsigned char reserved[50];
768};
769
770struct snd_ctl_elem_info {
771 struct snd_ctl_elem_id id;
772 snd_ctl_elem_type_t type;
773 unsigned int access;
774 unsigned int count;
775 pid_t owner;
776 union {
777 struct {
778 long min;
779 long max;
780 long step;
781 } integer;
782 struct {
783 long long min;
784 long long max;
785 long long step;
786 } integer64;
787 struct {
788 unsigned int items;
789 unsigned int item;
790 char name[64];
791 } enumerated;
792 unsigned char reserved[128];
793 } value;
794 union {
795 unsigned short d[4];
796 unsigned short *d_ptr;
797 } dimen;
798 unsigned char reserved[64-4*sizeof(unsigned short)];
799};
800
801struct snd_ctl_elem_value {
802 struct snd_ctl_elem_id id;
803 unsigned int indirect: 1;
804 union {
805 union {
806 long value[128];
807 long *value_ptr;
808 } integer;
809 union {
810 long long value[64];
811 long long *value_ptr;
812 } integer64;
813 union {
814 unsigned int item[128];
815 unsigned int *item_ptr;
816 } enumerated;
817 union {
818 unsigned char data[512];
819 unsigned char *data_ptr;
820 } bytes;
821 struct snd_aes_iec958 iec958;
822 } value;
823 struct timespec tstamp;
824 unsigned char reserved[128-sizeof(struct timespec)];
825};
826
827struct snd_ctl_tlv {
828 unsigned int numid;
829 unsigned int length;
830 unsigned int tlv[0];
831};
832
833enum {
834 SNDRV_CTL_IOCTL_PVERSION = _IOR('U', 0x00, int),
835 SNDRV_CTL_IOCTL_CARD_INFO = _IOR('U', 0x01, struct snd_ctl_card_info),
836 SNDRV_CTL_IOCTL_ELEM_LIST = _IOWR('U', 0x10, struct snd_ctl_elem_list),
837 SNDRV_CTL_IOCTL_ELEM_INFO = _IOWR('U', 0x11, struct snd_ctl_elem_info),
838 SNDRV_CTL_IOCTL_ELEM_READ = _IOWR('U', 0x12, struct snd_ctl_elem_value),
839 SNDRV_CTL_IOCTL_ELEM_WRITE = _IOWR('U', 0x13, struct snd_ctl_elem_value),
840 SNDRV_CTL_IOCTL_ELEM_LOCK = _IOW('U', 0x14, struct snd_ctl_elem_id),
841 SNDRV_CTL_IOCTL_ELEM_UNLOCK = _IOW('U', 0x15, struct snd_ctl_elem_id),
842 SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS = _IOWR('U', 0x16, int),
843 SNDRV_CTL_IOCTL_ELEM_ADD = _IOWR('U', 0x17, struct snd_ctl_elem_info),
844 SNDRV_CTL_IOCTL_ELEM_REPLACE = _IOWR('U', 0x18, struct snd_ctl_elem_info),
845 SNDRV_CTL_IOCTL_ELEM_REMOVE = _IOWR('U', 0x19, struct snd_ctl_elem_id),
846 SNDRV_CTL_IOCTL_TLV_READ = _IOWR('U', 0x1a, struct snd_ctl_tlv),
847 SNDRV_CTL_IOCTL_TLV_WRITE = _IOWR('U', 0x1b, struct snd_ctl_tlv),
848 SNDRV_CTL_IOCTL_TLV_COMMAND = _IOWR('U', 0x1c, struct snd_ctl_tlv),
849 SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE = _IOWR('U', 0x20, int),
850 SNDRV_CTL_IOCTL_HWDEP_INFO = _IOR('U', 0x21, struct snd_hwdep_info),
851 SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE = _IOR('U', 0x30, int),
852 SNDRV_CTL_IOCTL_PCM_INFO = _IOWR('U', 0x31, struct snd_pcm_info),
853 SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE = _IOW('U', 0x32, int),
854 SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE = _IOWR('U', 0x40, int),
855 SNDRV_CTL_IOCTL_RAWMIDI_INFO = _IOWR('U', 0x41, struct snd_rawmidi_info),
856 SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE = _IOW('U', 0x42, int),
857 SNDRV_CTL_IOCTL_POWER = _IOWR('U', 0xd0, int),
858 SNDRV_CTL_IOCTL_POWER_STATE = _IOR('U', 0xd1, int),
859};
860
861
862
863
864
865enum sndrv_ctl_event_type {
866 SNDRV_CTL_EVENT_ELEM = 0,
867 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
868};
869
870#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0)
871#define SNDRV_CTL_EVENT_MASK_INFO (1<<1)
872#define SNDRV_CTL_EVENT_MASK_ADD (1<<2)
873#define SNDRV_CTL_EVENT_MASK_TLV (1<<3)
874#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
875
876struct snd_ctl_event {
877 int type;
878 union {
879 struct {
880 unsigned int mask;
881 struct snd_ctl_elem_id id;
882 } elem;
883 unsigned char data8[60];
884 } data;
885};
886
887
888
889
890
891#define SNDRV_CTL_NAME_NONE ""
892#define SNDRV_CTL_NAME_PLAYBACK "Playback "
893#define SNDRV_CTL_NAME_CAPTURE "Capture "
894
895#define SNDRV_CTL_NAME_IEC958_NONE ""
896#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
897#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
898#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
899#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
900#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
901#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
902#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
903#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
904
905
906
907
908
909struct snd_xferv {
910 const struct iovec *vector;
911 unsigned long count;
912};
913
914enum {
915 SNDRV_IOCTL_READV = _IOW('K', 0x00, struct snd_xferv),
916 SNDRV_IOCTL_WRITEV = _IOW('K', 0x01, struct snd_xferv),
917};
918
919#endif
920