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24#include <sound/driver.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/slab.h>
28#include <linux/pci.h>
29#include <linux/dma-mapping.h>
30#include <linux/delay.h>
31#include <linux/moduleparam.h>
32#include <linux/mutex.h>
33
34#include <sound/core.h>
35#include <sound/initval.h>
36#include <sound/info.h>
37#include <sound/control.h>
38#include <sound/pcm.h>
39#include <sound/pcm_params.h>
40#include "pcxhr.h"
41#include "pcxhr_mixer.h"
42#include "pcxhr_hwdep.h"
43#include "pcxhr_core.h"
44
45#define DRIVER_NAME "pcxhr"
46
47MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
48MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
49MODULE_LICENSE("GPL");
50MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
51
52static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55static int mono[SNDRV_CARDS];
56
57module_param_array(index, int, NULL, 0444);
58MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
59module_param_array(id, charp, NULL, 0444);
60MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
61module_param_array(enable, bool, NULL, 0444);
62MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
63module_param_array(mono, bool, NULL, 0444);
64MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
65
66enum {
67 PCI_ID_VX882HR,
68 PCI_ID_PCX882HR,
69 PCI_ID_VX881HR,
70 PCI_ID_PCX881HR,
71 PCI_ID_PCX1222HR,
72 PCI_ID_PCX1221HR,
73 PCI_ID_LAST
74};
75
76static struct pci_device_id pcxhr_ids[] = {
77 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
78 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
79 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
80 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
81 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
82 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
83 { 0, }
84};
85
86MODULE_DEVICE_TABLE(pci, pcxhr_ids);
87
88struct board_parameters {
89 char* board_name;
90 short playback_chips;
91 short capture_chips;
92 short firmware_num;
93};
94static struct board_parameters pcxhr_board_params[] = {
95[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
96[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
97[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
98[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
99[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
100[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
101};
102
103
104static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
105 unsigned int* realfreq)
106{
107 unsigned int reg;
108
109 if (freq < 6900 || freq > 110250)
110 return -EINVAL;
111 reg = (28224000 * 10) / freq;
112 reg = (reg + 5) / 10;
113 if (reg < 0x200)
114 *pllreg = reg + 0x800;
115 else if (reg < 0x400)
116 *pllreg = reg & 0x1ff;
117 else if (reg < 0x800) {
118 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
119 reg &= ~1;
120 } else {
121 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
122 reg &= ~3;
123 }
124 if (realfreq)
125 *realfreq = ((28224000 * 10) / reg + 5) / 10;
126 return 0;
127}
128
129
130#define PCXHR_FREQ_REG_MASK 0x1f
131#define PCXHR_FREQ_QUARTZ_48000 0x00
132#define PCXHR_FREQ_QUARTZ_24000 0x01
133#define PCXHR_FREQ_QUARTZ_12000 0x09
134#define PCXHR_FREQ_QUARTZ_32000 0x08
135#define PCXHR_FREQ_QUARTZ_16000 0x04
136#define PCXHR_FREQ_QUARTZ_8000 0x0c
137#define PCXHR_FREQ_QUARTZ_44100 0x02
138#define PCXHR_FREQ_QUARTZ_22050 0x0a
139#define PCXHR_FREQ_QUARTZ_11025 0x06
140#define PCXHR_FREQ_PLL 0x05
141#define PCXHR_FREQ_QUARTZ_192000 0x10
142#define PCXHR_FREQ_QUARTZ_96000 0x18
143#define PCXHR_FREQ_QUARTZ_176400 0x14
144#define PCXHR_FREQ_QUARTZ_88200 0x1c
145#define PCXHR_FREQ_QUARTZ_128000 0x12
146#define PCXHR_FREQ_QUARTZ_64000 0x1a
147
148#define PCXHR_FREQ_WORD_CLOCK 0x0f
149#define PCXHR_FREQ_SYNC_AES 0x0e
150#define PCXHR_FREQ_AES_1 0x07
151#define PCXHR_FREQ_AES_2 0x0b
152#define PCXHR_FREQ_AES_3 0x03
153#define PCXHR_FREQ_AES_4 0x0d
154
155#define PCXHR_MODIFY_CLOCK_S_BIT 0x04
156
157#define PCXHR_IRQ_TIMER_FREQ 92000
158#define PCXHR_IRQ_TIMER_PERIOD 48
159
160static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
161 unsigned int *reg, unsigned int *freq)
162{
163 unsigned int val, realfreq, pllreg;
164 struct pcxhr_rmh rmh;
165 int err;
166
167 realfreq = rate;
168 switch (mgr->use_clock_type) {
169 case PCXHR_CLOCK_TYPE_INTERNAL :
170 switch (rate) {
171 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
172 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
173 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
174 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
175 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
176 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
177 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
178 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
179 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
180 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
181 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
182 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
183 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
184 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
185 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
186 default :
187 val = PCXHR_FREQ_PLL;
188
189 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
190 if (err)
191 return err;
192 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
193 rmh.cmd[0] |= IO_NUM_REG_GENCLK;
194 rmh.cmd[1] = pllreg & MASK_DSP_WORD;
195 rmh.cmd[2] = pllreg >> 24;
196 rmh.cmd_len = 3;
197 err = pcxhr_send_msg(mgr, &rmh);
198 if (err < 0) {
199 snd_printk(KERN_ERR
200 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
201 err );
202 return err;
203 }
204 }
205 break;
206 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
207 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
208 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
209 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
210 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
211 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
212 default : return -EINVAL;
213 }
214 *reg = val;
215 *freq = realfreq;
216 return 0;
217}
218
219
220int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
221{
222 unsigned int val, realfreq, speed;
223 struct pcxhr_rmh rmh;
224 int err, changed;
225
226 if (rate == 0)
227 return 0;
228
229 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
230 if (err)
231 return err;
232
233
234 if (rate < 55000)
235 speed = 0;
236 else if (rate < 100000)
237 speed = 1;
238 else
239 speed = 2;
240 if (mgr->codec_speed != speed) {
241 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
242 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
243 err = pcxhr_send_msg(mgr, &rmh);
244 if (err)
245 return err;
246
247 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
248 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
249 rmh.cmd[1] = speed;
250 rmh.cmd_len = 2;
251 err = pcxhr_send_msg(mgr, &rmh);
252 if (err)
253 return err;
254 }
255
256 snd_printdd("clock register : set %x\n", val);
257 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
258 if (err)
259 return err;
260 mgr->sample_rate_real = realfreq;
261 mgr->cur_clock_type = mgr->use_clock_type;
262
263
264 if (mgr->codec_speed != speed) {
265 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
266 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
267 err = pcxhr_send_msg(mgr, &rmh);
268 if (err)
269 return err;
270 mgr->codec_speed = speed;
271 }
272
273 if (changed) {
274 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
275 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT;
276 if (rate < PCXHR_IRQ_TIMER_FREQ)
277 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
278 else
279 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
280 rmh.cmd[2] = rate;
281 rmh.cmd_len = 3;
282 err = pcxhr_send_msg(mgr, &rmh);
283 if (err)
284 return err;
285 }
286 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
287 return 0;
288}
289
290
291int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
292 int *sample_rate)
293{
294 struct pcxhr_rmh rmh;
295 unsigned char reg;
296 int err, rate;
297
298 switch (clock_type) {
299 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
300 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
301 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
302 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
303 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
304 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
305 default : return -EINVAL;
306 }
307 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
308 rmh.cmd_len = 2;
309 rmh.cmd[0] |= IO_NUM_REG_STATUS;
310 if (mgr->last_reg_stat != reg) {
311 rmh.cmd[1] = reg;
312 err = pcxhr_send_msg(mgr, &rmh);
313 if (err)
314 return err;
315 udelay(100);
316 mgr->last_reg_stat = reg;
317 }
318 rmh.cmd[1] = REG_STATUS_CURRENT;
319 err = pcxhr_send_msg(mgr, &rmh);
320 if (err)
321 return err;
322 switch (rmh.stat[1] & 0x0f) {
323 case REG_STATUS_SYNC_32000 : rate = 32000; break;
324 case REG_STATUS_SYNC_44100 : rate = 44100; break;
325 case REG_STATUS_SYNC_48000 : rate = 48000; break;
326 case REG_STATUS_SYNC_64000 : rate = 64000; break;
327 case REG_STATUS_SYNC_88200 : rate = 88200; break;
328 case REG_STATUS_SYNC_96000 : rate = 96000; break;
329 case REG_STATUS_SYNC_128000 : rate = 128000; break;
330 case REG_STATUS_SYNC_176400 : rate = 176400; break;
331 case REG_STATUS_SYNC_192000 : rate = 192000; break;
332 default: rate = 0;
333 }
334 snd_printdd("External clock is at %d Hz\n", rate);
335 *sample_rate = rate;
336 return 0;
337}
338
339
340
341
342
343static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
344{
345 int err;
346 struct snd_pcxhr *chip;
347 struct pcxhr_rmh rmh;
348 int stream_mask, start;
349
350 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
351 start = 1;
352 else {
353 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
354 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
355 return -EINVAL;
356 }
357 start = 0;
358 }
359 if (!stream->substream)
360 return -EINVAL;
361
362 stream->timer_abs_periods = 0;
363 stream->timer_period_frag = 0;
364 stream->timer_buf_periods = 0;
365 stream->timer_is_synced = 0;
366
367 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
368
369 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
370 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
371 stream->pipe->first_audio, 0, stream_mask);
372
373 chip = snd_pcm_substream_chip(stream->substream);
374
375 err = pcxhr_send_msg(chip->mgr, &rmh);
376 if (err)
377 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
378 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
379 return err;
380}
381
382#define HEADER_FMT_BASE_LIN 0xfed00000
383#define HEADER_FMT_BASE_FLOAT 0xfad00000
384#define HEADER_FMT_INTEL 0x00008000
385#define HEADER_FMT_24BITS 0x00004000
386#define HEADER_FMT_16BITS 0x00002000
387#define HEADER_FMT_UPTO11 0x00000200
388#define HEADER_FMT_UPTO32 0x00000100
389#define HEADER_FMT_MONO 0x00000080
390
391static int pcxhr_set_format(struct pcxhr_stream *stream)
392{
393 int err, is_capture, sample_rate, stream_num;
394 struct snd_pcxhr *chip;
395 struct pcxhr_rmh rmh;
396 unsigned int header;
397
398 switch (stream->format) {
399 case SNDRV_PCM_FORMAT_U8:
400 header = HEADER_FMT_BASE_LIN;
401 break;
402 case SNDRV_PCM_FORMAT_S16_LE:
403 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
404 break;
405 case SNDRV_PCM_FORMAT_S16_BE:
406 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
407 break;
408 case SNDRV_PCM_FORMAT_S24_3LE:
409 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
410 break;
411 case SNDRV_PCM_FORMAT_S24_3BE:
412 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
413 break;
414 case SNDRV_PCM_FORMAT_FLOAT_LE:
415 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
416 break;
417 default:
418 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
419 return -EINVAL;
420 }
421 chip = snd_pcm_substream_chip(stream->substream);
422
423 sample_rate = chip->mgr->sample_rate;
424 if (sample_rate <= 32000 && sample_rate !=0) {
425 if (sample_rate <= 11025)
426 header |= HEADER_FMT_UPTO11;
427 else
428 header |= HEADER_FMT_UPTO32;
429 }
430 if (stream->channels == 1)
431 header |= HEADER_FMT_MONO;
432
433 is_capture = stream->pipe->is_capture;
434 stream_num = is_capture ? 0 : stream->substream->number;
435
436 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
437 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
438 if (is_capture)
439 rmh.cmd[0] |= 1<<12;
440 rmh.cmd[1] = 0;
441 rmh.cmd[2] = header >> 8;
442 rmh.cmd[3] = (header & 0xff) << 16;
443 rmh.cmd_len = 4;
444 err = pcxhr_send_msg(chip->mgr, &rmh);
445 if (err)
446 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
447 return err;
448}
449
450static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
451{
452 int err, is_capture, stream_num;
453 struct pcxhr_rmh rmh;
454 struct snd_pcm_substream *subs = stream->substream;
455 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
456
457 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
458 stream_num = is_capture ? 0 : subs->number;
459
460 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
461 is_capture ? 'c' : 'p',
462 chip->chip_idx, (void*)subs->runtime->dma_addr,
463 subs->runtime->dma_bytes, subs->number);
464
465 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
466 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
467
468 snd_assert(subs->runtime->dma_bytes < 0x200000);
469 rmh.cmd[1] = subs->runtime->dma_bytes * 8;
470 rmh.cmd[2] = subs->runtime->dma_addr >> 24;
471 rmh.cmd[2] |= 1<<19;
472 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
473 rmh.cmd_len = 4;
474 err = pcxhr_send_msg(chip->mgr, &rmh);
475 if (err)
476 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
477 return err;
478}
479
480
481#if 0
482static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
483{
484 struct pcxhr_rmh rmh;
485 int err;
486 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
487 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
488 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
489 1<<stream->pipe->first_audio);
490 err = pcxhr_send_msg(chip->mgr, &rmh);
491 if (err == 0) {
492 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
493 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
494 }
495 snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
496 return err;
497}
498#endif
499
500static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
501 struct pcxhr_pipe **pipe)
502{
503 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
504 *pipe = stream->pipe;
505 return 1;
506 }
507 return 0;
508}
509
510static void pcxhr_trigger_tasklet(unsigned long arg)
511{
512 unsigned long flags;
513 int i, j, err;
514 struct pcxhr_pipe *pipe;
515 struct snd_pcxhr *chip;
516 struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
517 int capture_mask = 0;
518 int playback_mask = 0;
519
520#ifdef CONFIG_SND_DEBUG_DETECT
521 struct timeval my_tv1, my_tv2;
522 do_gettimeofday(&my_tv1);
523#endif
524 mutex_lock(&mgr->setup_mutex);
525
526
527 for (i = 0; i < mgr->num_cards; i++) {
528 chip = mgr->chip[i];
529 for (j = 0; j < chip->nb_streams_capt; j++) {
530 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
531 capture_mask |= (1 << pipe->first_audio);
532 }
533 for (j = 0; j < chip->nb_streams_play; j++) {
534 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
535 playback_mask |= (1 << pipe->first_audio);
536 break;
537
538
539 }
540 }
541 }
542 if (capture_mask == 0 && playback_mask == 0) {
543 mutex_unlock(&mgr->setup_mutex);
544 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
545 return;
546 }
547
548 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
549 playback_mask, capture_mask);
550
551
552 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
553 if (err) {
554 mutex_unlock(&mgr->setup_mutex);
555 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
556 playback_mask, capture_mask);
557 return;
558 }
559
560
561 for (i = 0; i < mgr->num_cards; i++) {
562 struct pcxhr_stream *stream;
563 chip = mgr->chip[i];
564 for (j = 0; j < chip->nb_streams_capt; j++) {
565 stream = &chip->capture_stream[j];
566 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
567 err = pcxhr_set_format(stream);
568 err = pcxhr_update_r_buffer(stream);
569 }
570 }
571 for (j = 0; j < chip->nb_streams_play; j++) {
572 stream = &chip->playback_stream[j];
573 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
574 err = pcxhr_set_format(stream);
575 err = pcxhr_update_r_buffer(stream);
576 }
577 }
578 }
579
580 for (i = 0; i < mgr->num_cards; i++) {
581 struct pcxhr_stream *stream;
582 chip = mgr->chip[i];
583 for (j = 0; j < chip->nb_streams_capt; j++) {
584 stream = &chip->capture_stream[j];
585 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
586 err = pcxhr_set_stream_state(stream);
587 }
588 for (j = 0; j < chip->nb_streams_play; j++) {
589 stream = &chip->playback_stream[j];
590 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
591 err = pcxhr_set_stream_state(stream);
592 }
593 }
594
595
596 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
597 if (err) {
598 mutex_unlock(&mgr->setup_mutex);
599 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
600 playback_mask, capture_mask);
601 return;
602 }
603
604
605 spin_lock_irqsave(&mgr->lock, flags);
606 for ( i =0; i < mgr->num_cards; i++) {
607 struct pcxhr_stream *stream;
608 chip = mgr->chip[i];
609 for(j = 0; j < chip->nb_streams_capt; j++) {
610 stream = &chip->capture_stream[j];
611 if(stream->status == PCXHR_STREAM_STATUS_STARTED)
612 stream->status = PCXHR_STREAM_STATUS_RUNNING;
613 }
614 for (j = 0; j < chip->nb_streams_play; j++) {
615 stream = &chip->playback_stream[j];
616 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
617
618 stream->timer_period_frag += PCXHR_GRANULARITY;
619 stream->status = PCXHR_STREAM_STATUS_RUNNING;
620 }
621 }
622 }
623 spin_unlock_irqrestore(&mgr->lock, flags);
624
625 mutex_unlock(&mgr->setup_mutex);
626
627#ifdef CONFIG_SND_DEBUG_DETECT
628 do_gettimeofday(&my_tv2);
629 snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
630 my_tv2.tv_usec - my_tv1.tv_usec, err);
631#endif
632}
633
634
635
636
637
638static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
639{
640 struct pcxhr_stream *stream;
641 struct snd_pcm_substream *s;
642
643 switch (cmd) {
644 case SNDRV_PCM_TRIGGER_START:
645 snd_printdd("SNDRV_PCM_TRIGGER_START\n");
646 if (snd_pcm_stream_linked(subs)) {
647 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
648 snd_pcm_group_for_each_entry(s, subs) {
649 if (snd_pcm_substream_chip(s) != chip)
650 continue;
651 stream = s->runtime->private_data;
652 stream->status =
653 PCXHR_STREAM_STATUS_SCHEDULE_RUN;
654 snd_pcm_trigger_done(s, subs);
655 }
656 tasklet_hi_schedule(&chip->mgr->trigger_taskq);
657 } else {
658 stream = subs->runtime->private_data;
659 snd_printdd("Only one Substream %c %d\n",
660 stream->pipe->is_capture ? 'C' : 'P',
661 stream->pipe->first_audio);
662 if (pcxhr_set_format(stream))
663 return -EINVAL;
664 if (pcxhr_update_r_buffer(stream))
665 return -EINVAL;
666
667 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
668 if (pcxhr_set_stream_state(stream))
669 return -EINVAL;
670 stream->status = PCXHR_STREAM_STATUS_RUNNING;
671 }
672 break;
673 case SNDRV_PCM_TRIGGER_STOP:
674 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
675 snd_pcm_group_for_each_entry(s, subs) {
676 stream = s->runtime->private_data;
677 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
678 if (pcxhr_set_stream_state(stream))
679 return -EINVAL;
680 snd_pcm_trigger_done(s, subs);
681 }
682 break;
683 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
685
686 default:
687 return -EINVAL;
688 }
689 return 0;
690}
691
692
693static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
694{
695 struct pcxhr_rmh rmh;
696 int err;
697
698 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
699 if (start) {
700 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
701 rmh.cmd[0] |= PCXHR_GRANULARITY;
702 }
703 err = pcxhr_send_msg(mgr, &rmh);
704 if (err < 0)
705 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
706 return err;
707}
708
709
710
711
712static int pcxhr_prepare(struct snd_pcm_substream *subs)
713{
714 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
715 struct pcxhr_mgr *mgr = chip->mgr;
716
717
718
719 int err = 0;
720
721 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
722 subs->runtime->period_size, subs->runtime->periods,
723 subs->runtime->buffer_size);
724
725
726
727
728
729
730
731
732
733 mutex_lock(&mgr->setup_mutex);
734
735 do {
736
737
738
739
740
741
742
743
744
745
746
747
748
749 if (mgr->sample_rate != subs->runtime->rate) {
750 err = pcxhr_set_clock(mgr, subs->runtime->rate);
751 if (err)
752 break;
753 if (mgr->sample_rate == 0)
754
755 err = pcxhr_hardware_timer(mgr, 1);
756 mgr->sample_rate = subs->runtime->rate;
757 }
758 } while(0);
759
760 mutex_unlock(&mgr->setup_mutex);
761
762 return err;
763}
764
765
766
767
768
769static int pcxhr_hw_params(struct snd_pcm_substream *subs,
770 struct snd_pcm_hw_params *hw)
771{
772 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
773 struct pcxhr_mgr *mgr = chip->mgr;
774 struct pcxhr_stream *stream = subs->runtime->private_data;
775 snd_pcm_format_t format;
776 int err;
777 int channels;
778
779
780 channels = params_channels(hw);
781
782
783 format = params_format(hw);
784
785 mutex_lock(&mgr->setup_mutex);
786
787 stream->channels = channels;
788 stream->format = format;
789
790
791
792
793
794
795
796
797
798
799 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
800
801
802
803
804
805
806 mutex_unlock(&mgr->setup_mutex);
807
808 return err;
809}
810
811static int pcxhr_hw_free(struct snd_pcm_substream *subs)
812{
813 snd_pcm_lib_free_pages(subs);
814 return 0;
815}
816
817
818
819
820
821static struct snd_pcm_hardware pcxhr_caps =
822{
823 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
824 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
825 0 ),
826 .formats = ( SNDRV_PCM_FMTBIT_U8 |
827 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
828 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
829 SNDRV_PCM_FMTBIT_FLOAT_LE ),
830 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
831 .rate_min = 8000,
832 .rate_max = 192000,
833 .channels_min = 1,
834 .channels_max = 2,
835 .buffer_bytes_max = (32*1024),
836
837 .period_bytes_min = (2*PCXHR_GRANULARITY),
838 .period_bytes_max = (16*1024),
839 .periods_min = 2,
840 .periods_max = (32*1024/PCXHR_GRANULARITY),
841};
842
843
844static int pcxhr_open(struct snd_pcm_substream *subs)
845{
846 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
847 struct pcxhr_mgr *mgr = chip->mgr;
848 struct snd_pcm_runtime *runtime = subs->runtime;
849 struct pcxhr_stream *stream;
850 int is_capture;
851
852 mutex_lock(&mgr->setup_mutex);
853
854
855 runtime->hw = pcxhr_caps;
856
857 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
858 snd_printdd("pcxhr_open playback chip%d subs%d\n",
859 chip->chip_idx, subs->number);
860 is_capture = 0;
861 stream = &chip->playback_stream[subs->number];
862 } else {
863 snd_printdd("pcxhr_open capture chip%d subs%d\n",
864 chip->chip_idx, subs->number);
865 is_capture = 1;
866 if (mgr->mono_capture)
867 runtime->hw.channels_max = 1;
868 else
869 runtime->hw.channels_min = 2;
870 stream = &chip->capture_stream[subs->number];
871 }
872 if (stream->status != PCXHR_STREAM_STATUS_FREE){
873
874 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
875 chip->chip_idx, subs->number);
876 mutex_unlock(&mgr->setup_mutex);
877 return -EBUSY;
878 }
879
880
881
882
883 if (mgr->sample_rate)
884 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
885 else {
886 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
887 int external_rate;
888 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
889 &external_rate) ||
890 external_rate == 0) {
891
892 mutex_unlock(&mgr->setup_mutex);
893 return -EBUSY;
894 }
895 runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
896 }
897 }
898
899 stream->status = PCXHR_STREAM_STATUS_OPEN;
900 stream->substream = subs;
901 stream->channels = 0;
902
903 runtime->private_data = stream;
904
905 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
906 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
907
908 snd_pcm_set_sync(subs);
909
910 mgr->ref_count_rate++;
911
912 mutex_unlock(&mgr->setup_mutex);
913 return 0;
914}
915
916
917static int pcxhr_close(struct snd_pcm_substream *subs)
918{
919 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
920 struct pcxhr_mgr *mgr = chip->mgr;
921 struct pcxhr_stream *stream = subs->runtime->private_data;
922
923 mutex_lock(&mgr->setup_mutex);
924
925 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
926
927
928 if (--mgr->ref_count_rate == 0) {
929 mgr->sample_rate = 0;
930 pcxhr_hardware_timer(mgr, 0);
931 }
932
933 stream->status = PCXHR_STREAM_STATUS_FREE;
934 stream->substream = NULL;
935
936 mutex_unlock(&mgr->setup_mutex);
937
938 return 0;
939}
940
941
942static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
943{
944 unsigned long flags;
945 u_int32_t timer_period_frag;
946 int timer_buf_periods;
947 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
948 struct snd_pcm_runtime *runtime = subs->runtime;
949 struct pcxhr_stream *stream = runtime->private_data;
950
951 spin_lock_irqsave(&chip->mgr->lock, flags);
952
953
954 timer_period_frag = stream->timer_period_frag;
955 timer_buf_periods = stream->timer_buf_periods;
956
957 spin_unlock_irqrestore(&chip->mgr->lock, flags);
958
959 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
960 timer_period_frag);
961}
962
963
964static struct snd_pcm_ops pcxhr_ops = {
965 .open = pcxhr_open,
966 .close = pcxhr_close,
967 .ioctl = snd_pcm_lib_ioctl,
968 .prepare = pcxhr_prepare,
969 .hw_params = pcxhr_hw_params,
970 .hw_free = pcxhr_hw_free,
971 .trigger = pcxhr_trigger,
972 .pointer = pcxhr_stream_pointer,
973};
974
975
976
977int pcxhr_create_pcm(struct snd_pcxhr *chip)
978{
979 int err;
980 struct snd_pcm *pcm;
981 char name[32];
982
983 sprintf(name, "pcxhr %d", chip->chip_idx);
984 if ((err = snd_pcm_new(chip->card, name, 0,
985 chip->nb_streams_play,
986 chip->nb_streams_capt, &pcm)) < 0) {
987 snd_printk(KERN_ERR "cannot create pcm %s\n", name);
988 return err;
989 }
990 pcm->private_data = chip;
991
992 if (chip->nb_streams_play)
993 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
994 if (chip->nb_streams_capt)
995 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
996
997 pcm->info_flags = 0;
998 strcpy(pcm->name, name);
999
1000 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1001 snd_dma_pci_data(chip->mgr->pci),
1002 32*1024, 32*1024);
1003 chip->pcm = pcm;
1004 return 0;
1005}
1006
1007static int pcxhr_chip_free(struct snd_pcxhr *chip)
1008{
1009 kfree(chip);
1010 return 0;
1011}
1012
1013static int pcxhr_chip_dev_free(struct snd_device *device)
1014{
1015 struct snd_pcxhr *chip = device->device_data;
1016 return pcxhr_chip_free(chip);
1017}
1018
1019
1020
1021
1022static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
1023{
1024 int err;
1025 struct snd_pcxhr *chip;
1026 static struct snd_device_ops ops = {
1027 .dev_free = pcxhr_chip_dev_free,
1028 };
1029
1030 mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1031 if (! chip) {
1032 snd_printk(KERN_ERR "cannot allocate chip\n");
1033 return -ENOMEM;
1034 }
1035
1036 chip->card = card;
1037 chip->chip_idx = idx;
1038 chip->mgr = mgr;
1039
1040 if (idx < mgr->playback_chips)
1041
1042 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1043
1044 if (idx < mgr->capture_chips) {
1045 if (mgr->mono_capture)
1046 chip->nb_streams_capt = 2;
1047 else
1048 chip->nb_streams_capt = 1;
1049 }
1050
1051 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1052 pcxhr_chip_free(chip);
1053 return err;
1054 }
1055
1056 snd_card_set_dev(card, &mgr->pci->dev);
1057
1058 return 0;
1059}
1060
1061
1062static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1063{
1064 struct snd_pcxhr *chip = entry->private_data;
1065 struct pcxhr_mgr *mgr = chip->mgr;
1066
1067 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1068
1069
1070 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1071 struct pcxhr_rmh rmh;
1072 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1073 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1074 short ver_build = mgr->dsp_version & 0xff;
1075 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
1076 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
1077 if (mgr->board_has_analog)
1078 snd_iprintf(buffer, "analog io available\n");
1079 else
1080 snd_iprintf(buffer, "digital only board\n");
1081
1082
1083 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1084 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1085 int cur = rmh.stat[0];
1086 int ref = rmh.stat[1];
1087 if (ref > 0) {
1088 if (mgr->sample_rate_real != 0 &&
1089 mgr->sample_rate_real != 48000) {
1090 ref = (ref * 48000) / mgr->sample_rate_real;
1091 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
1092 ref *= 2;
1093 }
1094 cur = 100 - (100 * cur) / ref;
1095 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1096 snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
1097 rmh.stat[2], rmh.stat[3]);
1098 }
1099 }
1100 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
1101 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
1102 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1103 mgr->async_err_pipe_xrun);
1104 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1105 mgr->async_err_stream_xrun);
1106 snd_iprintf(buffer, "dsp async last other error : %x\n",
1107 mgr->async_err_other_last);
1108
1109 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1110 rmh.cmd_len = 1;
1111 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1112 rmh.dsp_stat = 0;
1113 rmh.cmd_idx = CMD_LAST_INDEX;
1114 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1115 int i;
1116 for (i = 0; i < rmh.stat_len; i++)
1117 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
1118 }
1119 } else
1120 snd_iprintf(buffer, "no firmware loaded\n");
1121 snd_iprintf(buffer, "\n");
1122}
1123static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1124{
1125 struct snd_pcxhr *chip = entry->private_data;
1126 struct pcxhr_mgr *mgr = chip->mgr;
1127 static char *texts[7] = {
1128 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
1129 };
1130
1131 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1132 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
1133 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
1134
1135
1136 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1137 int i, err, sample_rate;
1138 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
1139 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1140 if (err)
1141 break;
1142 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
1143 }
1144 } else
1145 snd_iprintf(buffer, "no firmware loaded\n");
1146 snd_iprintf(buffer, "\n");
1147}
1148
1149static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
1150{
1151 struct snd_info_entry *entry;
1152
1153 if (! snd_card_proc_new(chip->card, "info", &entry))
1154 snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1155 if (! snd_card_proc_new(chip->card, "sync", &entry))
1156 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1157}
1158
1159
1160
1161
1162
1163static int pcxhr_free(struct pcxhr_mgr *mgr)
1164{
1165 unsigned int i;
1166
1167 for (i = 0; i < mgr->num_cards; i++) {
1168 if (mgr->chip[i])
1169 snd_card_free(mgr->chip[i]->card);
1170 }
1171
1172
1173 if(mgr->dsp_loaded) {
1174 pcxhr_reset_board(mgr);
1175 snd_printdd("reset pcxhr !\n");
1176 }
1177
1178
1179 if (mgr->irq >= 0)
1180 free_irq(mgr->irq, mgr);
1181
1182 pci_release_regions(mgr->pci);
1183
1184
1185 if (mgr->hostport.area) {
1186 snd_dma_free_pages(&mgr->hostport);
1187 mgr->hostport.area = NULL;
1188 }
1189
1190 kfree(mgr->prmh);
1191
1192 pci_disable_device(mgr->pci);
1193 kfree(mgr);
1194 return 0;
1195}
1196
1197
1198
1199
1200static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1201{
1202 static int dev;
1203 struct pcxhr_mgr *mgr;
1204 unsigned int i;
1205 int err;
1206 size_t size;
1207 char *card_name;
1208
1209 if (dev >= SNDRV_CARDS)
1210 return -ENODEV;
1211 if (! enable[dev]) {
1212 dev++;
1213 return -ENOENT;
1214 }
1215
1216
1217 if ((err = pci_enable_device(pci)) < 0)
1218 return err;
1219 pci_set_master(pci);
1220
1221
1222 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
1223 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
1224 pci_disable_device(pci);
1225 return -ENXIO;
1226 }
1227
1228
1229 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1230 if (! mgr) {
1231 pci_disable_device(pci);
1232 return -ENOMEM;
1233 }
1234
1235 snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
1236 card_name = pcxhr_board_params[pci_id->driver_data].board_name;
1237 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
1238 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
1239 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
1240 mgr->mono_capture = mono[dev];
1241
1242
1243 if ((err = pci_request_regions(pci, card_name)) < 0) {
1244 kfree(mgr);
1245 pci_disable_device(pci);
1246 return err;
1247 }
1248 for (i = 0; i < 3; i++)
1249 mgr->port[i] = pci_resource_start(pci, i);
1250
1251 mgr->pci = pci;
1252 mgr->irq = -1;
1253
1254 if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED,
1255 card_name, mgr)) {
1256 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1257 pcxhr_free(mgr);
1258 return -EBUSY;
1259 }
1260 mgr->irq = pci->irq;
1261
1262 sprintf(mgr->shortname, "Digigram %s", card_name);
1263 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
1264 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1265
1266
1267 spin_lock_init(&mgr->lock);
1268 spin_lock_init(&mgr->msg_lock);
1269
1270
1271 mutex_init(&mgr->setup_mutex);
1272
1273
1274 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
1275 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
1276 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1277 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
1278 GFP_KERNEL);
1279 if (! mgr->prmh) {
1280 pcxhr_free(mgr);
1281 return -ENOMEM;
1282 }
1283
1284 for (i=0; i < PCXHR_MAX_CARDS; i++) {
1285 struct snd_card *card;
1286 char tmpid[16];
1287 int idx;
1288
1289 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1290 break;
1291 mgr->num_cards++;
1292
1293 if (index[dev] < 0)
1294 idx = index[dev];
1295 else
1296 idx = index[dev] + i;
1297
1298 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
1299 card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
1300
1301 if (! card) {
1302 snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
1303 pcxhr_free(mgr);
1304 return -ENOMEM;
1305 }
1306
1307 strcpy(card->driver, DRIVER_NAME);
1308 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1309 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1310
1311 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1312 pcxhr_free(mgr);
1313 return err;
1314 }
1315
1316 if (i == 0)
1317
1318 pcxhr_proc_init(mgr->chip[i]);
1319
1320 if ((err = snd_card_register(card)) < 0) {
1321 pcxhr_free(mgr);
1322 return err;
1323 }
1324 }
1325
1326
1327 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1328 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1329 size, &mgr->hostport) < 0) {
1330 pcxhr_free(mgr);
1331 return -ENOMEM;
1332 }
1333
1334 memset(mgr->hostport.area, 0, size);
1335
1336
1337 err = pcxhr_setup_firmware(mgr);
1338 if (err < 0) {
1339 pcxhr_free(mgr);
1340 return err;
1341 }
1342
1343 pci_set_drvdata(pci, mgr);
1344 dev++;
1345 return 0;
1346}
1347
1348static void __devexit pcxhr_remove(struct pci_dev *pci)
1349{
1350 pcxhr_free(pci_get_drvdata(pci));
1351 pci_set_drvdata(pci, NULL);
1352}
1353
1354static struct pci_driver driver = {
1355 .name = "Digigram pcxhr",
1356 .id_table = pcxhr_ids,
1357 .probe = pcxhr_probe,
1358 .remove = __devexit_p(pcxhr_remove),
1359};
1360
1361static int __init pcxhr_module_init(void)
1362{
1363 return pci_register_driver(&driver);
1364}
1365
1366static void __exit pcxhr_module_exit(void)
1367{
1368 pci_unregister_driver(&driver);
1369}
1370
1371module_init(pcxhr_module_init)
1372module_exit(pcxhr_module_exit)
1373
