LXR linux/sound/pci/vx222/vx222

   1/*
   2 * Driver for Digigram VX222 V2/Mic soundcards
   3 *
   4 * VX222-specific low-level routines
   5 *
   6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
   7 *
   8 *   This program is free software; you can redistribute it and/or modify
   9 *   it under the terms of the GNU General Public License as published by
  10 *   the Free Software Foundation; either version 2 of the License, or
  11 *   (at your option) any later version.
  12 *
  13 *   This program is distributed in the hope that it will be useful,
  14 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *   GNU General Public License for more details.
  17 *
  18 *   You should have received a copy of the GNU General Public License
  19 *   along with this program; if not, write to the Free Software
  20 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 */
  22
  23#include <sound/driver.h>
  24#include <linux/delay.h>
  25#include <linux/device.h>
  26#include <linux/firmware.h>
  27#include <linux/mutex.h>
  28
  29#include <sound/core.h>
  30#include <sound/control.h>
  31#include <sound/tlv.h>
  32#include <asm/io.h>
  33#include "vx222.h"
  34
  35
  36static int vx2_reg_offset[VX_REG_MAX] = {
  37        [VX_ICR]    = 0x00,
  38        [VX_CVR]    = 0x04,
  39        [VX_ISR]    = 0x08,
  40        [VX_IVR]    = 0x0c,
  41        [VX_RXH]    = 0x14,
  42        [VX_RXM]    = 0x18,
  43        [VX_RXL]    = 0x1c,
  44        [VX_DMA]    = 0x10,
  45        [VX_CDSP]   = 0x20,
  46        [VX_CFG]    = 0x24,
  47        [VX_RUER]   = 0x28,
  48        [VX_DATA]   = 0x2c,
  49        [VX_STATUS] = 0x30,
  50        [VX_LOFREQ] = 0x34,
  51        [VX_HIFREQ] = 0x38,
  52        [VX_CSUER]  = 0x3c,
  53        [VX_SELMIC] = 0x40,
  54        [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate
  55        [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate
  56        [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate
  57        [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET
  58        [VX_CNTRL]  = 0x50,             // VX_CNTRL_REGISTER_OFFSET
  59        [VX_GPIOC]  = 0x54,             // VX_GPIOC (new with PLX9030)
  60};
  61
  62static int vx2_reg_index[VX_REG_MAX] = {
  63        [VX_ICR]        = 1,
  64        [VX_CVR]        = 1,
  65        [VX_ISR]        = 1,
  66        [VX_IVR]        = 1,
  67        [VX_RXH]        = 1,
  68        [VX_RXM]        = 1,
  69        [VX_RXL]        = 1,
  70        [VX_DMA]        = 1,
  71        [VX_CDSP]       = 1,
  72        [VX_CFG]        = 1,
  73        [VX_RUER]       = 1,
  74        [VX_DATA]       = 1,
  75        [VX_STATUS]     = 1,
  76        [VX_LOFREQ]     = 1,
  77        [VX_HIFREQ]     = 1,
  78        [VX_CSUER]      = 1,
  79        [VX_SELMIC]     = 1,
  80        [VX_COMPOT]     = 1,
  81        [VX_SCOMPR]     = 1,
  82        [VX_GLIMIT]     = 1,
  83        [VX_INTCSR]     = 0,    /* on the PLX */
  84        [VX_CNTRL]      = 0,    /* on the PLX */
  85        [VX_GPIOC]      = 0,    /* on the PLX */
  86};
  87
  88static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg)
  89{
  90        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  91        return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
  92}
  93
  94/**
  95 * snd_vx_inb - read a byte from the register
  96 * @offset: register enum
  97 */
  98static unsigned char vx2_inb(struct vx_core *chip, int offset)
  99{
 100        return inb(vx2_reg_addr(chip, offset));
 101}
 102
 103/**
 104 * snd_vx_outb - write a byte on the register
 105 * @offset: the register offset
 106 * @val: the value to write
 107 */
 108static void vx2_outb(struct vx_core *chip, int offset, unsigned char val)
 109{
 110        outb(val, vx2_reg_addr(chip, offset));
 111        //printk("outb: %x -> %x\n", val, vx2_reg_addr(chip, offset));
 112}
 113
 114/**
 115 * snd_vx_inl - read a 32bit word from the register
 116 * @offset: register enum
 117 */
 118static unsigned int vx2_inl(struct vx_core *chip, int offset)
 119{
 120        return inl(vx2_reg_addr(chip, offset));
 121}
 122
 123/**
 124 * snd_vx_outl - write a 32bit word on the register
 125 * @offset: the register enum
 126 * @val: the value to write
 127 */
 128static void vx2_outl(struct vx_core *chip, int offset, unsigned int val)
 129{
 130        // printk("outl: %x -> %x\n", val, vx2_reg_addr(chip, offset));
 131        outl(val, vx2_reg_addr(chip, offset));
 132}
 133
 134/*
 135 * redefine macros to call directly
 136 */
 137#undef vx_inb
 138#define vx_inb(chip,reg)        vx2_inb((struct vx_core*)(chip), VX_##reg)
 139#undef vx_outb
 140#define vx_outb(chip,reg,val)   vx2_outb((struct vx_core*)(chip), VX_##reg, val)
 141#undef vx_inl
 142#define vx_inl(chip,reg)        vx2_inl((struct vx_core*)(chip), VX_##reg)
 143#undef vx_outl
 144#define vx_outl(chip,reg,val)   vx2_outl((struct vx_core*)(chip), VX_##reg, val)
 145
 146
 147/*
 148 * vx_reset_dsp - reset the DSP
 149 */
 150
 151#define XX_DSP_RESET_WAIT_TIME          2       /* ms */
 152
 153static void vx2_reset_dsp(struct vx_core *_chip)
 154{
 155        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 156
 157        /* set the reset dsp bit to 0 */
 158        vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
 159
 160        mdelay(XX_DSP_RESET_WAIT_TIME);
 161
 162        chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
 163        /* set the reset dsp bit to 1 */
 164        vx_outl(chip, CDSP, chip->regCDSP);
 165}
 166
 167
 168static int vx2_test_xilinx(struct vx_core *_chip)
 169{
 170        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 171        unsigned int data;
 172
 173        snd_printdd("testing xilinx...\n");
 174        /* This test uses several write/read sequences on TEST0 and TEST1 bits
 175         * to figure out whever or not the xilinx was correctly loaded
 176         */
 177
 178        /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
 179        vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
 180        vx_inl(chip, ISR);
 181        data = vx_inl(chip, STATUS);
 182        if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
 183                snd_printdd("bad!\n");
 184                return -ENODEV;
 185        }
 186
 187        /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
 188        vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
 189        vx_inl(chip, ISR);
 190        data = vx_inl(chip, STATUS);
 191        if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
 192                snd_printdd("bad! #2\n");
 193                return -ENODEV;
 194        }
 195
 196        if (_chip->type == VX_TYPE_BOARD) {
 197                /* not implemented on VX_2_BOARDS */
 198                /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
 199                vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
 200                vx_inl(chip, ISR);
 201                data = vx_inl(chip, STATUS);
 202                if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
 203                        snd_printdd("bad! #3\n");
 204                        return -ENODEV;
 205                }
 206
 207                /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
 208                vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
 209                vx_inl(chip, ISR);
 210                data = vx_inl(chip, STATUS);
 211                if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
 212                        snd_printdd("bad! #4\n");
 213                        return -ENODEV;
 214                }
 215        }
 216        snd_printdd("ok, xilinx fine.\n");
 217        return 0;
 218}
 219
 220
 221/**
 222 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
 223 * @do_write: 0 = read, 1 = set up for DMA write
 224 */
 225static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
 226{
 227        /* Interrupt mode and HREQ pin enabled for host transmit data transfers
 228         * (in case of the use of the pseudo-dma facility).
 229         */
 230        vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
 231
 232        /* Reset the pseudo-dma register (in case of the use of the
 233         * pseudo-dma facility).
 234         */
 235        vx_outl(chip, RESET_DMA, 0);
 236}
 237
 238/*
 239 * vx_release_pseudo_dma - disable the pseudo-DMA mode
 240 */
 241static inline void vx2_release_pseudo_dma(struct vx_core *chip)
 242{
 243        /* HREQ pin disabled. */
 244        vx_outl(chip, ICR, 0);
 245}
 246
 247
 248
 249/* pseudo-dma write */
 250static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 251                          struct vx_pipe *pipe, int count)
 252{
 253        unsigned long port = vx2_reg_addr(chip, VX_DMA);
 254        int offset = pipe->hw_ptr;
 255        u32 *addr = (u32 *)(runtime->dma_area + offset);
 256
 257        snd_assert(count % 4 == 0, return);
 258
 259        vx2_setup_pseudo_dma(chip, 1);
 260
 261        /* Transfer using pseudo-dma.
 262         */
 263        if (offset + count > pipe->buffer_bytes) {
 264                int length = pipe->buffer_bytes - offset;
 265                count -= length;
 266                length >>= 2; /* in 32bit words */
 267                /* Transfer using pseudo-dma. */
 268                while (length-- > 0) {
 269                        outl(cpu_to_le32(*addr), port);
 270                        addr++;
 271                }
 272                addr = (u32 *)runtime->dma_area;
 273                pipe->hw_ptr = 0;
 274        }
 275        pipe->hw_ptr += count;
 276        count >>= 2; /* in 32bit words */
 277        /* Transfer using pseudo-dma. */
 278        while (count-- > 0) {
 279                outl(cpu_to_le32(*addr), port);
 280                addr++;
 281        }
 282
 283        vx2_release_pseudo_dma(chip);
 284}
 285
 286
 287/* pseudo dma read */
 288static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 289                         struct vx_pipe *pipe, int count)
 290{
 291        int offset = pipe->hw_ptr;
 292        u32 *addr = (u32 *)(runtime->dma_area + offset);
 293        unsigned long port = vx2_reg_addr(chip, VX_DMA);
 294
 295        snd_assert(count % 4 == 0, return);
 296
 297        vx2_setup_pseudo_dma(chip, 0);
 298        /* Transfer using pseudo-dma.
 299         */
 300        if (offset + count > pipe->buffer_bytes) {
 301                int length = pipe->buffer_bytes - offset;
 302                count -= length;
 303                length >>= 2; /* in 32bit words */
 304                /* Transfer using pseudo-dma. */
 305                while (length-- > 0)
 306                        *addr++ = le32_to_cpu(inl(port));
 307                addr = (u32 *)runtime->dma_area;
 308                pipe->hw_ptr = 0;
 309        }
 310        pipe->hw_ptr += count;
 311        count >>= 2; /* in 32bit words */
 312        /* Transfer using pseudo-dma. */
 313        while (count-- > 0)
 314                *addr++ = le32_to_cpu(inl(port));
 315
 316        vx2_release_pseudo_dma(chip);
 317}
 318
 319#define VX_XILINX_RESET_MASK        0x40000000
 320#define VX_USERBIT0_MASK            0x00000004
 321#define VX_USERBIT1_MASK            0x00000020
 322#define VX_CNTRL_REGISTER_VALUE     0x00172012
 323
 324/*
 325 * transfer counts bits to PLX
 326 */
 327static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data)
 328{
 329        unsigned int i;
 330
 331        for (i = 0; i < counts; i++) {
 332                unsigned int val;
 333
 334                /* set the clock bit to 0. */
 335                val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
 336                vx2_outl(chip, port, val);
 337                vx2_inl(chip, port);
 338                udelay(1);
 339
 340                if (data & (1 << i))
 341                        val |= VX_USERBIT1_MASK;
 342                else
 343                        val &= ~VX_USERBIT1_MASK;
 344                vx2_outl(chip, port, val);
 345                vx2_inl(chip, port);
 346
 347                /* set the clock bit to 1. */
 348                val |= VX_USERBIT0_MASK;
 349                vx2_outl(chip, port, val);
 350                vx2_inl(chip, port);
 351                udelay(1);
 352        }
 353        return 0;
 354}
 355
 356/*
 357 * load the xilinx image
 358 */
 359static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx)
 360{
 361        unsigned int i;
 362        unsigned int port;
 363        unsigned char *image;
 364
 365        /* XILINX reset (wait at least 1 milisecond between reset on and off). */
 366        vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
 367        vx_inl(chip, CNTRL);
 368        msleep(10);
 369        vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
 370        vx_inl(chip, CNTRL);
 371        msleep(10);
 372
 373        if (chip->type == VX_TYPE_BOARD)
 374                port = VX_CNTRL;
 375        else
 376                port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */
 377
 378        image = xilinx->data;
 379        for (i = 0; i < xilinx->size; i++, image++) {
 380                if (put_xilinx_data(chip, port, 8, *image) < 0)
 381                        return -EINVAL;
 382                /* don't take too much time in this loop... */
 383                cond_resched();
 384        }
 385        put_xilinx_data(chip, port, 4, 0xff); /* end signature */
 386
 387        msleep(200);
 388
 389        /* test after loading (is buggy with VX222) */
 390        if (chip->type != VX_TYPE_BOARD) {
 391                /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */
 392                i = vx_inl(chip, GPIOC);
 393                if (i & 0x0100)
 394                        return 0;
 395                snd_printk(KERN_ERR "vx222: xilinx test failed after load, GPIOC=0x%x\n", i);
 396                return -EINVAL;
 397        }
 398
 399        return 0;
 400}
 401
 402        
 403/*
 404 * load the boot/dsp images
 405 */
 406static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp)
 407{
 408        int err;
 409
 410        switch (index) {
 411        case 1:
 412                /* xilinx image */
 413                if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0)
 414                        return err;
 415                if ((err = vx2_test_xilinx(vx)) < 0)
 416                        return err;
 417                return 0;
 418        case 2:
 419                /* DSP boot */
 420                return snd_vx_dsp_boot(vx, dsp);
 421        case 3:
 422                /* DSP image */
 423                return snd_vx_dsp_load(vx, dsp);
 424        default:
 425                snd_BUG();
 426                return -EINVAL;
 427        }
 428}
 429
 430
 431/*
 432 * vx_test_and_ack - test and acknowledge interrupt
 433 *
 434 * called from irq hander, too
 435 *
 436 * spinlock held!
 437 */
 438static int vx2_test_and_ack(struct vx_core *chip)
 439{
 440        /* not booted yet? */
 441        if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
 442                return -ENXIO;
 443
 444        if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
 445                return -EIO;
 446        
 447        /* ok, interrupts generated, now ack it */
 448        /* set ACQUIT bit up and down */
 449        vx_outl(chip, STATUS, 0);
 450        /* useless read just to spend some time and maintain
 451         * the ACQUIT signal up for a while ( a bus cycle )
 452         */
 453        vx_inl(chip, STATUS);
 454        /* ack */
 455        vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
 456        /* useless read just to spend some time and maintain
 457         * the ACQUIT signal up for a while ( a bus cycle ) */
 458        vx_inl(chip, STATUS);
 459        /* clear */
 460        vx_outl(chip, STATUS, 0);
 461
 462        return 0;
 463}
 464
 465
 466/*
 467 * vx_validate_irq - enable/disable IRQ
 468 */
 469static void vx2_validate_irq(struct vx_core *_chip, int enable)
 470{
 471        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 472
 473        /* Set the interrupt enable bit to 1 in CDSP register */
 474        if (enable) {
 475                /* Set the PCI interrupt enable bit to 1.*/
 476                vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
 477                chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
 478        } else {
 479                /* Set the PCI interrupt enable bit to 0. */
 480                vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
 481                chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
 482        }
 483        vx_outl(chip, CDSP, chip->regCDSP);
 484}
 485
 486
 487/*
 488 * write an AKM codec data (24bit)
 489 */
 490static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data)
 491{
 492        unsigned int i;
 493
 494        vx_inl(chip, HIFREQ);
 495
 496        /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
 497        for (i = 0; i < 24; i++, data <<= 1)
 498                vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
 499        /* Terminate access to codec registers */
 500        vx_inl(chip, RUER);
 501}
 502
 503
 504#define AKM_CODEC_POWER_CONTROL_CMD 0xA007
 505#define AKM_CODEC_RESET_ON_CMD      0xA100
 506#define AKM_CODEC_RESET_OFF_CMD     0xA103
 507#define AKM_CODEC_CLOCK_FORMAT_CMD  0xA240
 508#define AKM_CODEC_MUTE_CMD          0xA38D
 509#define AKM_CODEC_UNMUTE_CMD        0xA30D
 510#define AKM_CODEC_LEFT_LEVEL_CMD    0xA400
 511#define AKM_CODEC_RIGHT_LEVEL_CMD   0xA500
 512
 513static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
 514    0x7f,       // [000] =  +0.000 dB  ->  AKM(0x7f) =  +0.000 dB  error(+0.000 dB)
 515    0x7d,       // [001] =  -0.500 dB  ->  AKM(0x7d) =  -0.572 dB  error(-0.072 dB)
 516    0x7c,       // [002] =  -1.000 dB  ->  AKM(0x7c) =  -0.873 dB  error(+0.127 dB)
 517    0x7a,       // [003] =  -1.500 dB  ->  AKM(0x7a) =  -1.508 dB  error(-0.008 dB)
 518    0x79,       // [004] =  -2.000 dB  ->  AKM(0x79) =  -1.844 dB  error(+0.156 dB)
 519    0x77,       // [005] =  -2.500 dB  ->  AKM(0x77) =  -2.557 dB  error(-0.057 dB)
 520    0x76,       // [006] =  -3.000 dB  ->  AKM(0x76) =  -2.937 dB  error(+0.063 dB)
 521    0x75,       // [007] =  -3.500 dB  ->  AKM(0x75) =  -3.334 dB  error(+0.166 dB)
 522    0x73,       // [008] =  -4.000 dB  ->  AKM(0x73) =  -4.188 dB  error(-0.188 dB)
 523    0x72,       // [009] =  -4.500 dB  ->  AKM(0x72) =  -4.648 dB  error(-0.148 dB)
 524    0x71,       // [010] =  -5.000 dB  ->  AKM(0x71) =  -5.134 dB  error(-0.134 dB)
 525    0x70,       // [011] =  -5.500 dB  ->  AKM(0x70) =  -5.649 dB  error(-0.149 dB)
 526    0x6f,       // [012] =  -6.000 dB  ->  AKM(0x6f) =  -6.056 dB  error(-0.056 dB)
 527    0x6d,       // [013] =  -6.500 dB  ->  AKM(0x6d) =  -6.631 dB  error(-0.131 dB)
 528    0x6c,       // [014] =  -7.000 dB  ->  AKM(0x6c) =  -6.933 dB  error(+0.067 dB)
 529    0x6a,       // [015] =  -7.500 dB  ->  AKM(0x6a) =  -7.571 dB  error(-0.071 dB)
 530    0x69,       // [016] =  -8.000 dB  ->  AKM(0x69) =  -7.909 dB  error(+0.091 dB)
 531    0x67,       // [017] =  -8.500 dB  ->  AKM(0x67) =  -8.626 dB  error(-0.126 dB)
 532    0x66,       // [018] =  -9.000 dB  ->  AKM(0x66) =  -9.008 dB  error(-0.008 dB)
 533    0x65,       // [019] =  -9.500 dB  ->  AKM(0x65) =  -9.407 dB  error(+0.093 dB)
 534    0x64,       // [020] = -10.000 dB  ->  AKM(0x64) =  -9.826 dB  error(+0.174 dB)
 535    0x62,       // [021] = -10.500 dB  ->  AKM(0x62) = -10.730 dB  error(-0.230 dB)
 536    0x61,       // [022] = -11.000 dB  ->  AKM(0x61) = -11.219 dB  error(-0.219 dB)
 537    0x60,       // [023] = -11.500 dB  ->  AKM(0x60) = -11.738 dB  error(-0.238 dB)
 538    0x5f,       // [024] = -12.000 dB  ->  AKM(0x5f) = -12.149 dB  error(-0.149 dB)
 539    0x5e,       // [025] = -12.500 dB  ->  AKM(0x5e) = -12.434 dB  error(+0.066 dB)
 540    0x5c,       // [026] = -13.000 dB  ->  AKM(0x5c) = -13.033 dB  error(-0.033 dB)
 541    0x5b,       // [027] = -13.500 dB  ->  AKM(0x5b) = -13.350 dB  error(+0.150 dB)
 542    0x59,       // [028] = -14.000 dB  ->  AKM(0x59) = -14.018 dB  error(-0.018 dB)
 543    0x58,       // [029] = -14.500 dB  ->  AKM(0x58) = -14.373 dB  error(+0.127 dB)
 544    0x56,       // [030] = -15.000 dB  ->  AKM(0x56) = -15.130 dB  error(-0.130 dB)
 545    0x55,       // [031] = -15.500 dB  ->  AKM(0x55) = -15.534 dB  error(-0.034 dB)
 546    0x54,       // [032] = -16.000 dB  ->  AKM(0x54) = -15.958 dB  error(+0.042 dB)
 547    0x53,       // [033] = -16.500 dB  ->  AKM(0x53) = -16.404 dB  error(+0.096 dB)
 548    0x52,       // [034] = -17.000 dB  ->  AKM(0x52) = -16.874 dB  error(+0.126 dB)
 549    0x51,       // [035] = -17.500 dB  ->  AKM(0x51) = -17.371 dB  error(+0.129 dB)
 550    0x50,       // [036] = -18.000 dB  ->  AKM(0x50) = -17.898 dB  error(+0.102 dB)
 551    0x4e,       // [037] = -18.500 dB  ->  AKM(0x4e) = -18.605 dB  error(-0.105 dB)
 552    0x4d,       // [038] = -19.000 dB  ->  AKM(0x4d) = -18.905 dB  error(+0.095 dB)
 553    0x4b,       // [039] = -19.500 dB  ->  AKM(0x4b) = -19.538 dB  error(-0.038 dB)
 554    0x4a,       // [040] = -20.000 dB  ->  AKM(0x4a) = -19.872 dB  error(+0.128 dB)
 555    0x48,       // [041] = -20.500 dB  ->  AKM(0x48) = -20.583 dB  error(-0.083 dB)
 556    0x47,       // [042] = -21.000 dB  ->  AKM(0x47) = -20.961 dB  error(+0.039 dB)
 557    0x46,       // [043] = -21.500 dB  ->  AKM(0x46) = -21.356 dB  error(+0.144 dB)
 558    0x44,       // [044] = -22.000 dB  ->  AKM(0x44) = -22.206 dB  error(-0.206 dB)
 559    0x43,       // [045] = -22.500 dB  ->  AKM(0x43) = -22.664 dB  error(-0.164 dB)
 560    0x42,       // [046] = -23.000 dB  ->  AKM(0x42) = -23.147 dB  error(-0.147 dB)
 561    0x41,       // [047] = -23.500 dB  ->  AKM(0x41) = -23.659 dB  error(-0.159 dB)
 562    0x40,       // [048] = -24.000 dB  ->  AKM(0x40) = -24.203 dB  error(-0.203 dB)
 563    0x3f,       // [049] = -24.500 dB  ->  AKM(0x3f) = -24.635 dB  error(-0.135 dB)
 564    0x3e,       // [050] = -25.000 dB  ->  AKM(0x3e) = -24.935 dB  error(+0.065 dB)
 565    0x3c,       // [051] = -25.500 dB  ->  AKM(0x3c) = -25.569 dB  error(-0.069 dB)
 566    0x3b,       // [052] = -26.000 dB  ->  AKM(0x3b) = -25.904 dB  error(+0.096 dB)
 567    0x39,       // [053] = -26.500 dB  ->  AKM(0x39) = -26.615 dB  error(-0.115 dB)
 568    0x38,       // [054] = -27.000 dB  ->  AKM(0x38) = -26.994 dB  error(+0.006 dB)
 569    0x37,       // [055] = -27.500 dB  ->  AKM(0x37) = -27.390 dB  error(+0.110 dB)
 570    0x36,       // [056] = -28.000 dB  ->  AKM(0x36) = -27.804 dB  error(+0.196 dB)
 571    0x34,       // [057] = -28.500 dB  ->  AKM(0x34) = -28.699 dB  error(-0.199 dB)
 572    0x33,       // [058] = -29.000 dB  ->  AKM(0x33) = -29.183 dB  error(-0.183 dB)
 573    0x32,       // [059] = -29.500 dB  ->  AKM(0x32) = -29.696 dB  error(-0.196 dB)
 574    0x31,       // [060] = -30.000 dB  ->  AKM(0x31) = -30.241 dB  error(-0.241 dB)
 575    0x31,       // [061] = -30.500 dB  ->  AKM(0x31) = -30.241 dB  error(+0.259 dB)
 576    0x30,       // [062] = -31.000 dB  ->  AKM(0x30) = -30.823 dB  error(+0.177 dB)
 577    0x2e,       // [063] = -31.500 dB  ->  AKM(0x2e) = -31.610 dB  error(-0.110 dB)
 578    0x2d,       // [064] = -32.000 dB  ->  AKM(0x2d) = -31.945 dB  error(+0.055 dB)
 579    0x2b,       // [065] = -32.500 dB  ->  AKM(0x2b) = -32.659 dB  error(-0.159 dB)
 580    0x2a,       // [066] = -33.000 dB  ->  AKM(0x2a) = -33.038 dB  error(-0.038 dB)
 581    0x29,       // [067] = -33.500 dB  ->  AKM(0x29) = -33.435 dB  error(+0.065 dB)
 582    0x28,       // [068] = -34.000 dB  ->  AKM(0x28) = -33.852 dB  error(+0.148 dB)
 583    0x27,       // [069] = -34.500 dB  ->  AKM(0x27) = -34.289 dB  error(+0.211 dB)
 584    0x25,       // [070] = -35.000 dB  ->  AKM(0x25) = -35.235 dB  error(-0.235 dB)
 585    0x24,       // [071] = -35.500 dB  ->  AKM(0x24) = -35.750 dB  error(-0.250 dB)
 586    0x24,       // [072] = -36.000 dB  ->  AKM(0x24) = -35.750 dB  error(+0.250 dB)
 587    0x23,       // [073] = -36.500 dB  ->  AKM(0x23) = -36.297 dB  error(+0.203 dB)
 588    0x22,       // [074] = -37.000 dB  ->  AKM(0x22) = -36.881 dB  error(+0.119 dB)
 589    0x21,       // [075] = -37.500 dB  ->  AKM(0x21) = -37.508 dB  error(-0.008 dB)
 590    0x20,       // [076] = -38.000 dB  ->  AKM(0x20) = -38.183 dB  error(-0.183 dB)
 591    0x1f,       // [077] = -38.500 dB  ->  AKM(0x1f) = -38.726 dB  error(-0.226 dB)
 592    0x1e,       // [078] = -39.000 dB  ->  AKM(0x1e) = -39.108 dB  error(-0.108 dB)
 593    0x1d,       // [079] = -39.500 dB  ->  AKM(0x1d) = -39.507 dB  error(-0.007 dB)
 594    0x1c,       // [080] = -40.000 dB  ->  AKM(0x1c) = -39.926 dB  error(+0.074 dB)
 595    0x1b,       // [081] = -40.500 dB  ->  AKM(0x1b) = -40.366 dB  error(+0.134 dB)
 596    0x1a,       // [082] = -41.000 dB  ->  AKM(0x1a) = -40.829 dB  error(+0.171 dB)
 597    0x19,       // [083] = -41.500 dB  ->  AKM(0x19) = -41.318 dB  error(+0.182 dB)
 598    0x18,       // [084] = -42.000 dB  ->  AKM(0x18) = -41.837 dB  error(+0.163 dB)
 599    0x17,       // [085] = -42.500 dB  ->  AKM(0x17) = -42.389 dB  error(+0.111 dB)
 600    0x16,       // [086] = -43.000 dB  ->  AKM(0x16) = -42.978 dB  error(+0.022 dB)
 601    0x15,       // [087] = -43.500 dB  ->  AKM(0x15) = -43.610 dB  error(-0.110 dB)
 602    0x14,       // [088] = -44.000 dB  ->  AKM(0x14) = -44.291 dB  error(-0.291 dB)
 603    0x14,       // [089] = -44.500 dB  ->  AKM(0x14) = -44.291 dB  error(+0.209 dB)
 604    0x13,       // [090] = -45.000 dB  ->  AKM(0x13) = -45.031 dB  error(-0.031 dB)
 605    0x12,       // [091] = -45.500 dB  ->  AKM(0x12) = -45.840 dB  error(-0.340 dB)
 606    0x12,       // [092] = -46.000 dB  ->  AKM(0x12) = -45.840 dB  error(+0.160 dB)
 607    0x11,       // [093] = -46.500 dB  ->  AKM(0x11) = -46.731 dB  error(-0.231 dB)
 608    0x11,       // [094] = -47.000 dB  ->  AKM(0x11) = -46.731 dB  error(+0.269 dB)
 609    0x10,       // [095] = -47.500 dB  ->  AKM(0x10) = -47.725 dB  error(-0.225 dB)
 610    0x10,       // [096] = -48.000 dB  ->  AKM(0x10) = -47.725 dB  error(+0.275 dB)
 611    0x0f,       // [097] = -48.500 dB  ->  AKM(0x0f) = -48.553 dB  error(-0.053 dB)
 612    0x0e,       // [098] = -49.000 dB  ->  AKM(0x0e) = -49.152 dB  error(-0.152 dB)
 613    0x0d,       // [099] = -49.500 dB  ->  AKM(0x0d) = -49.796 dB  error(-0.296 dB)
 614    0x0d,       // [100] = -50.000 dB  ->  AKM(0x0d) = -49.796 dB  error(+0.204 dB)
 615    0x0c,       // [101] = -50.500 dB  ->  AKM(0x0c) = -50.491 dB  error(+0.009 dB)
 616    0x0b,       // [102] = -51.000 dB  ->  AKM(0x0b) = -51.247 dB  error(-0.247 dB)
 617    0x0b,       // [103] = -51.500 dB  ->  AKM(0x0b) = -51.247 dB  error(+0.253 dB)
 618    0x0a,       // [104] = -52.000 dB  ->  AKM(0x0a) = -52.075 dB  error(-0.075 dB)
 619    0x0a,       // [105] = -52.500 dB  ->  AKM(0x0a) = -52.075 dB  error(+0.425 dB)
 620    0x09,       // [106] = -53.000 dB  ->  AKM(0x09) = -52.990 dB  error(+0.010 dB)
 621    0x09,       // [107] = -53.500 dB  ->  AKM(0x09) = -52.990 dB  error(+0.510 dB)
 622    0x08,       // [108] = -54.000 dB  ->  AKM(0x08) = -54.013 dB  error(-0.013 dB)
 623    0x08,       // [109] = -54.500 dB  ->  AKM(0x08) = -54.013 dB  error(+0.487 dB)
 624    0x07,       // [110] = -55.000 dB  ->  AKM(0x07) = -55.173 dB  error(-0.173 dB)
 625    0x07,       // [111] = -55.500 dB  ->  AKM(0x07) = -55.173 dB  error(+0.327 dB)
 626    0x06,       // [112] = -56.000 dB  ->  AKM(0x06) = -56.512 dB  error(-0.512 dB)
 627    0x06,       // [113] = -56.500 dB  ->  AKM(0x06) = -56.512 dB  error(-0.012 dB)
 628    0x06,       // [114] = -57.000 dB  ->  AKM(0x06) = -56.512 dB  error(+0.488 dB)
 629    0x05,       // [115] = -57.500 dB  ->  AKM(0x05) = -58.095 dB  error(-0.595 dB)
 630    0x05,       // [116] = -58.000 dB  ->  AKM(0x05) = -58.095 dB  error(-0.095 dB)
 631    0x05,       // [117] = -58.500 dB  ->  AKM(0x05) = -58.095 dB  error(+0.405 dB)
 632    0x05,       // [118] = -59.000 dB  ->  AKM(0x05) = -58.095 dB  error(+0.905 dB)
 633    0x04,       // [119] = -59.500 dB  ->  AKM(0x04) = -60.034 dB  error(-0.534 dB)
 634    0x04,       // [120] = -60.000 dB  ->  AKM(0x04) = -60.034 dB  error(-0.034 dB)
 635    0x04,       // [121] = -60.500 dB  ->  AKM(0x04) = -60.034 dB  error(+0.466 dB)
 636    0x04,       // [122] = -61.000 dB  ->  AKM(0x04) = -60.034 dB  error(+0.966 dB)
 637    0x03,       // [123] = -61.500 dB  ->  AKM(0x03) = -62.532 dB  error(-1.032 dB)
 638    0x03,       // [124] = -62.000 dB  ->  AKM(0x03) = -62.532 dB  error(-0.532 dB)
 639    0x03,       // [125] = -62.500 dB  ->  AKM(0x03) = -62.532 dB  error(-0.032 dB)
 640    0x03,       // [126] = -63.000 dB  ->  AKM(0x03) = -62.532 dB  error(+0.468 dB)
 641    0x03,       // [127] = -63.500 dB  ->  AKM(0x03) = -62.532 dB  error(+0.968 dB)
 642    0x03,       // [128] = -64.000 dB  ->  AKM(0x03) = -62.532 dB  error(+1.468 dB)
 643    0x02,       // [129] = -64.500 dB  ->  AKM(0x02) = -66.054 dB  error(-1.554 dB)
 644    0x02,       // [130] = -65.000 dB  ->  AKM(0x02) = -66.054 dB  error(-1.054 dB)
 645    0x02,       // [131] = -65.500 dB  ->  AKM(0x02) = -66.054 dB  error(-0.554 dB)
 646    0x02,       // [132] = -66.000 dB  ->  AKM(0x02) = -66.054 dB  error(-0.054 dB)
 647    0x02,       // [133] = -66.500 dB  ->  AKM(0x02) = -66.054 dB  error(+0.446 dB)
 648    0x02,       // [134] = -67.000 dB  ->  AKM(0x02) = -66.054 dB  error(+0.946 dB)
 649    0x02,       // [135] = -67.500 dB  ->  AKM(0x02) = -66.054 dB  error(+1.446 dB)
 650    0x02,       // [136] = -68.000 dB  ->  AKM(0x02) = -66.054 dB  error(+1.946 dB)
 651    0x02,       // [137] = -68.500 dB  ->  AKM(0x02) = -66.054 dB  error(+2.446 dB)
 652    0x02,       // [138] = -69.000 dB  ->  AKM(0x02) = -66.054 dB  error(+2.946 dB)
 653    0x01,       // [139] = -69.500 dB  ->  AKM(0x01) = -72.075 dB  error(-2.575 dB)
 654    0x01,       // [140] = -70.000 dB  ->  AKM(0x01) = -72.075 dB  error(-2.075 dB)
 655    0x01,       // [141] = -70.500 dB  ->  AKM(0x01) = -72.075 dB  error(-1.575 dB)
 656    0x01,       // [142] = -71.000 dB  ->  AKM(0x01) = -72.075 dB  error(-1.075 dB)
 657    0x01,       // [143] = -71.500 dB  ->  AKM(0x01) = -72.075 dB  error(-0.575 dB)
 658    0x01,       // [144] = -72.000 dB  ->  AKM(0x01) = -72.075 dB  error(-0.075 dB)
 659    0x01,       // [145] = -72.500 dB  ->  AKM(0x01) = -72.075 dB  error(+0.425 dB)
 660    0x01,       // [146] = -73.000 dB  ->  AKM(0x01) = -72.075 dB  error(+0.925 dB)
 661    0x00};      // [147] = -73.500 dB  ->  AKM(0x00) =  mute       error(+infini)
 662
 663/*
 664 * pseudo-codec write entry
 665 */
 666static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data)
 667{
 668        unsigned int val;
 669
 670        if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
 671                vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
 672                return;
 673        }
 674
 675        /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need
 676           a look up table, as there is no linear matching between the driver codec values
 677           and the real dBu value
 678        */
 679        snd_assert(data < sizeof(vx2_akm_gains_lut), return);
 680
 681        switch (reg) {
 682        case XX_CODEC_LEVEL_LEFT_REGISTER:
 683                val = AKM_CODEC_LEFT_LEVEL_CMD;
 684                break;
 685        case XX_CODEC_LEVEL_RIGHT_REGISTER:
 686                val = AKM_CODEC_RIGHT_LEVEL_CMD;
 687                break;
 688        default:
 689                snd_BUG();
 690                return;
 691        }
 692        val |= vx2_akm_gains_lut[data];
 693
 694        vx2_write_codec_reg(chip, val);
 695}
 696
 697
 698/*
 699 * write codec bit for old VX222 board
 700 */
 701static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data)
 702{
 703        int i;
 704
 705        /* activate access to codec registers */
 706        vx_inl(chip, HIFREQ);
 707
 708        for (i = 0; i < 24; i++, data <<= 1)
 709                vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
 710
 711        /* Terminate access to codec registers */
 712        vx_inl(chip, RUER);
 713}
 714
 715
 716/*
 717 * reset codec bit
 718 */
 719static void vx2_reset_codec(struct vx_core *_chip)
 720{
 721        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 722
 723        /* Set the reset CODEC bit to 0. */
 724        vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
 725        vx_inl(chip, CDSP);
 726        msleep(10);
 727        /* Set the reset CODEC bit to 1. */
 728        chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
 729        vx_outl(chip, CDSP, chip->regCDSP);
 730        vx_inl(chip, CDSP);
 731        if (_chip->type == VX_TYPE_BOARD) {
 732                msleep(1);
 733                return;
 734        }
 735
 736        msleep(5);  /* additionnel wait time for AKM's */
 737
 738        vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
 739        
 740        vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */
 741        vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */
 742        vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */
 743
 744        if (_chip->type == VX_TYPE_MIC) {
 745                /* set up the micro input selector */
 746                chip->regSELMIC =  MICRO_SELECT_INPUT_NORM |
 747                        MICRO_SELECT_PREAMPLI_G_0 |
 748                        MICRO_SELECT_NOISE_T_52DB;
 749
 750                /* reset phantom power supply */
 751                chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
 752
 753                vx_outl(_chip, SELMIC, chip->regSELMIC);
 754        }
 755}
 756
 757
 758/*
 759 * change the audio source
 760 */
 761static void vx2_change_audio_source(struct vx_core *_chip, int src)
 762{
 763        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 764
 765        switch (src) {
 766        case VX_AUDIO_SRC_DIGITAL:
 767                chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
 768                break;
 769        default:
 770                chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
 771                break;
 772        }
 773        vx_outl(chip, CFG, chip->regCFG);
 774}
 775
 776
 777/*
 778 * set the clock source
 779 */
 780static void vx2_set_clock_source(struct vx_core *_chip, int source)
 781{
 782        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 783
 784        if (source == INTERNAL_QUARTZ)
 785                chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
 786        else
 787                chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
 788        vx_outl(chip, CFG, chip->regCFG);
 789}
 790
 791/*
 792 * reset the board
 793 */
 794static void vx2_reset_board(struct vx_core *_chip, int cold_reset)
 795{
 796        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 797
 798        /* initialize the register values */
 799        chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
 800        chip->regCFG = 0;
 801}
 802
 803
 804
 805/*
 806 * input level controls for VX222 Mic
 807 */
 808
 809/* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318),
 810 * 318 = 210 + 36 + 36 + 36   (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli)
 811 * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset !
 812 */
 813#define V2_MICRO_LEVEL_RANGE        (318 - 255)
 814
 815static void vx2_set_input_level(struct snd_vx222 *chip)
 816{
 817        int i, miclevel, preamp;
 818        unsigned int data;
 819
 820        miclevel = chip->mic_level;
 821        miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */
 822        preamp = 0;
 823        while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */
 824                preamp++;       /* raise pre ampli + 18dB */
 825                miclevel -= (18 * 2);   /* lower level 18 dB (*2 because of 0.5 dB steps !) */
 826        }
 827        snd_assert(preamp < 4, return);
 828
 829        /* set pre-amp level */
 830        chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
 831        chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
 832        vx_outl(chip, SELMIC, chip->regSELMIC);
 833
 834        data = (unsigned int)miclevel << 16 |
 835                (unsigned int)chip->input_level[1] << 8 |
 836                (unsigned int)chip->input_level[0];
 837        vx_inl(chip, DATA); /* Activate input level programming */
 838
 839        /* We have to send 32 bits (4 x 8 bits) */
 840        for (i = 0; i < 32; i++, data <<= 1)
 841                vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
 842
 843        vx_inl(chip, RUER); /* Terminate input level programming */
 844}
 845
 846
 847#define MIC_LEVEL_MAX   0xff
 848
 849static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0);
 850
 851/*
 852 * controls API for input levels
 853 */
 854
 855/* input levels */
 856static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
 857{
 858        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 859        uinfo->count = 2;
 860        uinfo->value.integer.min = 0;
 861        uinfo->value.integer.max = MIC_LEVEL_MAX;
 862        return 0;
 863}
 864
 865static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
 866{
 867        struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
 868        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 869        mutex_lock(&_chip->mixer_mutex);
 870        ucontrol->value.integer.value[0] = chip->input_level[0];
 871        ucontrol->value.integer.value[1] = chip->input_level[1];
 872        mutex_unlock(&_chip->mixer_mutex);
 873        return 0;
 874}
 875
 876static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
 877{
 878        struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
 879        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 880        mutex_lock(&_chip->mixer_mutex);
 881        if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
 882            chip->input_level[1] != ucontrol->value.integer.value[1]) {
 883                chip->input_level[0] = ucontrol->value.integer.value[0];
 884                chip->input_level[1] = ucontrol->value.integer.value[1];
 885                vx2_set_input_level(chip);
 886                mutex_unlock(&_chip->mixer_mutex);
 887                return 1;
 888        }
 889        mutex_unlock(&_chip->mixer_mutex);
 890        return 0;
 891}
 892
 893/* mic level */
 894static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
 895{
 896        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 897        uinfo->count = 1;
 898        uinfo->value.integer.min = 0;
 899        uinfo->value.integer.max = MIC_LEVEL_MAX;
 900        return 0;
 901}
 902
 903static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
 904{
 905        struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
 906        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 907        ucontrol->value.integer.value[0] = chip->mic_level;
 908        return 0;
 909}
 910
 911static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
 912{
 913        struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
 914        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 915        mutex_lock(&_chip->mixer_mutex);
 916        if (chip->mic_level != ucontrol->value.integer.value[0]) {
 917                chip->mic_level = ucontrol->value.integer.value[0];
 918                vx2_set_input_level(chip);
 919                mutex_unlock(&_chip->mixer_mutex);
 920                return 1;
 921        }
 922        mutex_unlock(&_chip->mixer_mutex);
 923        return 0;
 924}
 925
 926static struct snd_kcontrol_new vx_control_input_level = {
 927        .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
 928        .access =       (SNDRV_CTL_ELEM_ACCESS_READWRITE |
 929                         SNDRV_CTL_ELEM_ACCESS_TLV_READ),
 930        .name =         "Capture Volume",
 931        .info =         vx_input_level_info,
 932        .get =          vx_input_level_get,
 933        .put =          vx_input_level_put,
 934        .tlv = { .p = db_scale_mic },
 935};
 936
 937static struct snd_kcontrol_new vx_control_mic_level = {
 938        .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
 939        .access =       (SNDRV_CTL_ELEM_ACCESS_READWRITE |
 940                         SNDRV_CTL_ELEM_ACCESS_TLV_READ),
 941        .name =         "Mic Capture Volume",
 942        .info =         vx_mic_level_info,
 943        .get =          vx_mic_level_get,
 944        .put =          vx_mic_level_put,
 945        .tlv = { .p = db_scale_mic },
 946};
 947
 948/*
 949 * FIXME: compressor/limiter implementation is missing yet...
 950 */
 951
 952static int vx2_add_mic_controls(struct vx_core *_chip)
 953{
 954        struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 955        int err;
 956
 957        if (_chip->type != VX_TYPE_MIC)
 958                return 0;
 959
 960        /* mute input levels */
 961        chip->input_level[0] = chip->input_level[1] = 0;
 962        chip->mic_level = 0;
 963        vx2_set_input_level(chip);
 964
 965        /* controls */
 966        if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0)
 967                return err;
 968        if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0)
 969                return err;
 970
 971        return 0;
 972}
 973
 974
 975/*
 976 * callbacks
 977 */
 978struct snd_vx_ops vx222_ops = {
 979        .in8 = vx2_inb,
 980        .in32 = vx2_inl,
 981        .out8 = vx2_outb,
 982        .out32 = vx2_outl,
 983        .test_and_ack = vx2_test_and_ack,
 984        .validate_irq = vx2_validate_irq,
 985        .akm_write = vx2_write_akm,
 986        .reset_codec = vx2_reset_codec,
 987        .change_audio_source = vx2_change_audio_source,
 988        .set_clock_source = vx2_set_clock_source,
 989        .load_dsp = vx2_load_dsp,
 990        .reset_dsp = vx2_reset_dsp,
 991        .reset_board = vx2_reset_board,
 992        .dma_write = vx2_dma_write,
 993        .dma_read = vx2_dma_read,
 994        .add_controls = vx2_add_mic_controls,
 995};
 996
 997/* for old VX222 board */
 998struct snd_vx_ops vx222_old_ops = {
 999        .in8 = vx2_inb,
1000        .in32 = vx2_inl,

1001        .out8 = vx2_outb,
1002        .out32 = vx2_outl,
1003        .test_and_ack = vx2_test_and_ack,
1004        .validate_irq = vx2_validate_irq,
1005        .write_codec = vx2_old_write_codec_bit,
1006        .reset_codec = vx2_reset_codec,
1007        .change_audio_source = vx2_change_audio_source,
1008        .set_clock_source = vx2_set_clock_source,
1009        .load_dsp = vx2_load_dsp,
1010        .reset_dsp = vx2_reset_dsp,
1011        .reset_board = vx2_reset_board,
1012        .dma_write = vx2_dma_write,
1013        .dma_read = vx2_dma_read,
1014};
1015
1016