LXR linux/sound/soc/at91/eti_b1

   1/*
   2 * eti_b1_wm8731  --  SoC audio for AT91RM9200-based Endrelia ETI_B1 board.
   3 *
   4 * Author:      Frank Mandarino <fmandarino@endrelia.com>
   5 *              Endrelia Technologies Inc.
   6 * Created:     Mar 29, 2006
   7 *
   8 * Based on corgi.c by:
   9 *
  10 * Copyright 2005 Wolfson Microelectronics PLC.
  11 * Copyright 2005 Openedhand Ltd.
  12 *
  13 * Authors: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
  14 *          Richard Purdie <richard@openedhand.com>
  15 *
  16 *  This program is free software; you can redistribute  it and/or modify it
  17 *  under  the terms of  the GNU General  Public License as published by the
  18 *  Free Software Foundation;  either version 2 of the  License, or (at your
  19 *  option) any later version.
  20 *
  21 */
  22
  23#include <linux/module.h>
  24#include <linux/moduleparam.h>
  25#include <linux/version.h>
  26#include <linux/kernel.h>
  27#include <linux/clk.h>
  28#include <linux/timer.h>
  29#include <linux/interrupt.h>
  30#include <linux/platform_device.h>
  31#include <sound/driver.h>
  32#include <sound/core.h>
  33#include <sound/pcm.h>
  34#include <sound/soc.h>
  35#include <sound/soc-dapm.h>
  36
  37#include <asm/arch/hardware.h>
  38#include <asm/arch/at91_pio.h>
  39#include <asm/arch/gpio.h>
  40
  41#include "../codecs/wm8731.h"
  42#include "at91-pcm.h"
  43#include "at91-ssc.h"
  44
  45#if 0
  46#define DBG(x...)       printk(KERN_INFO "eti_b1_wm8731: " x)
  47#else
  48#define DBG(x...)
  49#endif
  50
  51#define AT91_PIO_TF1    (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
  52#define AT91_PIO_TK1    (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
  53#define AT91_PIO_TD1    (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
  54#define AT91_PIO_RD1    (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
  55#define AT91_PIO_RK1    (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
  56#define AT91_PIO_RF1    (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
  57
  58static struct clk *pck1_clk;
  59static struct clk *pllb_clk;
  60
  61
  62static int eti_b1_startup(struct snd_pcm_substream *substream)
  63{
  64        struct snd_soc_pcm_runtime *rtd = substream->private_data;
  65        struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
  66        struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  67        int ret;
  68
  69        /* cpu clock is the AT91 master clock sent to the SSC */
  70        ret = cpu_dai->dai_ops.set_sysclk(cpu_dai, AT91_SYSCLK_MCK,
  71                60000000, SND_SOC_CLOCK_IN);
  72        if (ret < 0)
  73                return ret;
  74
  75        /* codec system clock is supplied by PCK1, set to 12MHz */
  76        ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8731_SYSCLK,
  77                12000000, SND_SOC_CLOCK_IN);
  78        if (ret < 0)
  79                return ret;
  80
  81        /* Start PCK1 clock. */
  82        clk_enable(pck1_clk);
  83        DBG("pck1 started\n");
  84
  85        return 0;
  86}
  87
  88static void eti_b1_shutdown(struct snd_pcm_substream *substream)
  89{
  90        /* Stop PCK1 clock. */
  91        clk_disable(pck1_clk);
  92        DBG("pck1 stopped\n");
  93}
  94
  95static int eti_b1_hw_params(struct snd_pcm_substream *substream,
  96        struct snd_pcm_hw_params *params)
  97{
  98        struct snd_soc_pcm_runtime *rtd = substream->private_data;
  99        struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
 100        struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 101        int ret;
 102
 103#ifdef CONFIG_SND_AT91_SOC_ETI_SLAVE
 104        unsigned int rate;
 105        int cmr_div, period;
 106
 107        /* set codec DAI configuration */
 108        ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
 109                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
 110        if (ret < 0)
 111                return ret;
 112
 113        /* set cpu DAI configuration */
 114        ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
 115                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
 116        if (ret < 0)
 117                return ret;
 118
 119        /*
 120         * The SSC clock dividers depend on the sample rate.  The CMR.DIV
 121         * field divides the system master clock MCK to drive the SSC TK
 122         * signal which provides the codec BCLK.  The TCMR.PERIOD and
 123         * RCMR.PERIOD fields further divide the BCLK signal to drive
 124         * the SSC TF and RF signals which provide the codec DACLRC and
 125         * ADCLRC clocks.
 126         *
 127         * The dividers were determined through trial and error, where a
 128         * CMR.DIV value is chosen such that the resulting BCLK value is
 129         * divisible, or almost divisible, by (2 * sample rate), and then
 130         * the TCMR.PERIOD or RCMR.PERIOD is BCLK / (2 * sample rate) - 1.
 131         */
 132        rate = params_rate(params);
 133
 134        switch (rate) {
 135        case 8000:
 136                cmr_div = 25;   /* BCLK = 60MHz/(2*25) = 1.2MHz */
 137                period = 74;    /* LRC = BCLK/(2*(74+1)) = 8000Hz */
 138                break;
 139        case 32000:
 140                cmr_div = 7;    /* BCLK = 60MHz/(2*7) ~= 4.28571428MHz */
 141                period = 66;    /* LRC = BCLK/(2*(66+1)) = 31982.942Hz */
 142                break;
 143        case 48000:
 144                cmr_div = 13;   /* BCLK = 60MHz/(2*13) ~= 2.3076923MHz */
 145                period = 23;    /* LRC = BCLK/(2*(23+1)) = 48076.923Hz */
 146                break;
 147        default:
 148                printk(KERN_WARNING "unsupported rate %d on ETI-B1 board\n", rate);
 149                return -EINVAL;
 150        }
 151
 152        /* set the MCK divider for BCLK */
 153        ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, AT91SSC_CMR_DIV, cmr_div);
 154        if (ret < 0)
 155                return ret;
 156
 157        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 158                /* set the BCLK divider for DACLRC */
 159                ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai,
 160                                                AT91SSC_TCMR_PERIOD, period);
 161        } else {
 162                /* set the BCLK divider for ADCLRC */
 163                ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai,
 164                                                AT91SSC_RCMR_PERIOD, period);
 165        }
 166        if (ret < 0)
 167                return ret;
 168
 169#else /* CONFIG_SND_AT91_SOC_ETI_SLAVE */
 170        /*
 171         * Codec in Master Mode.
 172         */
 173
 174        /* set codec DAI configuration */
 175        ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
 176                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
 177        if (ret < 0)
 178                return ret;
 179
 180        /* set cpu DAI configuration */
 181        ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
 182                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
 183        if (ret < 0)
 184                return ret;
 185
 186#endif /* CONFIG_SND_AT91_SOC_ETI_SLAVE */
 187
 188        return 0;
 189}
 190
 191static struct snd_soc_ops eti_b1_ops = {
 192        .startup = eti_b1_startup,
 193        .hw_params = eti_b1_hw_params,
 194        .shutdown = eti_b1_shutdown,
 195};
 196
 197
 198static const struct snd_soc_dapm_widget eti_b1_dapm_widgets[] = {
 199        SND_SOC_DAPM_MIC("Int Mic", NULL),
 200        SND_SOC_DAPM_SPK("Ext Spk", NULL),
 201};
 202
 203static const char *intercon[][3] = {
 204
 205        /* speaker connected to LHPOUT */
 206        {"Ext Spk", NULL, "LHPOUT"},
 207
 208        /* mic is connected to Mic Jack, with WM8731 Mic Bias */
 209        {"MICIN", NULL, "Mic Bias"},
 210        {"Mic Bias", NULL, "Int Mic"},
 211
 212        /* terminator */
 213        {NULL, NULL, NULL},
 214};
 215
 216/*
 217 * Logic for a wm8731 as connected on a Endrelia ETI-B1 board.
 218 */
 219static int eti_b1_wm8731_init(struct snd_soc_codec *codec)
 220{
 221        int i;
 222
 223        DBG("eti_b1_wm8731_init() called\n");
 224
 225        /* Add specific widgets */
 226        for(i = 0; i < ARRAY_SIZE(eti_b1_dapm_widgets); i++) {
 227                snd_soc_dapm_new_control(codec, &eti_b1_dapm_widgets[i]);
 228        }
 229
 230        /* Set up specific audio path interconnects */
 231        for(i = 0; intercon[i][0] != NULL; i++) {
 232                snd_soc_dapm_connect_input(codec, intercon[i][0],
 233                        intercon[i][1], intercon[i][2]);
 234        }
 235
 236        /* not connected */
 237        snd_soc_dapm_set_endpoint(codec, "RLINEIN", 0);
 238        snd_soc_dapm_set_endpoint(codec, "LLINEIN", 0);
 239
 240        /* always connected */
 241        snd_soc_dapm_set_endpoint(codec, "Int Mic", 1);
 242        snd_soc_dapm_set_endpoint(codec, "Ext Spk", 1);
 243
 244        snd_soc_dapm_sync_endpoints(codec);
 245
 246        return 0;
 247}
 248
 249static struct snd_soc_dai_link eti_b1_dai = {
 250        .name = "WM8731",
 251        .stream_name = "WM8731 PCM",
 252        .cpu_dai = &at91_ssc_dai[1],
 253        .codec_dai = &wm8731_dai,
 254        .init = eti_b1_wm8731_init,
 255        .ops = &eti_b1_ops,
 256};
 257
 258static struct snd_soc_machine snd_soc_machine_eti_b1 = {
 259        .name = "ETI_B1_WM8731",
 260        .dai_link = &eti_b1_dai,
 261        .num_links = 1,
 262};
 263
 264static struct wm8731_setup_data eti_b1_wm8731_setup = {
 265        .i2c_address = 0x1a,
 266};
 267
 268static struct snd_soc_device eti_b1_snd_devdata = {
 269        .machine = &snd_soc_machine_eti_b1,
 270        .platform = &at91_soc_platform,
 271        .codec_dev = &soc_codec_dev_wm8731,
 272        .codec_data = &eti_b1_wm8731_setup,
 273};
 274
 275static struct platform_device *eti_b1_snd_device;
 276
 277static int __init eti_b1_init(void)
 278{
 279        int ret;
 280        u32 ssc_pio_lines;
 281        struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
 282
 283        if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
 284                DBG("SSC1 memory region is busy\n");
 285                return -EBUSY;
 286        }
 287
 288        ssc->base = ioremap(AT91RM9200_BASE_SSC1, SZ_16K);
 289        if (!ssc->base) {
 290                DBG("SSC1 memory ioremap failed\n");
 291                ret = -ENOMEM;
 292                goto fail_release_mem;
 293        }
 294
 295        ssc->pid = AT91RM9200_ID_SSC1;
 296
 297        eti_b1_snd_device = platform_device_alloc("soc-audio", -1);
 298        if (!eti_b1_snd_device) {
 299                DBG("platform device allocation failed\n");
 300                ret = -ENOMEM;
 301                goto fail_io_unmap;
 302        }
 303
 304        platform_set_drvdata(eti_b1_snd_device, &eti_b1_snd_devdata);
 305        eti_b1_snd_devdata.dev = &eti_b1_snd_device->dev;
 306
 307        ret = platform_device_add(eti_b1_snd_device);
 308        if (ret) {
 309                DBG("platform device add failed\n");
 310                platform_device_put(eti_b1_snd_device);
 311                goto fail_io_unmap;
 312        }
 313
 314        ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
 315                        | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
 316
 317        /* Reset all PIO registers and assign lines to peripheral A */
 318        at91_sys_write(AT91_PIOB + PIO_PDR,  ssc_pio_lines);
 319        at91_sys_write(AT91_PIOB + PIO_ODR,  ssc_pio_lines);
 320        at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
 321        at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
 322        at91_sys_write(AT91_PIOB + PIO_IDR,  ssc_pio_lines);
 323        at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
 324        at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
 325        at91_sys_write(AT91_PIOB + PIO_ASR,  ssc_pio_lines);
 326        at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
 327
 328        /*
 329         * Set PCK1 parent to PLLB and its rate to 12 Mhz.
 330         */
 331        pllb_clk = clk_get(NULL, "pllb");
 332        pck1_clk = clk_get(NULL, "pck1");
 333
 334        clk_set_parent(pck1_clk, pllb_clk);
 335        clk_set_rate(pck1_clk, 12000000);
 336
 337        DBG("MCLK rate %luHz\n", clk_get_rate(pck1_clk));
 338
 339        /* assign the GPIO pin to PCK1 */
 340        at91_set_B_periph(AT91_PIN_PA24, 0);
 341
 342#ifdef CONFIG_SND_AT91_SOC_ETI_SLAVE
 343        printk(KERN_INFO "eti_b1_wm8731: Codec in Slave Mode\n");
 344#else
 345        printk(KERN_INFO "eti_b1_wm8731: Codec in Master Mode\n");
 346#endif
 347        return ret;
 348
 349fail_io_unmap:
 350        iounmap(ssc->base);
 351fail_release_mem:
 352        release_mem_region(AT91RM9200_BASE_SSC1, SZ_16K);
 353        return ret;
 354}
 355
 356static void __exit eti_b1_exit(void)
 357{
 358        struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
 359
 360        clk_put(pck1_clk);
 361        clk_put(pllb_clk);
 362
 363        platform_device_unregister(eti_b1_snd_device);
 364
 365        iounmap(ssc->base);
 366        release_mem_region(AT91RM9200_BASE_SSC1, SZ_16K);
 367}
 368
 369module_init(eti_b1_init);
 370module_exit(eti_b1_exit);
 371
 372/* Module information */
 373MODULE_AUTHOR("Frank Mandarino <fmandarino@endrelia.com>");
 374MODULE_DESCRIPTION("ALSA SoC ETI-B1-WM8731");
 375MODULE_LICENSE("GPL");
 376