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30#include <linux/errno.h>
31#include <linux/module.h>
32#include <linux/sched.h>
33#include <linux/kernel.h>
34#include <linux/param.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/delay.h>
38#include <linux/ioport.h>
39#include <linux/irq.h>
40#include <linux/interrupt.h>
41#include <linux/init.h>
42#include <linux/bcd.h>
43#include <linux/profile.h>
44
45#include <asm/uaccess.h>
46#include <asm/io.h>
47#include <asm/hwrpb.h>
48#include <asm/8253pit.h>
49#include <asm/rtc.h>
50
51#include <linux/mc146818rtc.h>
52#include <linux/time.h>
53#include <linux/timex.h>
54
55#include "proto.h"
56#include "irq_impl.h"
57
58static int set_rtc_mmss(unsigned long);
59
60DEFINE_SPINLOCK(rtc_lock);
61EXPORT_SYMBOL(rtc_lock);
62
63#define TICK_SIZE (tick_nsec / 1000)
64
65
66
67
68
69
70#define FIX_SHIFT 48
71
72
73static struct {
74
75 __u32 last_time;
76
77 unsigned long scaled_ticks_per_cycle;
78
79 time_t last_rtc_update;
80
81 unsigned long partial_tick;
82} state;
83
84unsigned long est_cycle_freq;
85
86
87static inline __u32 rpcc(void)
88{
89 __u32 result;
90 asm volatile ("rpcc %0" : "=r"(result));
91 return result;
92}
93
94
95
96
97
98irqreturn_t timer_interrupt(int irq, void *dev)
99{
100 unsigned long delta;
101 __u32 now;
102 long nticks;
103
104#ifndef CONFIG_SMP
105
106 profile_tick(CPU_PROFILING);
107#endif
108
109 write_seqlock(&xtime_lock);
110
111
112
113
114
115
116 now = rpcc();
117 delta = now - state.last_time;
118 state.last_time = now;
119 delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
120 state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
121 nticks = delta >> FIX_SHIFT;
122
123 if (nticks)
124 do_timer(nticks);
125
126
127
128
129
130
131 if (ntp_synced()
132 && xtime.tv_sec > state.last_rtc_update + 660
133 && xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2
134 && xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) {
135 int tmp = set_rtc_mmss(xtime.tv_sec);
136 state.last_rtc_update = xtime.tv_sec - (tmp ? 600 : 0);
137 }
138
139 write_sequnlock(&xtime_lock);
140
141#ifndef CONFIG_SMP
142 while (nticks--)
143 update_process_times(user_mode(get_irq_regs()));
144#endif
145
146 return IRQ_HANDLED;
147}
148
149void __init
150common_init_rtc(void)
151{
152 unsigned char x;
153
154
155 x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
156
157
158 if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
159 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
160 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
161 }
162
163
164 x = CMOS_READ(RTC_CONTROL);
165 if (!(x & RTC_PIE)) {
166 printk("Turning on RTC interrupts.\n");
167 x |= RTC_PIE;
168 x &= ~(RTC_AIE | RTC_UIE);
169 CMOS_WRITE(x, RTC_CONTROL);
170 }
171 (void) CMOS_READ(RTC_INTR_FLAGS);
172
173 outb(0x36, 0x43);
174 outb(0x00, 0x40);
175 outb(0x00, 0x40);
176
177 outb(0xb6, 0x43);
178 outb(0x31, 0x42);
179 outb(0x13, 0x42);
180
181 init_rtc_irq();
182}
183
184unsigned int common_get_rtc_time(struct rtc_time *time)
185{
186 return __get_rtc_time(time);
187}
188
189int common_set_rtc_time(struct rtc_time *time)
190{
191 return __set_rtc_time(time);
192}
193
194
195
196
197
198
199
200static unsigned long __init
201validate_cc_value(unsigned long cc)
202{
203 static struct bounds {
204 unsigned int min, max;
205 } cpu_hz[] __initdata = {
206 [EV3_CPU] = { 50000000, 200000000 },
207 [EV4_CPU] = { 100000000, 300000000 },
208 [LCA4_CPU] = { 100000000, 300000000 },
209 [EV45_CPU] = { 200000000, 300000000 },
210 [EV5_CPU] = { 250000000, 433000000 },
211 [EV56_CPU] = { 333000000, 667000000 },
212 [PCA56_CPU] = { 400000000, 600000000 },
213 [PCA57_CPU] = { 500000000, 600000000 },
214 [EV6_CPU] = { 466000000, 600000000 },
215 [EV67_CPU] = { 600000000, 750000000 },
216 [EV68AL_CPU] = { 750000000, 940000000 },
217 [EV68CB_CPU] = { 1000000000, 1333333333 },
218
219 [EV68CX_CPU] = { 1000000000, 1700000000 },
220 [EV69_CPU] = { 1000000000, 1700000000 },
221 [EV7_CPU] = { 800000000, 1400000000 },
222 [EV79_CPU] = { 1000000000, 2000000000 },
223 };
224
225
226 const unsigned int deviation = 10000000;
227
228 struct percpu_struct *cpu;
229 unsigned int index;
230
231 cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
232 index = cpu->type & 0xffffffff;
233
234
235 if (index >= ARRAY_SIZE(cpu_hz))
236 return cc;
237
238
239 if (cpu_hz[index].max == 0)
240 return cc;
241
242 if (cc < cpu_hz[index].min - deviation
243 || cc > cpu_hz[index].max + deviation)
244 return 0;
245
246 return cc;
247}
248
249
250
251
252
253
254
255#define CALIBRATE_LATCH 0xffff
256#define TIMEOUT_COUNT 0x100000
257
258static unsigned long __init
259calibrate_cc_with_pit(void)
260{
261 int cc, count = 0;
262
263
264 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
265
266
267
268
269
270
271
272
273 outb(0xb0, 0x43);
274 outb(CALIBRATE_LATCH & 0xff, 0x42);
275 outb(CALIBRATE_LATCH >> 8, 0x42);
276
277 cc = rpcc();
278 do {
279 count++;
280 } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
281 cc = rpcc() - cc;
282
283
284 if (count <= 1 || count == TIMEOUT_COUNT)
285 return 0;
286
287 return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
288}
289
290
291
292
293
294
295static unsigned long __init
296rpcc_after_update_in_progress(void)
297{
298 do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
299 do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
300
301 return rpcc();
302}
303
304void __init
305time_init(void)
306{
307 unsigned int year, mon, day, hour, min, sec, cc1, cc2, epoch;
308 unsigned long cycle_freq, tolerance;
309 long diff;
310
311
312 if (!est_cycle_freq)
313 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
314
315 cc1 = rpcc();
316
317
318 if (!est_cycle_freq) {
319 cc1 = rpcc_after_update_in_progress();
320 cc2 = rpcc_after_update_in_progress();
321 est_cycle_freq = validate_cc_value(cc2 - cc1);
322 cc1 = cc2;
323 }
324
325 cycle_freq = hwrpb->cycle_freq;
326 if (est_cycle_freq) {
327
328
329 tolerance = cycle_freq / 4000;
330 diff = cycle_freq - est_cycle_freq;
331 if (diff < 0)
332 diff = -diff;
333 if ((unsigned long)diff > tolerance) {
334 cycle_freq = est_cycle_freq;
335 printk("HWRPB cycle frequency bogus. "
336 "Estimated %lu Hz\n", cycle_freq);
337 } else {
338 est_cycle_freq = 0;
339 }
340 } else if (! validate_cc_value (cycle_freq)) {
341 printk("HWRPB cycle frequency bogus, "
342 "and unable to estimate a proper value!\n");
343 }
344
345
346
347
348
349 __delay(1000000);
350
351 sec = CMOS_READ(RTC_SECONDS);
352 min = CMOS_READ(RTC_MINUTES);
353 hour = CMOS_READ(RTC_HOURS);
354 day = CMOS_READ(RTC_DAY_OF_MONTH);
355 mon = CMOS_READ(RTC_MONTH);
356 year = CMOS_READ(RTC_YEAR);
357
358 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
359 sec = bcd2bin(sec);
360 min = bcd2bin(min);
361 hour = bcd2bin(hour);
362 day = bcd2bin(day);
363 mon = bcd2bin(mon);
364 year = bcd2bin(year);
365 }
366
367
368 epoch = 1900;
369 if (year < 20)
370 epoch = 2000;
371 else if (year >= 20 && year < 48)
372
373 epoch = 1980;
374 else if (year >= 48 && year < 70)
375
376 epoch = 1952;
377
378 printk(KERN_INFO "Using epoch = %d\n", epoch);
379
380 if ((year += epoch) < 1970)
381 year += 100;
382
383 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
384 xtime.tv_nsec = 0;
385
386 wall_to_monotonic.tv_sec -= xtime.tv_sec;
387 wall_to_monotonic.tv_nsec = 0;
388
389 if (HZ > (1<<16)) {
390 extern void __you_loose (void);
391 __you_loose();
392 }
393
394 state.last_time = cc1;
395 state.scaled_ticks_per_cycle
396 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
397 state.last_rtc_update = 0;
398 state.partial_tick = 0L;
399
400
401 alpha_mv.init_rtc();
402}
403
404
405
406
407
408
409
410
411u32 arch_gettimeoffset(void)
412{
413#ifdef CONFIG_SMP
414
415
416 return 0;
417#else
418 unsigned long delta_cycles, delta_usec, partial_tick;
419
420 delta_cycles = rpcc() - state.last_time;
421 partial_tick = state.partial_tick;
422
423
424
425
426
427
428
429
430
431
432
433
434
435 delta_usec = (delta_cycles * state.scaled_ticks_per_cycle
436 + partial_tick) * 15625;
437 delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
438 return delta_usec * 1000;
439#endif
440}
441
442
443
444
445
446
447
448
449
450
451
452
453
454static int
455set_rtc_mmss(unsigned long nowtime)
456{
457 int retval = 0;
458 int real_seconds, real_minutes, cmos_minutes;
459 unsigned char save_control, save_freq_select;
460
461
462 spin_lock(&rtc_lock);
463
464 save_control = CMOS_READ(RTC_CONTROL);
465 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
466
467
468 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
469 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
470
471 cmos_minutes = CMOS_READ(RTC_MINUTES);
472 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
473 cmos_minutes = bcd2bin(cmos_minutes);
474
475
476
477
478
479
480
481 real_seconds = nowtime % 60;
482 real_minutes = nowtime / 60;
483 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
484
485 real_minutes += 30;
486 }
487 real_minutes %= 60;
488
489 if (abs(real_minutes - cmos_minutes) < 30) {
490 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
491 real_seconds = bin2bcd(real_seconds);
492 real_minutes = bin2bcd(real_minutes);
493 }
494 CMOS_WRITE(real_seconds,RTC_SECONDS);
495 CMOS_WRITE(real_minutes,RTC_MINUTES);
496 } else {
497 printk(KERN_WARNING
498 "set_rtc_mmss: can't update from %d to %d\n",
499 cmos_minutes, real_minutes);
500 retval = -1;
501 }
502
503
504
505
506
507
508
509
510 CMOS_WRITE(save_control, RTC_CONTROL);
511 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
512 spin_unlock(&rtc_lock);
513
514 return retval;
515}
516