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11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/smp.h>
16#include <linux/jiffies.h>
17#include <linux/clockchips.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20
21#include <asm/smp_twd.h>
22#include <asm/hardware/gic.h>
23
24#define TWD_TIMER_LOAD 0x00
25#define TWD_TIMER_COUNTER 0x04
26#define TWD_TIMER_CONTROL 0x08
27#define TWD_TIMER_INTSTAT 0x0C
28
29#define TWD_WDOG_LOAD 0x20
30#define TWD_WDOG_COUNTER 0x24
31#define TWD_WDOG_CONTROL 0x28
32#define TWD_WDOG_INTSTAT 0x2C
33#define TWD_WDOG_RESETSTAT 0x30
34#define TWD_WDOG_DISABLE 0x34
35
36#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
37#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
38#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
39#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
40
41
42void __iomem *twd_base;
43
44static unsigned long twd_timer_rate;
45
46static void twd_set_mode(enum clock_event_mode mode,
47 struct clock_event_device *clk)
48{
49 unsigned long ctrl;
50
51 switch (mode) {
52 case CLOCK_EVT_MODE_PERIODIC:
53
54 ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
55 | TWD_TIMER_CONTROL_PERIODIC;
56 break;
57 case CLOCK_EVT_MODE_ONESHOT:
58
59 ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
60 break;
61 case CLOCK_EVT_MODE_UNUSED:
62 case CLOCK_EVT_MODE_SHUTDOWN:
63 default:
64 ctrl = 0;
65 }
66
67 __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
68}
69
70static int twd_set_next_event(unsigned long evt,
71 struct clock_event_device *unused)
72{
73 unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
74
75 ctrl |= TWD_TIMER_CONTROL_ENABLE;
76
77 __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
78 __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
79
80 return 0;
81}
82
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84
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86
87
88
89int twd_timer_ack(void)
90{
91 if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
92 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
93 return 1;
94 }
95
96 return 0;
97}
98
99static void __cpuinit twd_calibrate_rate(void)
100{
101 unsigned long load, count;
102 u64 waitjiffies;
103
104
105
106
107
108 if (twd_timer_rate == 0) {
109 printk(KERN_INFO "Calibrating local timer... ");
110
111
112 waitjiffies = get_jiffies_64() + 1;
113
114 while (get_jiffies_64() < waitjiffies)
115 udelay(10);
116
117
118 waitjiffies += 5;
119
120
121 __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
122
123
124 __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
125
126 while (get_jiffies_64() < waitjiffies)
127 udelay(10);
128
129 count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
130
131 twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
132
133 printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
134 (twd_timer_rate / 100000) % 100);
135 }
136
137 load = twd_timer_rate / HZ;
138
139 __raw_writel(load, twd_base + TWD_TIMER_LOAD);
140}
141
142
143
144
145void __cpuinit twd_timer_setup(struct clock_event_device *clk)
146{
147 unsigned long flags;
148
149 twd_calibrate_rate();
150
151 clk->name = "local_timer";
152 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
153 clk->rating = 350;
154 clk->set_mode = twd_set_mode;
155 clk->set_next_event = twd_set_next_event;
156 clk->shift = 20;
157 clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
158 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
159 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
160
161
162 local_irq_save(flags);
163 get_irq_chip(clk->irq)->unmask(clk->irq);
164 local_irq_restore(flags);
165
166 clockevents_register_device(clk);
167}
168
169#ifdef CONFIG_HOTPLUG_CPU
170
171
172
173void twd_timer_stop(void)
174{
175 __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
176}
177#endif
178