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12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/i2c-gpio.h>
18
19#include <linux/fb.h>
20#include <video/atmel_lcdc.h>
21
22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9g45.h>
25#include <mach/at91sam9g45_matrix.h>
26#include <mach/at91sam9_smc.h>
27#include <mach/at_hdmac.h>
28
29#include "generic.h"
30
31
32
33
34
35
36#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
37static u64 hdmac_dmamask = DMA_BIT_MASK(32);
38
39static struct at_dma_platform_data atdma_pdata = {
40 .nr_channels = 8,
41};
42
43static struct resource hdmac_resources[] = {
44 [0] = {
45 .start = AT91_BASE_SYS + AT91_DMA,
46 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
47 .flags = IORESOURCE_MEM,
48 },
49 [2] = {
50 .start = AT91SAM9G45_ID_DMA,
51 .end = AT91SAM9G45_ID_DMA,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56static struct platform_device at_hdmac_device = {
57 .name = "at_hdmac",
58 .id = -1,
59 .dev = {
60 .dma_mask = &hdmac_dmamask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 .platform_data = &atdma_pdata,
63 },
64 .resource = hdmac_resources,
65 .num_resources = ARRAY_SIZE(hdmac_resources),
66};
67
68void __init at91_add_device_hdmac(void)
69{
70 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
71 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
72 platform_device_register(&at_hdmac_device);
73}
74#else
75void __init at91_add_device_hdmac(void) {}
76#endif
77
78
79
80
81
82
83#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84static u64 ohci_dmamask = DMA_BIT_MASK(32);
85static struct at91_usbh_data usbh_ohci_data;
86
87static struct resource usbh_ohci_resources[] = {
88 [0] = {
89 .start = AT91SAM9G45_OHCI_BASE,
90 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = AT91SAM9G45_ID_UHPHS,
95 .end = AT91SAM9G45_ID_UHPHS,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static struct platform_device at91_usbh_ohci_device = {
101 .name = "at91_ohci",
102 .id = -1,
103 .dev = {
104 .dma_mask = &ohci_dmamask,
105 .coherent_dma_mask = DMA_BIT_MASK(32),
106 .platform_data = &usbh_ohci_data,
107 },
108 .resource = usbh_ohci_resources,
109 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
110};
111
112void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
113{
114 int i;
115
116 if (!data)
117 return;
118
119
120 for (i = 0; i < data->ports; i++) {
121 if (data->vbus_pin[i])
122 at91_set_gpio_output(data->vbus_pin[i], 0);
123 }
124
125 usbh_ohci_data = *data;
126 platform_device_register(&at91_usbh_ohci_device);
127}
128#else
129void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
130#endif
131
132
133
134
135
136
137#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
138static struct resource usba_udc_resources[] = {
139 [0] = {
140 .start = AT91SAM9G45_UDPHS_FIFO,
141 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = AT91SAM9G45_BASE_UDPHS,
146 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [2] = {
150 .start = AT91SAM9G45_ID_UDPHS,
151 .end = AT91SAM9G45_ID_UDPHS,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
157 [idx] = { \
158 .name = nam, \
159 .index = idx, \
160 .fifo_size = maxpkt, \
161 .nr_banks = maxbk, \
162 .can_dma = dma, \
163 .can_isoc = isoc, \
164 }
165
166static struct usba_ep_data usba_udc_ep[] __initdata = {
167 EP("ep0", 0, 64, 1, 0, 0),
168 EP("ep1", 1, 1024, 2, 1, 1),
169 EP("ep2", 2, 1024, 2, 1, 1),
170 EP("ep3", 3, 1024, 3, 1, 0),
171 EP("ep4", 4, 1024, 3, 1, 0),
172 EP("ep5", 5, 1024, 3, 1, 1),
173 EP("ep6", 6, 1024, 3, 1, 1),
174};
175
176#undef EP
177
178
179
180
181
182static struct {
183 struct usba_platform_data pdata;
184 struct usba_ep_data ep[7];
185} usba_udc_data;
186
187static struct platform_device at91_usba_udc_device = {
188 .name = "atmel_usba_udc",
189 .id = -1,
190 .dev = {
191 .platform_data = &usba_udc_data.pdata,
192 },
193 .resource = usba_udc_resources,
194 .num_resources = ARRAY_SIZE(usba_udc_resources),
195};
196
197void __init at91_add_device_usba(struct usba_platform_data *data)
198{
199 usba_udc_data.pdata.vbus_pin = -EINVAL;
200 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
201 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
202
203 if (data && data->vbus_pin > 0) {
204 at91_set_gpio_input(data->vbus_pin, 0);
205 at91_set_deglitch(data->vbus_pin, 1);
206 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
207 }
208
209
210
211
212 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
213 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
214
215 platform_device_register(&at91_usba_udc_device);
216}
217#else
218void __init at91_add_device_usba(struct usba_platform_data *data) {}
219#endif
220
221
222
223
224
225
226#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
227static u64 eth_dmamask = DMA_BIT_MASK(32);
228static struct at91_eth_data eth_data;
229
230static struct resource eth_resources[] = {
231 [0] = {
232 .start = AT91SAM9G45_BASE_EMAC,
233 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = AT91SAM9G45_ID_EMAC,
238 .end = AT91SAM9G45_ID_EMAC,
239 .flags = IORESOURCE_IRQ,
240 },
241};
242
243static struct platform_device at91sam9g45_eth_device = {
244 .name = "macb",
245 .id = -1,
246 .dev = {
247 .dma_mask = ð_dmamask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 .platform_data = ð_data,
250 },
251 .resource = eth_resources,
252 .num_resources = ARRAY_SIZE(eth_resources),
253};
254
255void __init at91_add_device_eth(struct at91_eth_data *data)
256{
257 if (!data)
258 return;
259
260 if (data->phy_irq_pin) {
261 at91_set_gpio_input(data->phy_irq_pin, 0);
262 at91_set_deglitch(data->phy_irq_pin, 1);
263 }
264
265
266 at91_set_A_periph(AT91_PIN_PA17, 0);
267 at91_set_A_periph(AT91_PIN_PA15, 0);
268 at91_set_A_periph(AT91_PIN_PA12, 0);
269 at91_set_A_periph(AT91_PIN_PA13, 0);
270 at91_set_A_periph(AT91_PIN_PA16, 0);
271 at91_set_A_periph(AT91_PIN_PA14, 0);
272 at91_set_A_periph(AT91_PIN_PA10, 0);
273 at91_set_A_periph(AT91_PIN_PA11, 0);
274 at91_set_A_periph(AT91_PIN_PA19, 0);
275 at91_set_A_periph(AT91_PIN_PA18, 0);
276
277 if (!data->is_rmii) {
278 at91_set_B_periph(AT91_PIN_PA29, 0);
279 at91_set_B_periph(AT91_PIN_PA30, 0);
280 at91_set_B_periph(AT91_PIN_PA8, 0);
281 at91_set_B_periph(AT91_PIN_PA9, 0);
282 at91_set_B_periph(AT91_PIN_PA28, 0);
283 at91_set_B_periph(AT91_PIN_PA6, 0);
284 at91_set_B_periph(AT91_PIN_PA7, 0);
285 at91_set_B_periph(AT91_PIN_PA27, 0);
286 }
287
288 eth_data = *data;
289 platform_device_register(&at91sam9g45_eth_device);
290}
291#else
292void __init at91_add_device_eth(struct at91_eth_data *data) {}
293#endif
294
295
296
297
298
299
300#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
301static struct atmel_nand_data nand_data;
302
303#define NAND_BASE AT91_CHIPSELECT_3
304
305static struct resource nand_resources[] = {
306 [0] = {
307 .start = NAND_BASE,
308 .end = NAND_BASE + SZ_256M - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = AT91_BASE_SYS + AT91_ECC,
313 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
314 .flags = IORESOURCE_MEM,
315 }
316};
317
318static struct platform_device at91sam9g45_nand_device = {
319 .name = "atmel_nand",
320 .id = -1,
321 .dev = {
322 .platform_data = &nand_data,
323 },
324 .resource = nand_resources,
325 .num_resources = ARRAY_SIZE(nand_resources),
326};
327
328void __init at91_add_device_nand(struct atmel_nand_data *data)
329{
330 unsigned long csa;
331
332 if (!data)
333 return;
334
335 csa = at91_sys_read(AT91_MATRIX_EBICSA);
336 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
337
338
339 if (data->enable_pin)
340 at91_set_gpio_output(data->enable_pin, 1);
341
342
343 if (data->rdy_pin)
344 at91_set_gpio_input(data->rdy_pin, 1);
345
346
347 if (data->det_pin)
348 at91_set_gpio_input(data->det_pin, 1);
349
350 nand_data = *data;
351 platform_device_register(&at91sam9g45_nand_device);
352}
353#else
354void __init at91_add_device_nand(struct atmel_nand_data *data) {}
355#endif
356
357
358
359
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361
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363
364
365
366
367#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
368static struct i2c_gpio_platform_data pdata_i2c0 = {
369 .sda_pin = AT91_PIN_PA20,
370 .sda_is_open_drain = 1,
371 .scl_pin = AT91_PIN_PA21,
372 .scl_is_open_drain = 1,
373 .udelay = 2,
374};
375
376static struct platform_device at91sam9g45_twi0_device = {
377 .name = "i2c-gpio",
378 .id = 0,
379 .dev.platform_data = &pdata_i2c0,
380};
381
382static struct i2c_gpio_platform_data pdata_i2c1 = {
383 .sda_pin = AT91_PIN_PB10,
384 .sda_is_open_drain = 1,
385 .scl_pin = AT91_PIN_PB11,
386 .scl_is_open_drain = 1,
387 .udelay = 2,
388};
389
390static struct platform_device at91sam9g45_twi1_device = {
391 .name = "i2c-gpio",
392 .id = 1,
393 .dev.platform_data = &pdata_i2c1,
394};
395
396void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
397{
398 i2c_register_board_info(i2c_id, devices, nr_devices);
399
400 if (i2c_id == 0) {
401 at91_set_GPIO_periph(AT91_PIN_PA20, 1);
402 at91_set_multi_drive(AT91_PIN_PA20, 1);
403
404 at91_set_GPIO_periph(AT91_PIN_PA21, 1);
405 at91_set_multi_drive(AT91_PIN_PA21, 1);
406
407 platform_device_register(&at91sam9g45_twi0_device);
408 } else {
409 at91_set_GPIO_periph(AT91_PIN_PB10, 1);
410 at91_set_multi_drive(AT91_PIN_PB10, 1);
411
412 at91_set_GPIO_periph(AT91_PIN_PB11, 1);
413 at91_set_multi_drive(AT91_PIN_PB11, 1);
414
415 platform_device_register(&at91sam9g45_twi1_device);
416 }
417}
418
419#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
420static struct resource twi0_resources[] = {
421 [0] = {
422 .start = AT91SAM9G45_BASE_TWI0,
423 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
424 .flags = IORESOURCE_MEM,
425 },
426 [1] = {
427 .start = AT91SAM9G45_ID_TWI0,
428 .end = AT91SAM9G45_ID_TWI0,
429 .flags = IORESOURCE_IRQ,
430 },
431};
432
433static struct platform_device at91sam9g45_twi0_device = {
434 .name = "at91_i2c",
435 .id = 0,
436 .resource = twi0_resources,
437 .num_resources = ARRAY_SIZE(twi0_resources),
438};
439
440static struct resource twi1_resources[] = {
441 [0] = {
442 .start = AT91SAM9G45_BASE_TWI1,
443 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 [1] = {
447 .start = AT91SAM9G45_ID_TWI1,
448 .end = AT91SAM9G45_ID_TWI1,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static struct platform_device at91sam9g45_twi1_device = {
454 .name = "at91_i2c",
455 .id = 1,
456 .resource = twi1_resources,
457 .num_resources = ARRAY_SIZE(twi1_resources),
458};
459
460void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
461{
462 i2c_register_board_info(i2c_id, devices, nr_devices);
463
464
465 if (i2c_id == 0) {
466 at91_set_A_periph(AT91_PIN_PA20, 0);
467 at91_set_multi_drive(AT91_PIN_PA20, 1);
468
469 at91_set_A_periph(AT91_PIN_PA21, 0);
470 at91_set_multi_drive(AT91_PIN_PA21, 1);
471
472 platform_device_register(&at91sam9g45_twi0_device);
473 } else {
474 at91_set_A_periph(AT91_PIN_PB10, 0);
475 at91_set_multi_drive(AT91_PIN_PB10, 1);
476
477 at91_set_A_periph(AT91_PIN_PB11, 0);
478 at91_set_multi_drive(AT91_PIN_PB11, 1);
479
480 platform_device_register(&at91sam9g45_twi1_device);
481 }
482}
483#else
484void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
485#endif
486
487
488
489
490
491
492#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
493static u64 spi_dmamask = DMA_BIT_MASK(32);
494
495static struct resource spi0_resources[] = {
496 [0] = {
497 .start = AT91SAM9G45_BASE_SPI0,
498 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
499 .flags = IORESOURCE_MEM,
500 },
501 [1] = {
502 .start = AT91SAM9G45_ID_SPI0,
503 .end = AT91SAM9G45_ID_SPI0,
504 .flags = IORESOURCE_IRQ,
505 },
506};
507
508static struct platform_device at91sam9g45_spi0_device = {
509 .name = "atmel_spi",
510 .id = 0,
511 .dev = {
512 .dma_mask = &spi_dmamask,
513 .coherent_dma_mask = DMA_BIT_MASK(32),
514 },
515 .resource = spi0_resources,
516 .num_resources = ARRAY_SIZE(spi0_resources),
517};
518
519static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
520
521static struct resource spi1_resources[] = {
522 [0] = {
523 .start = AT91SAM9G45_BASE_SPI1,
524 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = AT91SAM9G45_ID_SPI1,
529 .end = AT91SAM9G45_ID_SPI1,
530 .flags = IORESOURCE_IRQ,
531 },
532};
533
534static struct platform_device at91sam9g45_spi1_device = {
535 .name = "atmel_spi",
536 .id = 1,
537 .dev = {
538 .dma_mask = &spi_dmamask,
539 .coherent_dma_mask = DMA_BIT_MASK(32),
540 },
541 .resource = spi1_resources,
542 .num_resources = ARRAY_SIZE(spi1_resources),
543};
544
545static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
546
547void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
548{
549 int i;
550 unsigned long cs_pin;
551 short enable_spi0 = 0;
552 short enable_spi1 = 0;
553
554
555 for (i = 0; i < nr_devices; i++) {
556 if (devices[i].controller_data)
557 cs_pin = (unsigned long) devices[i].controller_data;
558 else if (devices[i].bus_num == 0)
559 cs_pin = spi0_standard_cs[devices[i].chip_select];
560 else
561 cs_pin = spi1_standard_cs[devices[i].chip_select];
562
563 if (devices[i].bus_num == 0)
564 enable_spi0 = 1;
565 else
566 enable_spi1 = 1;
567
568
569 at91_set_gpio_output(cs_pin, 1);
570
571
572 devices[i].controller_data = (void *) cs_pin;
573 }
574
575 spi_register_board_info(devices, nr_devices);
576
577
578 if (enable_spi0) {
579 at91_set_A_periph(AT91_PIN_PB0, 0);
580 at91_set_A_periph(AT91_PIN_PB1, 0);
581 at91_set_A_periph(AT91_PIN_PB2, 0);
582
583 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
584 platform_device_register(&at91sam9g45_spi0_device);
585 }
586 if (enable_spi1) {
587 at91_set_A_periph(AT91_PIN_PB14, 0);
588 at91_set_A_periph(AT91_PIN_PB15, 0);
589 at91_set_A_periph(AT91_PIN_PB16, 0);
590
591 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
592 platform_device_register(&at91sam9g45_spi1_device);
593 }
594}
595#else
596void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
597#endif
598
599
600
601
602
603
604#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
605static u64 ac97_dmamask = DMA_BIT_MASK(32);
606static struct ac97c_platform_data ac97_data;
607
608static struct resource ac97_resources[] = {
609 [0] = {
610 .start = AT91SAM9G45_BASE_AC97C,
611 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
612 .flags = IORESOURCE_MEM,
613 },
614 [1] = {
615 .start = AT91SAM9G45_ID_AC97C,
616 .end = AT91SAM9G45_ID_AC97C,
617 .flags = IORESOURCE_IRQ,
618 },
619};
620
621static struct platform_device at91sam9g45_ac97_device = {
622 .name = "atmel_ac97c",
623 .id = 0,
624 .dev = {
625 .dma_mask = &ac97_dmamask,
626 .coherent_dma_mask = DMA_BIT_MASK(32),
627 .platform_data = &ac97_data,
628 },
629 .resource = ac97_resources,
630 .num_resources = ARRAY_SIZE(ac97_resources),
631};
632
633void __init at91_add_device_ac97(struct ac97c_platform_data *data)
634{
635 if (!data)
636 return;
637
638 at91_set_A_periph(AT91_PIN_PD8, 0);
639 at91_set_A_periph(AT91_PIN_PD9, 0);
640 at91_set_A_periph(AT91_PIN_PD7, 0);
641 at91_set_A_periph(AT91_PIN_PD6, 0);
642
643
644 if (data->reset_pin)
645 at91_set_gpio_output(data->reset_pin, 0);
646
647 ac97_data = *data;
648 platform_device_register(&at91sam9g45_ac97_device);
649}
650#else
651void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
652#endif
653
654
655
656
657
658
659#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
660static u64 lcdc_dmamask = DMA_BIT_MASK(32);
661static struct atmel_lcdfb_info lcdc_data;
662
663static struct resource lcdc_resources[] = {
664 [0] = {
665 .start = AT91SAM9G45_LCDC_BASE,
666 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
667 .flags = IORESOURCE_MEM,
668 },
669 [1] = {
670 .start = AT91SAM9G45_ID_LCDC,
671 .end = AT91SAM9G45_ID_LCDC,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device at91_lcdc_device = {
677 .name = "atmel_lcdfb",
678 .id = 0,
679 .dev = {
680 .dma_mask = &lcdc_dmamask,
681 .coherent_dma_mask = DMA_BIT_MASK(32),
682 .platform_data = &lcdc_data,
683 },
684 .resource = lcdc_resources,
685 .num_resources = ARRAY_SIZE(lcdc_resources),
686};
687
688void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
689{
690 if (!data)
691 return;
692
693 at91_set_A_periph(AT91_PIN_PE0, 0);
694
695 at91_set_A_periph(AT91_PIN_PE2, 0);
696 at91_set_A_periph(AT91_PIN_PE3, 0);
697 at91_set_A_periph(AT91_PIN_PE4, 0);
698 at91_set_A_periph(AT91_PIN_PE5, 0);
699 at91_set_A_periph(AT91_PIN_PE6, 0);
700 at91_set_A_periph(AT91_PIN_PE7, 0);
701 at91_set_A_periph(AT91_PIN_PE8, 0);
702 at91_set_A_periph(AT91_PIN_PE9, 0);
703 at91_set_A_periph(AT91_PIN_PE10, 0);
704 at91_set_A_periph(AT91_PIN_PE11, 0);
705 at91_set_A_periph(AT91_PIN_PE12, 0);
706 at91_set_A_periph(AT91_PIN_PE13, 0);
707 at91_set_A_periph(AT91_PIN_PE14, 0);
708 at91_set_A_periph(AT91_PIN_PE15, 0);
709 at91_set_A_periph(AT91_PIN_PE16, 0);
710 at91_set_A_periph(AT91_PIN_PE17, 0);
711 at91_set_A_periph(AT91_PIN_PE18, 0);
712 at91_set_A_periph(AT91_PIN_PE19, 0);
713 at91_set_A_periph(AT91_PIN_PE20, 0);
714 at91_set_A_periph(AT91_PIN_PE21, 0);
715 at91_set_A_periph(AT91_PIN_PE22, 0);
716 at91_set_A_periph(AT91_PIN_PE23, 0);
717 at91_set_A_periph(AT91_PIN_PE24, 0);
718 at91_set_A_periph(AT91_PIN_PE25, 0);
719 at91_set_A_periph(AT91_PIN_PE26, 0);
720 at91_set_A_periph(AT91_PIN_PE27, 0);
721 at91_set_A_periph(AT91_PIN_PE28, 0);
722 at91_set_A_periph(AT91_PIN_PE29, 0);
723 at91_set_A_periph(AT91_PIN_PE30, 0);
724
725 lcdc_data = *data;
726 platform_device_register(&at91_lcdc_device);
727}
728#else
729void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
730#endif
731
732
733
734
735
736
737#ifdef CONFIG_ATMEL_TCLIB
738static struct resource tcb0_resources[] = {
739 [0] = {
740 .start = AT91SAM9G45_BASE_TCB0,
741 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
742 .flags = IORESOURCE_MEM,
743 },
744 [1] = {
745 .start = AT91SAM9G45_ID_TCB,
746 .end = AT91SAM9G45_ID_TCB,
747 .flags = IORESOURCE_IRQ,
748 },
749};
750
751static struct platform_device at91sam9g45_tcb0_device = {
752 .name = "atmel_tcb",
753 .id = 0,
754 .resource = tcb0_resources,
755 .num_resources = ARRAY_SIZE(tcb0_resources),
756};
757
758
759static struct resource tcb1_resources[] = {
760 [0] = {
761 .start = AT91SAM9G45_BASE_TCB1,
762 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
763 .flags = IORESOURCE_MEM,
764 },
765 [1] = {
766 .start = AT91SAM9G45_ID_TCB,
767 .end = AT91SAM9G45_ID_TCB,
768 .flags = IORESOURCE_IRQ,
769 },
770};
771
772static struct platform_device at91sam9g45_tcb1_device = {
773 .name = "atmel_tcb",
774 .id = 1,
775 .resource = tcb1_resources,
776 .num_resources = ARRAY_SIZE(tcb1_resources),
777};
778
779static void __init at91_add_device_tc(void)
780{
781
782 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
783 platform_device_register(&at91sam9g45_tcb0_device);
784 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
785 platform_device_register(&at91sam9g45_tcb1_device);
786}
787#else
788static void __init at91_add_device_tc(void) { }
789#endif
790
791
792
793
794
795
796#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
797static struct platform_device at91sam9g45_rtc_device = {
798 .name = "at91_rtc",
799 .id = -1,
800 .num_resources = 0,
801};
802
803static void __init at91_add_device_rtc(void)
804{
805 platform_device_register(&at91sam9g45_rtc_device);
806}
807#else
808static void __init at91_add_device_rtc(void) {}
809#endif
810
811
812
813
814
815
816static struct resource rtt_resources[] = {
817 {
818 .start = AT91_BASE_SYS + AT91_RTT,
819 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
820 .flags = IORESOURCE_MEM,
821 }
822};
823
824static struct platform_device at91sam9g45_rtt_device = {
825 .name = "at91_rtt",
826 .id = 0,
827 .resource = rtt_resources,
828 .num_resources = ARRAY_SIZE(rtt_resources),
829};
830
831static void __init at91_add_device_rtt(void)
832{
833 platform_device_register(&at91sam9g45_rtt_device);
834}
835
836
837
838
839
840
841#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
842static struct platform_device at91sam9g45_wdt_device = {
843 .name = "at91_wdt",
844 .id = -1,
845 .num_resources = 0,
846};
847
848static void __init at91_add_device_watchdog(void)
849{
850 platform_device_register(&at91sam9g45_wdt_device);
851}
852#else
853static void __init at91_add_device_watchdog(void) {}
854#endif
855
856
857
858
859
860
861#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
862static u32 pwm_mask;
863
864static struct resource pwm_resources[] = {
865 [0] = {
866 .start = AT91SAM9G45_BASE_PWMC,
867 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
868 .flags = IORESOURCE_MEM,
869 },
870 [1] = {
871 .start = AT91SAM9G45_ID_PWMC,
872 .end = AT91SAM9G45_ID_PWMC,
873 .flags = IORESOURCE_IRQ,
874 },
875};
876
877static struct platform_device at91sam9g45_pwm0_device = {
878 .name = "atmel_pwm",
879 .id = -1,
880 .dev = {
881 .platform_data = &pwm_mask,
882 },
883 .resource = pwm_resources,
884 .num_resources = ARRAY_SIZE(pwm_resources),
885};
886
887void __init at91_add_device_pwm(u32 mask)
888{
889 if (mask & (1 << AT91_PWM0))
890 at91_set_B_periph(AT91_PIN_PD24, 1);
891
892 if (mask & (1 << AT91_PWM1))
893 at91_set_B_periph(AT91_PIN_PD31, 1);
894
895 if (mask & (1 << AT91_PWM2))
896 at91_set_B_periph(AT91_PIN_PD26, 1);
897
898 if (mask & (1 << AT91_PWM3))
899 at91_set_B_periph(AT91_PIN_PD0, 1);
900
901 pwm_mask = mask;
902
903 platform_device_register(&at91sam9g45_pwm0_device);
904}
905#else
906void __init at91_add_device_pwm(u32 mask) {}
907#endif
908
909
910
911
912
913
914#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
915static u64 ssc0_dmamask = DMA_BIT_MASK(32);
916
917static struct resource ssc0_resources[] = {
918 [0] = {
919 .start = AT91SAM9G45_BASE_SSC0,
920 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
921 .flags = IORESOURCE_MEM,
922 },
923 [1] = {
924 .start = AT91SAM9G45_ID_SSC0,
925 .end = AT91SAM9G45_ID_SSC0,
926 .flags = IORESOURCE_IRQ,
927 },
928};
929
930static struct platform_device at91sam9g45_ssc0_device = {
931 .name = "ssc",
932 .id = 0,
933 .dev = {
934 .dma_mask = &ssc0_dmamask,
935 .coherent_dma_mask = DMA_BIT_MASK(32),
936 },
937 .resource = ssc0_resources,
938 .num_resources = ARRAY_SIZE(ssc0_resources),
939};
940
941static inline void configure_ssc0_pins(unsigned pins)
942{
943 if (pins & ATMEL_SSC_TF)
944 at91_set_A_periph(AT91_PIN_PD1, 1);
945 if (pins & ATMEL_SSC_TK)
946 at91_set_A_periph(AT91_PIN_PD0, 1);
947 if (pins & ATMEL_SSC_TD)
948 at91_set_A_periph(AT91_PIN_PD2, 1);
949 if (pins & ATMEL_SSC_RD)
950 at91_set_A_periph(AT91_PIN_PD3, 1);
951 if (pins & ATMEL_SSC_RK)
952 at91_set_A_periph(AT91_PIN_PD4, 1);
953 if (pins & ATMEL_SSC_RF)
954 at91_set_A_periph(AT91_PIN_PD5, 1);
955}
956
957static u64 ssc1_dmamask = DMA_BIT_MASK(32);
958
959static struct resource ssc1_resources[] = {
960 [0] = {
961 .start = AT91SAM9G45_BASE_SSC1,
962 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
963 .flags = IORESOURCE_MEM,
964 },
965 [1] = {
966 .start = AT91SAM9G45_ID_SSC1,
967 .end = AT91SAM9G45_ID_SSC1,
968 .flags = IORESOURCE_IRQ,
969 },
970};
971
972static struct platform_device at91sam9g45_ssc1_device = {
973 .name = "ssc",
974 .id = 1,
975 .dev = {
976 .dma_mask = &ssc1_dmamask,
977 .coherent_dma_mask = DMA_BIT_MASK(32),
978 },
979 .resource = ssc1_resources,
980 .num_resources = ARRAY_SIZE(ssc1_resources),
981};
982
983static inline void configure_ssc1_pins(unsigned pins)
984{
985 if (pins & ATMEL_SSC_TF)
986 at91_set_A_periph(AT91_PIN_PD14, 1);
987 if (pins & ATMEL_SSC_TK)
988 at91_set_A_periph(AT91_PIN_PD12, 1);
989 if (pins & ATMEL_SSC_TD)
990 at91_set_A_periph(AT91_PIN_PD10, 1);
991 if (pins & ATMEL_SSC_RD)
992 at91_set_A_periph(AT91_PIN_PD11, 1);
993 if (pins & ATMEL_SSC_RK)
994 at91_set_A_periph(AT91_PIN_PD13, 1);
995 if (pins & ATMEL_SSC_RF)
996 at91_set_A_periph(AT91_PIN_PD15, 1);
997}
998
999
1000
1001
1002
1003
1004
1005void __init at91_add_device_ssc(unsigned id, unsigned pins)
1006{
1007 struct platform_device *pdev;
1008
1009
1010
1011
1012
1013 switch (id) {
1014 case AT91SAM9G45_ID_SSC0:
1015 pdev = &at91sam9g45_ssc0_device;
1016 configure_ssc0_pins(pins);
1017 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1018 break;
1019 case AT91SAM9G45_ID_SSC1:
1020 pdev = &at91sam9g45_ssc1_device;
1021 configure_ssc1_pins(pins);
1022 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1023 break;
1024 default:
1025 return;
1026 }
1027
1028 platform_device_register(pdev);
1029}
1030
1031#else
1032void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1033#endif
1034
1035
1036
1037
1038
1039
1040#if defined(CONFIG_SERIAL_ATMEL)
1041static struct resource dbgu_resources[] = {
1042 [0] = {
1043 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1044 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1045 .flags = IORESOURCE_MEM,
1046 },
1047 [1] = {
1048 .start = AT91_ID_SYS,
1049 .end = AT91_ID_SYS,
1050 .flags = IORESOURCE_IRQ,
1051 },
1052};
1053
1054static struct atmel_uart_data dbgu_data = {
1055 .use_dma_tx = 0,
1056 .use_dma_rx = 0,
1057 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1058};
1059
1060static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1061
1062static struct platform_device at91sam9g45_dbgu_device = {
1063 .name = "atmel_usart",
1064 .id = 0,
1065 .dev = {
1066 .dma_mask = &dbgu_dmamask,
1067 .coherent_dma_mask = DMA_BIT_MASK(32),
1068 .platform_data = &dbgu_data,
1069 },
1070 .resource = dbgu_resources,
1071 .num_resources = ARRAY_SIZE(dbgu_resources),
1072};
1073
1074static inline void configure_dbgu_pins(void)
1075{
1076 at91_set_A_periph(AT91_PIN_PB12, 0);
1077 at91_set_A_periph(AT91_PIN_PB13, 1);
1078}
1079
1080static struct resource uart0_resources[] = {
1081 [0] = {
1082 .start = AT91SAM9G45_BASE_US0,
1083 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1084 .flags = IORESOURCE_MEM,
1085 },
1086 [1] = {
1087 .start = AT91SAM9G45_ID_US0,
1088 .end = AT91SAM9G45_ID_US0,
1089 .flags = IORESOURCE_IRQ,
1090 },
1091};
1092
1093static struct atmel_uart_data uart0_data = {
1094 .use_dma_tx = 1,
1095 .use_dma_rx = 1,
1096};
1097
1098static u64 uart0_dmamask = DMA_BIT_MASK(32);
1099
1100static struct platform_device at91sam9g45_uart0_device = {
1101 .name = "atmel_usart",
1102 .id = 1,
1103 .dev = {
1104 .dma_mask = &uart0_dmamask,
1105 .coherent_dma_mask = DMA_BIT_MASK(32),
1106 .platform_data = &uart0_data,
1107 },
1108 .resource = uart0_resources,
1109 .num_resources = ARRAY_SIZE(uart0_resources),
1110};
1111
1112static inline void configure_usart0_pins(unsigned pins)
1113{
1114 at91_set_A_periph(AT91_PIN_PB19, 1);
1115 at91_set_A_periph(AT91_PIN_PB18, 0);
1116
1117 if (pins & ATMEL_UART_RTS)
1118 at91_set_B_periph(AT91_PIN_PB17, 0);
1119 if (pins & ATMEL_UART_CTS)
1120 at91_set_B_periph(AT91_PIN_PB15, 0);
1121}
1122
1123static struct resource uart1_resources[] = {
1124 [0] = {
1125 .start = AT91SAM9G45_BASE_US1,
1126 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1127 .flags = IORESOURCE_MEM,
1128 },
1129 [1] = {
1130 .start = AT91SAM9G45_ID_US1,
1131 .end = AT91SAM9G45_ID_US1,
1132 .flags = IORESOURCE_IRQ,
1133 },
1134};
1135
1136static struct atmel_uart_data uart1_data = {
1137 .use_dma_tx = 1,
1138 .use_dma_rx = 1,
1139};
1140
1141static u64 uart1_dmamask = DMA_BIT_MASK(32);
1142
1143static struct platform_device at91sam9g45_uart1_device = {
1144 .name = "atmel_usart",
1145 .id = 2,
1146 .dev = {
1147 .dma_mask = &uart1_dmamask,
1148 .coherent_dma_mask = DMA_BIT_MASK(32),
1149 .platform_data = &uart1_data,
1150 },
1151 .resource = uart1_resources,
1152 .num_resources = ARRAY_SIZE(uart1_resources),
1153};
1154
1155static inline void configure_usart1_pins(unsigned pins)
1156{
1157 at91_set_A_periph(AT91_PIN_PB4, 1);
1158 at91_set_A_periph(AT91_PIN_PB5, 0);
1159
1160 if (pins & ATMEL_UART_RTS)
1161 at91_set_A_periph(AT91_PIN_PD16, 0);
1162 if (pins & ATMEL_UART_CTS)
1163 at91_set_A_periph(AT91_PIN_PD17, 0);
1164}
1165
1166static struct resource uart2_resources[] = {
1167 [0] = {
1168 .start = AT91SAM9G45_BASE_US2,
1169 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1170 .flags = IORESOURCE_MEM,
1171 },
1172 [1] = {
1173 .start = AT91SAM9G45_ID_US2,
1174 .end = AT91SAM9G45_ID_US2,
1175 .flags = IORESOURCE_IRQ,
1176 },
1177};
1178
1179static struct atmel_uart_data uart2_data = {
1180 .use_dma_tx = 1,
1181 .use_dma_rx = 1,
1182};
1183
1184static u64 uart2_dmamask = DMA_BIT_MASK(32);
1185
1186static struct platform_device at91sam9g45_uart2_device = {
1187 .name = "atmel_usart",
1188 .id = 3,
1189 .dev = {
1190 .dma_mask = &uart2_dmamask,
1191 .coherent_dma_mask = DMA_BIT_MASK(32),
1192 .platform_data = &uart2_data,
1193 },
1194 .resource = uart2_resources,
1195 .num_resources = ARRAY_SIZE(uart2_resources),
1196};
1197
1198static inline void configure_usart2_pins(unsigned pins)
1199{
1200 at91_set_A_periph(AT91_PIN_PB6, 1);
1201 at91_set_A_periph(AT91_PIN_PB7, 0);
1202
1203 if (pins & ATMEL_UART_RTS)
1204 at91_set_B_periph(AT91_PIN_PC9, 0);
1205 if (pins & ATMEL_UART_CTS)
1206 at91_set_B_periph(AT91_PIN_PC11, 0);
1207}
1208
1209static struct resource uart3_resources[] = {
1210 [0] = {
1211 .start = AT91SAM9G45_BASE_US3,
1212 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1213 .flags = IORESOURCE_MEM,
1214 },
1215 [1] = {
1216 .start = AT91SAM9G45_ID_US3,
1217 .end = AT91SAM9G45_ID_US3,
1218 .flags = IORESOURCE_IRQ,
1219 },
1220};
1221
1222static struct atmel_uart_data uart3_data = {
1223 .use_dma_tx = 1,
1224 .use_dma_rx = 1,
1225};
1226
1227static u64 uart3_dmamask = DMA_BIT_MASK(32);
1228
1229static struct platform_device at91sam9g45_uart3_device = {
1230 .name = "atmel_usart",
1231 .id = 4,
1232 .dev = {
1233 .dma_mask = &uart3_dmamask,
1234 .coherent_dma_mask = DMA_BIT_MASK(32),
1235 .platform_data = &uart3_data,
1236 },
1237 .resource = uart3_resources,
1238 .num_resources = ARRAY_SIZE(uart3_resources),
1239};
1240
1241static inline void configure_usart3_pins(unsigned pins)
1242{
1243 at91_set_A_periph(AT91_PIN_PB8, 1);
1244 at91_set_A_periph(AT91_PIN_PB9, 0);
1245
1246 if (pins & ATMEL_UART_RTS)
1247 at91_set_B_periph(AT91_PIN_PA23, 0);
1248 if (pins & ATMEL_UART_CTS)
1249 at91_set_B_periph(AT91_PIN_PA24, 0);
1250}
1251
1252static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];
1253struct platform_device *atmel_default_console_device;
1254
1255void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1256{
1257 struct platform_device *pdev;
1258
1259 switch (id) {
1260 case 0:
1261 pdev = &at91sam9g45_dbgu_device;
1262 configure_dbgu_pins();
1263 at91_clock_associate("mck", &pdev->dev, "usart");
1264 break;
1265 case AT91SAM9G45_ID_US0:
1266 pdev = &at91sam9g45_uart0_device;
1267 configure_usart0_pins(pins);
1268 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1269 break;
1270 case AT91SAM9G45_ID_US1:
1271 pdev = &at91sam9g45_uart1_device;
1272 configure_usart1_pins(pins);
1273 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1274 break;
1275 case AT91SAM9G45_ID_US2:
1276 pdev = &at91sam9g45_uart2_device;
1277 configure_usart2_pins(pins);
1278 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1279 break;
1280 case AT91SAM9G45_ID_US3:
1281 pdev = &at91sam9g45_uart3_device;
1282 configure_usart3_pins(pins);
1283 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1284 break;
1285 default:
1286 return;
1287 }
1288 pdev->id = portnr;
1289
1290 if (portnr < ATMEL_MAX_UART)
1291 at91_uarts[portnr] = pdev;
1292}
1293
1294void __init at91_set_serial_console(unsigned portnr)
1295{
1296 if (portnr < ATMEL_MAX_UART)
1297 atmel_default_console_device = at91_uarts[portnr];
1298}
1299
1300void __init at91_add_device_serial(void)
1301{
1302 int i;
1303
1304 for (i = 0; i < ATMEL_MAX_UART; i++) {
1305 if (at91_uarts[i])
1306 platform_device_register(at91_uarts[i]);
1307 }
1308
1309 if (!atmel_default_console_device)
1310 printk(KERN_INFO "AT91: No default serial console defined.\n");
1311}
1312#else
1313void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1314void __init at91_set_serial_console(unsigned portnr) {}
1315void __init at91_add_device_serial(void) {}
1316#endif
1317
1318
1319
1320
1321
1322
1323
1324static int __init at91_add_standard_devices(void)
1325{
1326 at91_add_device_hdmac();
1327 at91_add_device_rtc();
1328 at91_add_device_rtt();
1329 at91_add_device_watchdog();
1330 at91_add_device_tc();
1331 return 0;
1332}
1333
1334arch_initcall(at91_add_standard_devices);
1335
