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13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <mach/at91_pmc.h>
29#include <mach/cpu.h>
30
31#include "clock.h"
32
33
34
35
36
37
38
39
40#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
41#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
42#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
43#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
44
45
46
47
48
49#define cpu_has_utmi() ( cpu_is_at91cap9() \
50 || cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9g45())
52
53#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
54 || cpu_is_at91sam9g45())
55
56#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
57
58#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
59 || cpu_is_at91sam9g45()))
60
61#define cpu_has_upll() (cpu_is_at91sam9g45())
62
63
64#define cpu_has_uhp() (!cpu_is_at91sam9rl())
65
66
67#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
68 || cpu_is_at91sam9g45()))
69
70static LIST_HEAD(clocks);
71static DEFINE_SPINLOCK(clk_lock);
72
73static u32 at91_pllb_usb_init;
74
75
76
77
78
79
80
81static struct clk clk32k = {
82 .name = "clk32k",
83 .rate_hz = AT91_SLOW_CLOCK,
84 .users = 1,
85 .id = 0,
86 .type = CLK_TYPE_PRIMARY,
87};
88static struct clk main_clk = {
89 .name = "main",
90 .pmc_mask = AT91_PMC_MOSCS,
91 .id = 1,
92 .type = CLK_TYPE_PRIMARY,
93};
94static struct clk plla = {
95 .name = "plla",
96 .parent = &main_clk,
97 .pmc_mask = AT91_PMC_LOCKA,
98 .id = 2,
99 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
100};
101
102static void pllb_mode(struct clk *clk, int is_on)
103{
104 u32 value;
105
106 if (is_on) {
107 is_on = AT91_PMC_LOCKB;
108 value = at91_pllb_usb_init;
109 } else
110 value = 0;
111
112
113 at91_sys_write(AT91_CKGR_PLLBR, value);
114
115 do {
116 cpu_relax();
117 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
118}
119
120static struct clk pllb = {
121 .name = "pllb",
122 .parent = &main_clk,
123 .pmc_mask = AT91_PMC_LOCKB,
124 .mode = pllb_mode,
125 .id = 3,
126 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
127};
128
129static void pmc_sys_mode(struct clk *clk, int is_on)
130{
131 if (is_on)
132 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
133 else
134 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
135}
136
137static void pmc_uckr_mode(struct clk *clk, int is_on)
138{
139 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
140
141 if (cpu_is_at91sam9g45()) {
142 if (is_on)
143 uckr |= AT91_PMC_BIASEN;
144 else
145 uckr &= ~AT91_PMC_BIASEN;
146 }
147
148 if (is_on) {
149 is_on = AT91_PMC_LOCKU;
150 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
151 } else
152 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
153
154 do {
155 cpu_relax();
156 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
157}
158
159
160static struct clk udpck = {
161 .name = "udpck",
162 .parent = &pllb,
163 .mode = pmc_sys_mode,
164};
165static struct clk utmi_clk = {
166 .name = "utmi_clk",
167 .parent = &main_clk,
168 .pmc_mask = AT91_PMC_UPLLEN,
169 .mode = pmc_uckr_mode,
170 .type = CLK_TYPE_PLL,
171};
172static struct clk uhpck = {
173 .name = "uhpck",
174
175 .mode = pmc_sys_mode,
176};
177
178
179
180
181
182
183
184static struct clk mck = {
185 .name = "mck",
186 .pmc_mask = AT91_PMC_MCKRDY,
187};
188
189static void pmc_periph_mode(struct clk *clk, int is_on)
190{
191 if (is_on)
192 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
193 else
194 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
195}
196
197static struct clk __init *at91_css_to_clk(unsigned long css)
198{
199 switch (css) {
200 case AT91_PMC_CSS_SLOW:
201 return &clk32k;
202 case AT91_PMC_CSS_MAIN:
203 return &main_clk;
204 case AT91_PMC_CSS_PLLA:
205 return &plla;
206 case AT91_PMC_CSS_PLLB:
207 if (cpu_has_upll())
208
209 return &utmi_clk;
210 else if (cpu_has_pllb())
211 return &pllb;
212 }
213
214 return NULL;
215}
216
217
218
219
220
221
222void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
223{
224 struct clk *clk = clk_get(NULL, id);
225
226 if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
227 return;
228
229 clk->function = func;
230 clk->dev = dev;
231}
232
233
234struct clk *clk_get(struct device *dev, const char *id)
235{
236 struct clk *clk;
237
238 list_for_each_entry(clk, &clocks, node) {
239 if (strcmp(id, clk->name) == 0)
240 return clk;
241 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
242 return clk;
243 }
244
245 return ERR_PTR(-ENOENT);
246}
247EXPORT_SYMBOL(clk_get);
248
249void clk_put(struct clk *clk)
250{
251}
252EXPORT_SYMBOL(clk_put);
253
254static void __clk_enable(struct clk *clk)
255{
256 if (clk->parent)
257 __clk_enable(clk->parent);
258 if (clk->users++ == 0 && clk->mode)
259 clk->mode(clk, 1);
260}
261
262int clk_enable(struct clk *clk)
263{
264 unsigned long flags;
265
266 spin_lock_irqsave(&clk_lock, flags);
267 __clk_enable(clk);
268 spin_unlock_irqrestore(&clk_lock, flags);
269 return 0;
270}
271EXPORT_SYMBOL(clk_enable);
272
273static void __clk_disable(struct clk *clk)
274{
275 BUG_ON(clk->users == 0);
276 if (--clk->users == 0 && clk->mode)
277 clk->mode(clk, 0);
278 if (clk->parent)
279 __clk_disable(clk->parent);
280}
281
282void clk_disable(struct clk *clk)
283{
284 unsigned long flags;
285
286 spin_lock_irqsave(&clk_lock, flags);
287 __clk_disable(clk);
288 spin_unlock_irqrestore(&clk_lock, flags);
289}
290EXPORT_SYMBOL(clk_disable);
291
292unsigned long clk_get_rate(struct clk *clk)
293{
294 unsigned long flags;
295 unsigned long rate;
296
297 spin_lock_irqsave(&clk_lock, flags);
298 for (;;) {
299 rate = clk->rate_hz;
300 if (rate || !clk->parent)
301 break;
302 clk = clk->parent;
303 }
304 spin_unlock_irqrestore(&clk_lock, flags);
305 return rate;
306}
307EXPORT_SYMBOL(clk_get_rate);
308
309
310
311#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
312
313
314
315
316
317
318
319
320long clk_round_rate(struct clk *clk, unsigned long rate)
321{
322 unsigned long flags;
323 unsigned prescale;
324 unsigned long actual;
325 unsigned long prev = ULONG_MAX;
326
327 if (!clk_is_programmable(clk))
328 return -EINVAL;
329 spin_lock_irqsave(&clk_lock, flags);
330
331 actual = clk->parent->rate_hz;
332 for (prescale = 0; prescale < 7; prescale++) {
333 if (actual > rate)
334 prev = actual;
335
336 if (actual && actual <= rate) {
337 if ((prev - rate) < (rate - actual)) {
338 actual = prev;
339 prescale--;
340 }
341 break;
342 }
343 actual >>= 1;
344 }
345
346 spin_unlock_irqrestore(&clk_lock, flags);
347 return (prescale < 7) ? actual : -ENOENT;
348}
349EXPORT_SYMBOL(clk_round_rate);
350
351int clk_set_rate(struct clk *clk, unsigned long rate)
352{
353 unsigned long flags;
354 unsigned prescale;
355 unsigned long actual;
356
357 if (!clk_is_programmable(clk))
358 return -EINVAL;
359 if (clk->users)
360 return -EBUSY;
361 spin_lock_irqsave(&clk_lock, flags);
362
363 actual = clk->parent->rate_hz;
364 for (prescale = 0; prescale < 7; prescale++) {
365 if (actual && actual <= rate) {
366 u32 pckr;
367
368 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
369 pckr &= AT91_PMC_CSS;
370 pckr |= prescale << 2;
371 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
372 clk->rate_hz = actual;
373 break;
374 }
375 actual >>= 1;
376 }
377
378 spin_unlock_irqrestore(&clk_lock, flags);
379 return (prescale < 7) ? actual : -ENOENT;
380}
381EXPORT_SYMBOL(clk_set_rate);
382
383struct clk *clk_get_parent(struct clk *clk)
384{
385 return clk->parent;
386}
387EXPORT_SYMBOL(clk_get_parent);
388
389int clk_set_parent(struct clk *clk, struct clk *parent)
390{
391 unsigned long flags;
392
393 if (clk->users)
394 return -EBUSY;
395 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
396 return -EINVAL;
397
398 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
399 return -EINVAL;
400
401 spin_lock_irqsave(&clk_lock, flags);
402
403 clk->rate_hz = parent->rate_hz;
404 clk->parent = parent;
405 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
406
407 spin_unlock_irqrestore(&clk_lock, flags);
408 return 0;
409}
410EXPORT_SYMBOL(clk_set_parent);
411
412
413static void __init init_programmable_clock(struct clk *clk)
414{
415 struct clk *parent;
416 u32 pckr;
417
418 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
419 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
420 clk->parent = parent;
421 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
422}
423
424#endif
425
426
427
428#ifdef CONFIG_DEBUG_FS
429
430static int at91_clk_show(struct seq_file *s, void *unused)
431{
432 u32 scsr, pcsr, uckr = 0, sr;
433 struct clk *clk;
434
435 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
436 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
437 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
438 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
439 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
440 if (cpu_has_pllb())
441 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
442 if (cpu_has_utmi())
443 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
444 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
445 if (cpu_has_upll())
446 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
447 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
448
449 seq_printf(s, "\n");
450
451 list_for_each_entry(clk, &clocks, node) {
452 char *state;
453
454 if (clk->mode == pmc_sys_mode)
455 state = (scsr & clk->pmc_mask) ? "on" : "off";
456 else if (clk->mode == pmc_periph_mode)
457 state = (pcsr & clk->pmc_mask) ? "on" : "off";
458 else if (clk->mode == pmc_uckr_mode)
459 state = (uckr & clk->pmc_mask) ? "on" : "off";
460 else if (clk->pmc_mask)
461 state = (sr & clk->pmc_mask) ? "on" : "off";
462 else if (clk == &clk32k || clk == &main_clk)
463 state = "on";
464 else
465 state = "";
466
467 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
468 clk->name, clk->users, state, clk_get_rate(clk),
469 clk->parent ? clk->parent->name : "");
470 }
471 return 0;
472}
473
474static int at91_clk_open(struct inode *inode, struct file *file)
475{
476 return single_open(file, at91_clk_show, NULL);
477}
478
479static const struct file_operations at91_clk_operations = {
480 .open = at91_clk_open,
481 .read = seq_read,
482 .llseek = seq_lseek,
483 .release = single_release,
484};
485
486static int __init at91_clk_debugfs_init(void)
487{
488
489 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
490
491 return 0;
492}
493postcore_initcall(at91_clk_debugfs_init);
494
495#endif
496
497
498
499
500int __init clk_register(struct clk *clk)
501{
502 if (clk_is_peripheral(clk)) {
503 clk->parent = &mck;
504 clk->mode = pmc_periph_mode;
505 list_add_tail(&clk->node, &clocks);
506 }
507 else if (clk_is_sys(clk)) {
508 clk->parent = &mck;
509 clk->mode = pmc_sys_mode;
510
511 list_add_tail(&clk->node, &clocks);
512 }
513#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
514 else if (clk_is_programmable(clk)) {
515 clk->mode = pmc_sys_mode;
516 init_programmable_clock(clk);
517 list_add_tail(&clk->node, &clocks);
518 }
519#endif
520
521 return 0;
522}
523
524
525
526
527static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
528{
529 unsigned mul, div;
530
531 div = reg & 0xff;
532 mul = (reg >> 16) & 0x7ff;
533 if (div && mul) {
534 freq /= div;
535 freq *= mul + 1;
536 } else
537 freq = 0;
538
539 return freq;
540}
541
542static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
543{
544 if (pll == &pllb && (reg & AT91_PMC_USB96M))
545 return freq / 2;
546 else
547 return freq;
548}
549
550static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
551{
552 unsigned i, div = 0, mul = 0, diff = 1 << 30;
553 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
554
555
556 if (out_freq > 240000000)
557 goto fail;
558
559 for (i = 1; i < 256; i++) {
560 int diff1;
561 unsigned input, mul1;
562
563
564
565
566
567
568 input = main_freq / i;
569 if (cpu_is_at91sam9g20() && input < 2000000)
570 continue;
571 if (input < 100000)
572 continue;
573 if (input > 32000000)
574 continue;
575
576 mul1 = out_freq / input;
577 if (cpu_is_at91sam9g20() && mul > 63)
578 continue;
579 if (mul1 > 2048)
580 continue;
581 if (mul1 < 2)
582 goto fail;
583
584 diff1 = out_freq - input * mul1;
585 if (diff1 < 0)
586 diff1 = -diff1;
587 if (diff > diff1) {
588 diff = diff1;
589 div = i;
590 mul = mul1;
591 if (diff == 0)
592 break;
593 }
594 }
595 if (i == 256 && diff > (out_freq >> 5))
596 goto fail;
597 return ret | ((mul - 1) << 16) | div;
598fail:
599 return 0;
600}
601
602static struct clk *const standard_pmc_clocks[] __initdata = {
603
604 &clk32k,
605 &main_clk,
606 &plla,
607
608
609 &mck
610};
611
612
613static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
614{
615
616
617
618
619
620
621 uhpck.parent = &pllb;
622
623 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
624 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
625 if (cpu_is_at91rm9200()) {
626 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
627 udpck.pmc_mask = AT91RM9200_PMC_UDP;
628 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
629 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
630 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
631 cpu_is_at91sam9g10()) {
632 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
633 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
634 } else if (cpu_is_at91cap9()) {
635 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
636 }
637 at91_sys_write(AT91_CKGR_PLLBR, 0);
638
639 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
640 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
641}
642
643
644static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
645{
646
647
648
649 unsigned int usbr = AT91_PMC_USBS_UPLL;
650
651
652 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
653
654 at91_sys_write(AT91_PMC_USB, usbr);
655
656
657 uhpck.parent = &utmi_clk;
658 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
659 uhpck.rate_hz = utmi_clk.parent->rate_hz;
660 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
661}
662
663int __init at91_clock_init(unsigned long main_clock)
664{
665 unsigned tmp, freq, mckr;
666 int i;
667 int pll_overclock = false;
668
669
670
671
672
673
674
675 if (!main_clock) {
676 do {
677 tmp = at91_sys_read(AT91_CKGR_MCFR);
678 } while (!(tmp & AT91_PMC_MAINRDY));
679 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
680 }
681 main_clk.rate_hz = main_clock;
682
683
684 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
685 if (cpu_has_300M_plla()) {
686 if (plla.rate_hz > 300000000)
687 pll_overclock = true;
688 } else if (cpu_has_800M_plla()) {
689 if (plla.rate_hz > 800000000)
690 pll_overclock = true;
691 } else {
692 if (plla.rate_hz > 209000000)
693 pll_overclock = true;
694 }
695 if (pll_overclock)
696 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
697
698 if (cpu_is_at91sam9g45()) {
699 mckr = at91_sys_read(AT91_PMC_MCKR);
700 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));
701 }
702
703 if (!cpu_has_pllb() && cpu_has_upll()) {
704
705
706 utmi_clk.type |= CLK_TYPE_PRIMARY;
707 utmi_clk.id = 3;
708 }
709
710
711
712
713
714 if (cpu_has_utmi())
715
716
717
718
719 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
720
721
722
723
724 if (cpu_has_pllb())
725 at91_pllb_usbfs_clock_init(main_clock);
726 if (cpu_has_upll())
727
728 at91_upll_usbfs_clock_init(main_clock);
729
730
731
732
733
734 mckr = at91_sys_read(AT91_PMC_MCKR);
735 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
736 freq = mck.parent->rate_hz;
737 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));
738 if (cpu_is_at91rm9200()) {
739 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));
740 } else if (cpu_is_at91sam9g20()) {
741 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
742 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;
743 if (mckr & AT91_PMC_PDIV)
744 freq /= 2;
745 } else if (cpu_is_at91sam9g45()) {
746 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
747 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
748 } else {
749 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
750 }
751
752
753 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
754 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
755
756 if (cpu_has_pllb())
757 list_add_tail(&pllb.node, &clocks);
758
759 if (cpu_has_uhp())
760 list_add_tail(&uhpck.node, &clocks);
761
762 if (cpu_has_udpfs())
763 list_add_tail(&udpck.node, &clocks);
764
765 if (cpu_has_utmi())
766 list_add_tail(&utmi_clk.node, &clocks);
767
768
769 clk_enable(&mck);
770
771 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
772 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
773 (unsigned) main_clock / 1000000,
774 ((unsigned) main_clock % 1000000) / 1000);
775
776 return 0;
777}
778
779
780
781
782static int __init at91_clock_reset(void)
783{
784 unsigned long pcdr = 0;
785 unsigned long scdr = 0;
786 struct clk *clk;
787
788 list_for_each_entry(clk, &clocks, node) {
789 if (clk->users > 0)
790 continue;
791
792 if (clk->mode == pmc_periph_mode)
793 pcdr |= clk->pmc_mask;
794
795 if (clk->mode == pmc_sys_mode)
796 scdr |= clk->pmc_mask;
797
798 pr_debug("Clocks: disable unused %s\n", clk->name);
799 }
800
801 at91_sys_write(AT91_PMC_PCDR, pcdr);
802 at91_sys_write(AT91_PMC_SCDR, scdr);
803
804 return 0;
805}
806late_initcall(at91_clock_reset);
807